Adder–subtractor
An adder–subtractor is a combinational digital circuit that performs both binary addition and subtraction of two multi-bit unsigned or signed numbers using a shared set of full adders controlled by a single mode input signal.[1] This design leverages the principle that subtraction can be achieved by adding the two's complement of the subtrahend, allowing efficient implementation without separate adder and subtractor hardware.[2] The core structure of an adder–subtractor consists of n full adders for n-bit operands, where each full adder's B input is passed through an exclusive-OR (XOR) gate with the mode signal M.[1] When M = 0 (addition mode), the XOR gates pass the B bits unchanged, the initial carry-in C0 is set to 0, and the circuit computes the sum A + B, producing sum bits and an overflow carry-out.[1] In subtraction mode (M = 1), the XOR gates invert the B bits to form B', C0 is set to 1, and the circuit adds A + (B' + 1), which equals A – B in two's complement arithmetic.[1] For unsigned numbers, the result is A – B if A ≥ B; otherwise, it yields the two's complement of (B – A), requiring a separate comparison for sign interpretation.[1] Adder–subtractors form a key component of arithmetic logic units (ALUs) in microprocessors and are implemented in various forms, such as ripple-carry for simplicity or parallel-prefix (e.g., carry-lookahead) for reduced propagation delay in high-speed applications.[2] They support fixed-point arithmetic in computer architecture, handling both positive and negative values without overflow in properly ranged operations.[1]Fundamentals
Binary Arithmetic Operations
Binary addition is performed bit by bit, starting from the least significant bit (LSB), similar to decimal addition but using base-2 arithmetic where digits are only 0 or 1. When adding two bits, if both are 0, the sum is 0 with no carry; if one is 1 and the other 0, the sum is 1 with no carry; if both are 1, the sum bit is 0 and a carry of 1 is generated to the next higher bit position. This carry may propagate through subsequent bits, potentially causing a chain reaction if multiple consecutive bits sum to 2 (i.e., 1 + 1 with incoming carry). For multi-bit numbers, the process repeats across all positions, with the final carry out indicating overflow if the result exceeds the bit width.[3][4] Consider the example of adding the 3-bit binary numbers 101 (decimal 5) and 011 (decimal 3). Starting from the LSB: 1 + 1 = 0 with carry 1; next, 0 + 1 + carry 1 = 0 with carry 1; then, 1 + 0 + carry 1 = 0 with carry 1 out, resulting in 1000 (decimal 8). This illustrates carry generation at the LSB and propagation through the higher bits.[3] Key concepts in binary addition include the sum bit, which represents the result modulo 2 at each position, and the carry signal, a binary (0 or 1) value indicating whether a 2 was exceeded, passed to the next bit. These operate in standard 0/1 logic, where 0 denotes false/low and 1 true/high. For a single-bit addition (half adder), the truth table is as follows:| A | B | Sum (A ⊕ B) | Carry (A ∧ B) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| A | B | Difference (A ⊕ B) | Borrow (¬A ∧ B) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
Complement Methods for Subtraction
Complement methods for subtraction transform the operation into an addition by representing the subtrahend's negation, allowing the reuse of existing adder circuitry in digital systems. These techniques are fundamental in binary arithmetic, where direct subtraction is avoided to simplify hardware design. The two primary approaches are one's complement and two's complement, each handling negative values differently during the addition process.[9] One's complement negation is achieved by inverting all bits of the subtrahend through a bitwise NOT operation, effectively representing the negative value. To perform subtraction of B from A (A - B), the one's complement of B is added to A using standard binary addition, including an end-around carry where the overflow bit is added back to the least significant bit if present. This method ensures the result accounts for the negation but introduces complexity due to the need for carry adjustment. For example, in a 3-bit system, subtracting 011 (3) from 101 (5): the one's complement of 011 is 100 (-3), adding 101 + 100 yields 1001, and applying the end-around carry (adding the overflow 1 to the result) gives 010 (2).[9][10] Two's complement, the more widely adopted method, negates the subtrahend by first taking its one's complement and then adding 1, given by the formula \tilde{B} + 1, where \tilde{B} denotes the bitwise NOT of B. Subtraction proceeds by adding this two's complement value to A, with any overflow carry simply discarded, eliminating the need for end-around carry and simplifying overflow detection. In the same 3-bit example, the two's complement of 011 is 100 (one's complement) + 1 = 101 (-3), and 101 + 101 yields 1010, discarding the overflow carry to obtain 010 (2) directly. This approach is preferred in modern digital circuits for its efficiency and uniform treatment of addition and subtraction.[11][12] The primary advantages of complement methods lie in hardware simplification: they enable a single adder circuit to handle both addition and subtraction by conditionally generating the complement of the subtrahend, reducing overall gate count, power consumption, and design complexity compared to dedicated subtractor logic. This unification supports versatile arithmetic logic units (ALUs) capable of fast operations without separate pathways for subtraction. Early binary computer designs, such as those from the mid-20th century, explicitly leveraged two's complement for this purpose to achieve high-speed arithmetic with minimal additional hardware.[12][13]Circuit Design
Basic Building Blocks
The half adder is a fundamental combinational logic circuit designed to perform binary addition of two single-bit inputs, denoted as A and B, producing a sum output S and a carry output C. The sum is generated using an exclusive-OR (XOR) gate, where S = A \oplus B, while the carry is produced by an AND gate, C = A \cdot B. This circuit requires only two logic gates: one XOR for the sum and one AND for the carry.[14] The truth table for the half adder is as follows:| A | B | S (A \oplus B) | C (A \cdot B) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| A | B | D (A \oplus B) | B_out (\overline{A} \cdot B) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
Full Adder-Subtractor Implementation
A full adder is a combinational circuit that adds three binary bits: two input bits A and B, along with a carry-in bit Cin, producing a sum bit S and a carry-out bit Cout.[16] The sum output is given by the equation S = A \oplus B \oplus C_{in}, while the carry-out is C_{out} = (A \land B) \lor (A \land C_{in}) \lor (B \land C_{in}).[16] The truth table for a full adder is as follows:| A | B | Cin | S | Cout |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |