OR gate
An OR gate is a fundamental digital logic gate that performs the logical disjunction operation on one or more binary inputs, producing a high output (logic 1) if at least one input is high (logic 1), and a low output (logic 0) only if all inputs are low (logic 0).[1][2] The concept underlying the OR gate originates from Boolean algebra, developed by mathematician George Boole in the mid-19th century, which provides the mathematical foundation for binary logic operations.[3] In 1937, Claude Shannon's master's thesis at MIT first demonstrated how Boolean algebra could be applied to practical switching circuits using relays, effectively inventing the AND, OR, and NOT gates as building blocks for digital computation.[4] This work laid the groundwork for modern digital electronics, transitioning from mechanical relays to transistor-based implementations in the mid-20th century.[5] OR gates are typically represented by a standard ANSI or IEC symbol: a curved input side with multiple input lines converging to a pointed output, and their behavior is fully defined by a truth table that enumerates all possible input combinations.[2] For a two-input OR gate, the truth table is as follows: In practice, OR gates are constructed using diodes for simple diode-OR logic or transistors in CMOS and TTL technologies for integrated circuits, enabling efficient signal processing in processors, memory units, and control systems.[6] They form essential components in combinational and sequential logic designs, underpinning the operation of computers, telecommunications equipment, and embedded systems by facilitating operations like addition, selection, and decision-making in binary form.[7]Fundamentals
Definition and Operation
An OR gate is a fundamental digital logic gate in electronics that implements the logical disjunction operation, producing a high output signal (representing logic 1 or true) when at least one of its input signals is high, and a low output signal (logic 0 or false) otherwise.[8] This behavior makes it a basic building block for constructing more complex digital circuits, such as those in computers and control systems.[9] In operation, the OR gate assumes binary inputs and outputs, where signals are strictly either high voltage (logic 1) or low voltage (logic 0), serving as a prerequisite for all digital electronic systems that rely on such two-state representations.[10] For a typical two-input OR gate, the output remains low only if both inputs are low; it transitions to high if either the first input, the second input, or both are high, enabling the gate to detect the presence of any active input condition.[8] The conceptual foundation of the OR gate traces to Boolean algebra, developed by George Boole in the mid-19th century, with early 20th-century efforts by electrical engineers to model switching behaviors using it, such as Claude Shannon's 1937 master's thesis providing the formal linkage between Boolean algebra and electrical relay circuits.[11] In this seminal work, published in 1938, Shannon demonstrated how operations like logical OR could be realized through circuit switching, laying the groundwork for modern digital logic design.[12]Truth Table and Boolean Algebra
The logical operation of an OR gate is formally defined by its truth table, which enumerates all possible input combinations and corresponding outputs for a two-input case. The inputs A and B each can be 0 (false) or 1 (true), and the output Y is 1 if at least one input is 1, otherwise 0.[13]| A | B | Y (A ∨ B) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Representations
Graphical Symbols
The ANSI/IEEE standard symbol for the OR gate employs a distinctive shape characterized by multiple straight input lines converging into a curved, concave side on the left, terminating in a pointed triangular output on the right. This configuration allows for variants accommodating two or more inputs by simply extending additional input lines to the curved side, facilitating clear representation in circuit schematics. The curved input distinguishes the OR gate from the AND gate symbol, which features straight input lines meeting at a pointed convergence rather than a curve.[18][19][20] In contrast, the IEC 60617 standard utilizes a rectangular outline for the OR gate, with a flat vertical input side on the left and the output on the right, often containing the notation "≥1" to denote the logical OR operation.[21][22] This symbol aligns with broader IEC efforts to standardize graphical representations across global engineering practices, often appearing in European and ISO-compliant documentation. The graphical symbols for the OR gate trace their evolution from rudimentary depictions in 1940s relay logic diagrams, where OR functions were illustrated via parallel branches of normally open contacts in ladder-style schematics, to the formalized distinctive shapes introduced in the 1960s through U.S. military standards like MIL-STD-806. These evolved into the comprehensive IEEE Std 91-1984, which codified both distinctive and rectangular variants for use in modern semiconductor and integrated circuit designs, reflecting the shift from electromechanical to solid-state technologies.[23][24][20] Bubble notations enhance these symbols by indicating active-low logic levels; a small circle at each input terminal signifies that the input is asserted when low, while for the NOR variant, a bubble at the output inverts the standard OR function to produce a low output only when all inputs are high.[25][18]Analytical Expressions
The logical OR operation is fundamentally represented in sum-of-products (SOP) form, where for two inputs, the output Y is given by Y = A + B, with the plus symbol denoting the logical OR operation.[26] This expression arises directly from the disjunctive nature of the OR gate, summing the individual input literals without product terms since each input alone suffices for a true output. For three inputs, the SOP form extends straightforwardly to Y = A + B + C, maintaining the additive structure for multi-input OR functions.[26] An alternative algebraic representation decomposes the two-input OR using exclusive-OR (XOR) and AND operations: A \lor B = (A \oplus B) \oplus (A \land B).[27] This identity holds because A \oplus B captures the cases where exactly one input is true, while A \land B accounts for the case where both are true, and XORing them together yields the full OR without overlap, as the terms are mutually exclusive. To derive this step-by-step, begin with the known disjoint decomposition: A \lor B = (A \land B) \lor (A \oplus B). Since (A \land B) \land (A \oplus B) = 0 (the terms do not overlap), the logical OR of disjoint Boolean terms equals their XOR: (A \land B) \oplus (A \oplus B). Expanding (A \oplus B) = A \land \lnot B + \lnot A \land B confirms the truth table match, but the disjoint property directly justifies the equivalence.[27] This decomposition is useful in contexts like arithmetic circuits or when XOR primitives are available, enabling OR synthesis from other gates. Karnaugh maps (K-maps) provide a visual method for simplifying Boolean functions that incorporate OR operations, revealing minimal SOP expressions where OR gates fit as summed terms. For the two-input OR function, a K-map with 1s in the cells for inputs (A=0, B=1) and (A=1, B=0 or 1) allows grouping of the two adjacent 1s covering B=1 and the single 1 for A=1 when B=0, but the optimal grouping yields the simplified SOP Y = A + B by encircling all 1s in largest power-of-two rectangles that eliminate variables.[28] In more complex OR-inclusive functions, such as Y = A \lor (B \land C), the K-map groups minterms to minimize literals, often resulting in expressions where OR acts as the top-level summation, demonstrating how OR gates integrate into reduced two-level logic.[28] This technique prioritizes adjacent groupings to exploit Boolean absorption and consensus laws, ensuring OR terms dominate in disjunctive normal form. In quantum and reversible computing extensions, the classical OR gate serves as a basis for analogs constructed using Toffoli gates, which enable reversible disjunction while preserving all input information through ancillary qubits.[29] For instance, a reversible OR can be synthesized from Toffoli gates by computing intermediate AND and copying operations, allowing the OR to be embedded in unitary transformations without information loss, as Toffoli's universality supports all classical reversible functions including OR.[29]Hardware Implementations
Integrated Circuit Examples
One prominent example in the TTL family is the SN7432, a quad two-input positive-OR gate integrated circuit that contains four independent OR gates in a single 14-pin package.[30] The pinout configuration follows the standard TTL layout: pins 1 and 2 serve as inputs for the first OR gate with output on pin 3; pins 4 and 5 for the second gate with output on pin 6; pins 9 and 10 for the third gate with output on pin 8; and pins 12 and 13 for the fourth gate with output on pin 11; power supply connections are Vcc on pin 14 and ground on pin 7. Key electrical characteristics include a minimum high-level output voltage of 2.4 V when sourcing 400 µA. In the CMOS domain, the CD4071B provides a quad two-input OR gate equivalent, offering advantages such as lower static power consumption with a maximum of approximately 1 µW per gate and a broader supply voltage range of 3 V to 18 V.[31] This makes it suitable for battery-powered or low-power applications where TTL's higher quiescent current would be inefficient.[31] The CD4071B shares the same 14-pin pinout as the SN7432 for compatibility in gate configurations.[31] Propagation delay for TTL OR gates like the SN7432 is typically 10 ns at a 5 V supply, though this can vary with factors such as fan-out (the number of gates driven by the output) and loading capacitance.[32] CMOS versions like the CD4071B exhibit higher delays, often in the 60-100 ns range depending on voltage and load, prioritizing power efficiency over speed.[31] These ICs are commonly housed in a 14-pin dual in-line package (DIP-14) for through-hole mounting in prototyping and legacy designs.[30] Modern variants include surface-mount options such as small-outline integrated circuit (SOIC-14) packages for compact, automated assembly in contemporary electronics.[30]Discrete and Alternative Circuits
One common discrete implementation of an OR gate uses diodes and resistors, known as diode-resistor logic (DRL). In a basic two-input diode OR gate, the anodes of two diodes are connected to the respective inputs, while the cathodes are joined together and connected through a load resistor to ground. The output is taken from the common cathode point. When both inputs are low (logic 0), both diodes are reverse-biased, and the output remains low. If either or both inputs go high (logic 1), the corresponding diode(s) forward-bias and conduct, allowing current to flow through the load resistor, raising the output voltage to approximately the input high level minus the diode forward voltage drop of about 0.7 V for silicon diodes. This configuration sums the input currents at the output, providing the OR function, though the voltage drop limits its use in multi-stage logic without amplification.[33][34] A transistor-based OR gate can be built using discrete NPN bipolar junction transistors (BJTs) in a resistor-transistor logic (RTL) style, often requiring an inversion stage for the desired polarity. For a two-input design, two NPN transistors are placed in parallel: their bases connect to the inputs through current-limiting resistors, emitters are grounded, and collectors are tied together and connected to the positive supply (Vcc) via a pull-up resistor, forming the core NOR stage. This parallel arrangement ensures that if any input is high, the corresponding transistor receives base current, enters saturation (with collector-emitter voltage near 0 V), and pulls the intermediate output low. To achieve the OR function—where the final output is high when any input is high—an additional NPN inverter transistor is added: its base connects to the NOR output via another resistor, its emitter to ground, and its collector to Vcc through a pull-up resistor, with the final output at the collector. When the NOR output goes low (due to any input high), the inverter transistor turns off, allowing the pull-up resistor to drive the final output high. This saturation in the parallel transistors ensures reliable switching for the high output state.[35] Historically, OR gates were implemented using relay logic in early electromechanical computers, where parallel relay contacts performed the OR operation. In this setup, each input energizes a relay coil, closing its normally open contacts in parallel across the output path; if any input activates, the corresponding contact closes, completing the circuit and producing a high output (energizing the output relay or load). Series contacts would instead implement AND logic. This approach was used in the Harvard Mark I (also known as the IBM Automatic Sequence Controlled Calculator), completed in 1944, which relied on over 3,000 relays for logic operations in its arithmetic and control units. Relay logic provided robust isolation and handling of higher voltages but was slow (milliseconds per operation) and power-hungry compared to later semiconductor designs.[36][37] As an example of RTL applied to a two-input OR gate, consider the circuit described above with specific component values for a 5 V supply: use 10 kΩ base resistors for the parallel NPN transistors (e.g., 2N3904), a 4.7 kΩ pull-up for the NOR collector, a 10 kΩ base resistor for the inverter NPN, and a 4.7 kΩ pull-up for the final output. The schematic consists of inputs A and B feeding the bases of T1 and T2 (parallel NPNs) via resistors; T1 and T2 collectors join at node X with pull-up to Vcc; node X feeds the base of T3 (inverter NPN) via resistor, T3 emitter to ground, and T3 collector (output Y) with pull-up to Vcc. This realizes Y = A OR B, verified by the truth table:| Input A | Input B | Output Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |