Program status word
The program status word (PSW) is a control register in IBM mainframe CPU designs, starting from System/360, that combines the function of a status register and program counter. It contains status information reflecting the current execution state of a program, including condition codes indicating outcomes such as lesser than zero, zero or equal, or greater than zero from arithmetic or logical operations. The PSW serves to encapsulate key processor conditions that influence control flow, exception handling, and privilege modes, enabling the operating system to manage interrupts, context switches, and diagnostic information efficiently.[1] Common components include condition code bits that indicate the outcome of the most recent instruction, interruption masks to control asynchronous events, and addressing mode indicators for virtual memory or architecture-specific behaviors.[1] The PSW incorporates the address of the next instruction to be executed, facilitating precise resumption after interruptions.[2] Notable examples appear in IBM architectures: in z/Architecture systems, the PSW is a 16-byte structure that denotes the system's general status (e.g., wait state or processing mode), interrupt capabilities, and the instruction address, with variants like restart, external, or program PSWs providing diagnostics for events such as machine checks.[2] These implementations highlight the PSW's role in maintaining processor state in mainframe computing environments.Overview
Definition and Purpose
The Program Status Word (PSW) is a hardware register in IBM mainframe architectures that combines the functions of a program counter and a status register, defining the state of the central processing unit (CPU) for the currently active program.[3][4] It holds the address of the next instruction to be executed, ensuring continuity in program flow, while also tracking essential execution details such as operational outcomes and system conditions.[3] This dual role allows the PSW to serve as a central control mechanism, preserving the CPU's operational context during task execution.[4] The primary purposes of the PSW include maintaining seamless program execution by directing instruction sequencing, signaling conditions that may trigger branching or interrupts, and enforcing storage protection to safeguard data integrity.[3] For instance, it facilitates interrupt handling by storing the current CPU state and loading a new PSW to transfer control to an appropriate handler, thereby supporting efficient multitasking and error recovery.[4] Additionally, through embedded protection mechanisms, the PSW prevents unauthorized access to memory by comparing access keys against storage protections, a critical feature for secure multi-programmed environments.[3] In general composition, the PSW typically encompasses an instruction address field for the next executable command, a condition code of 2-4 bits that indicates results such as zero, overflow, or negative outcomes from prior operations, a program mask to enable or disable specific program exceptions such as fixed-point overflow or decimal overflow, and a system mask to control interrupts such as I/O or external events, along with a protection key to regulate memory access permissions.[3][4] Over time, the PSW has evolved from a 64-bit structure in early systems to a 128-bit format in modern implementations, accommodating expanded addressing and enhanced control capabilities without altering its core conceptual framework.[3][4]Role in Program Execution
The Program Status Word (PSW) plays a central role in sequencing instructions during program execution by specifying the address of the next instruction to be fetched from main storage. After an instruction is fetched, the instruction address field within the PSW is automatically incremented by the length of that instruction, as indicated by the instruction length code (ILC) field, to point to the subsequent instruction in a linear execution flow.[5] Branching instructions can modify this address based on specified conditions, enabling non-sequential execution such as jumps or calls to subroutines.[5] In exceptional situations like interrupts or mode switches, the PSW ensures continuity by preserving the current execution state. When an interruption occurs, the existing PSW—capturing the precise instruction address, condition code, and control bits—is stored as the "old PSW" in a designated location in main storage, allowing the program to resume exactly from the interruption point upon completion of the handling routine.[5] A "new PSW" is then loaded from another predefined storage location to initiate the interrupt service, updating the CPU state for the required processing.[5] This mechanism supports seamless transitions between normal program flow and exception handling without loss of context.[5] The PSW also governs access to and interaction with other CPU components, such as general registers and floating-point status, through its state and mask fields. For instance, the problem state bit in the PSW determines whether the CPU operates in supervisor or problem mode, restricting privileged access to certain registers and operations in user mode to maintain system integrity.[5] Similarly, the program mask field controls exception handling for arithmetic operations involving general registers or floating-point units, influencing how results propagate to the overall execution state.[5] A practical example of the PSW's dynamic role occurs in conditional looping constructs, where arithmetic instructions update the condition code field based on results from general register operations, such as comparisons or additions. The Branch on Condition (BC) instruction then examines this condition code to decide whether to alter the instruction address, for instance, repeating a loop if a counter in a general register remains nonzero after decrementing.[5] This integration allows efficient data-dependent control flow without manual address management.[5]Historical Development
Origins in System/360
The Program Status Word (PSW) was introduced with the IBM System/360 family of computers, announced on April 7, 1964, as a key element in unifying IBM's disparate pre-existing computer lines—such as the scientific 701 series and business-oriented 1401—into a single, compatible architecture spanning low- to high-end models.[6] This design effort, guided by the 1961 SPREAD Task Group recommendations, aimed to create a "New Product Line" that eliminated the fragmentation of hardware, software, and peripherals, enabling seamless data and application portability across the range.[6] The PSW served as the central repository for CPU state information, facilitating this unified approach by standardizing program control and interruption handling in a 64-bit doubleword format.[5] The primary motivations for the PSW's design centered on the need for a compact mechanism to manage program execution status and the instruction counter, essential for supporting multitasking environments and ensuring binary compatibility across System/360 models from the entry-level Model 30 to the high-performance Model 91.[6] In an era of growing system complexity, the PSW addressed the challenges of asynchronous events like I/O interruptions and program exceptions by storing all necessary control information—such as the next instruction address and interruption masks—in one accessible unit, allowing efficient state preservation and restoration during context switches.[5] This compactness was crucial for real-time operations and task queuing, as seen in applications like NASA's Apollo program, while promoting upward and downward compatibility without requiring program rewrites.[6] Key innovations in the PSW included embedding a 24-bit instruction address within the 64-bit structure to support up to 16 megabytes of main storage addressing, balancing immediate hardware capabilities with future scalability across the model lineup.[5] Additionally, the incorporation of a 4-bit protection key provided early memory access control, comparing the PSW key against 2,048-byte storage blocks to prevent unauthorized stores and trigger protection exceptions, enhancing system security in multi-programmed setups.[5] These features centralized status switching and exception handling, marking a departure from prior IBM designs and laying the groundwork for robust, interrupt-driven processing.[5] An early deviation occurred with the System/360 Model 20, a cost-reduced variant introduced to bridge smaller installations, which employed a non-standard 4-byte (32-bit) PSW format due to hardware limitations in its 16-bit register set and simplified architecture.[7] This shorter PSW, consisting of two halfwords for instruction address, condition codes, and limited status bits like channel masks, maintained basic compatibility but omitted full 64-bit features such as extended interruption codes, reflecting the Model 20's role as a transitional subset rather than a full implementation.[7]Evolution Through System/370 and Successors
The IBM System/370, introduced in 1970, marked a significant evolution in the Program Status Word (PSW) by incorporating an Extended Control (EC) mode alongside the Basic Control (BC) mode for compatibility with the System/360. In EC mode, the PSW expanded to support 31-bit logical addressing, enabling dynamic address translation for virtual storage and addressing up to 16 MB of real memory, a step beyond the 24-bit limit of prior architectures. This addition included new fields such as the translation-control bit (bit 5) to enable or disable address translation and the Program-Event-Recording (PER) mask (bit 1) for debugging, while relocating interruption-related fields like channel masks to main storage or control registers to streamline the 64-bit PSW structure.[8] In the 1980s, the System/370 Extended Architecture (S/370-XA), announced in 1981, further refined the PSW to address growing memory demands, mandating EC mode and introducing full 31-bit addressing via the addressing-mode bit (bit 32), which allowed programs to operate in either 24-bit or 31-bit modes for bimodal compatibility. A key enhancement was the address-space-control bit (bit 16), enabling primary- and secondary-space modes to support multiple virtual address spaces of up to 2 GB each, facilitated by control registers for segment-table designations and instructions like SET ADDRESS SPACE CONTROL. These changes supported larger memory configurations and virtual machine environments, with the PSW retaining its 64-bit format but gaining fields for enhanced interruption validity and space-switching.[9] The 1990s brought the Enterprise Systems Architecture/390 (ESA/390) in 1990, which enhanced the PSW for enterprise-scale operations, including logical partitioning (LPAR) through expanded address-space-control bits (16-17) that defined four modes: primary, secondary, access-register, and home-space. This allowed up to 65,536 address spaces per partition, with bit fields integrating access-list entries (ALETs) and space-switching instructions like PROGRAM CALL to manage partitioned environments on a single system. The PSW remained 64 bits but incorporated additional validity indicators and control-register interactions (e.g., CR13 for home-space designation), improving virtualization and resource isolation without altering core compatibility.[10] By the 2000s, z/Architecture, introduced in 2000 with the zSeries 900, shifted the PSW to a 128-bit format to natively support 64-bit addressing, using bits 31 (extended-addressing mode) and 32 (basic-addressing mode) to enable 24-, 31-, or 64-bit operations, addressing up to 16 exabytes of virtual memory. This evolution included an expanded instruction-address field (bits 64-127) and enhanced dynamic address translation with region tables, while maintaining compatibility modes for ESA/390 via a short 64-bit PSW option in instructions like LOAD PSW. As of 2025, IBM Z mainframes fully leverage this 128-bit PSW in z/Architecture for high-performance computing, with ongoing support for legacy modes ensuring seamless migration.[11] Overall, the PSW's development from System/370 onward reflects a progression from compatibility-driven expansions—focusing on virtual storage and addressing limits—to comprehensive 64-bit native capabilities, enabling modern IBM Z systems to handle massive-scale workloads while preserving backward compatibility across decades of mainframe evolution.Access and Manipulation
Instructions for PSW Handling
The Load Program Status Word (LPSW) instruction in IBM System/360 architecture loads a new 8-byte PSW from a doubleword location in main storage, specified by the operand address in the instruction formatLPSW D2(B2) with operation code 82 hexadecimal.[5] This privileged instruction, executable only in supervisor state, replaces the current PSW, immediately altering the CPU's execution state, including the instruction address (PSW bits 40-63), condition code (bits 34-35), protection key (bits 8-11), and interruption masks.[5] If executed in problem state, it triggers a privileged-operation exception; additionally, invalid operand addresses (e.g., not on a doubleword boundary) or nonzero protection keys without the protection feature cause specification exceptions.[5]
In z/Architecture, the Load PSW Extended (LPSWE) instruction extends this capability for the 16-byte PSW format, using the syntax LPSWE D2(B2) with operation code B2B2 hexadecimal, and supports loading in 64-bit addressing mode while handling transitions between long (64-bit) and short (31-bit or 24-bit) PSW formats.[12] Like LPSW, LPSWE is privileged and causes serialization and checkpoint synchronization upon execution, updating fields such as the addressing mode (PSW bits 31-32), DAT mode (bit 5), and instruction address (bits 64-127 in long format).[12] Loading an invalid PSW via LPSWE—such as one with unassigned bits set or bit 12 zero in certain models—results in a specification exception after loading, with the instruction length code (ILC) set to zero and potential entry into a program interruption loop unless interrupted by reset.[12]
For storing or examining PSW contents without full replacement, the Extract PSW (EPSW) instruction provides a non-privileged mechanism to copy the current PSW into a general register or storage, using formats such as EPSW R1 (operation code B98D hexadecimal in RRE format) for diagnostic purposes in user programs.[12] This read-only operation places PSW bits 0-11 and 13-31 into specified register bits (e.g., 32-43 and 45-63 of GR R1), with bit 44 indicating the PSW format (0 for z/Architecture long PSW), and does not alter the execution state.[12] Complementing this, the Set PSW Key from Address (SPKA) instruction, privileged and formatted as SPKA R1,D2(X2,B2) (operation code E1C0 hexadecimal), stores the current PSW key (bits 8-11) into bits 56-59 of a target register while setting the PSW key from the low-order bits of an address operand, facilitating selective updates to storage protection without full PSW replacement.[12]
Earlier IBM systems, such as System/360 and System/370, relied solely on the 8-byte LPSW for PSW loading, treating it as a 64-bit entity with implicit short-format handling.[5] Modern z/Architecture implementations maintain backward compatibility by automatically converting 8-byte PSWs loaded via LPSW to 16-byte format (e.g., inverting bit 12), but LPSWE enables direct manipulation of extended fields, including selective updates to masks and addresses in 64-bit mode without requiring full privileged reloads in some contexts.[12]
Privileged and Compatibility Modes
The Program Status Word (PSW) enforces privilege levels in IBM mainframe architectures by distinguishing between supervisor state, which allows kernel-level operations with full access to privileged instructions and system resources, and problem state, which confines user programs to non-privileged instructions to prevent unauthorized system interference.[5][8][11] In supervisor state, the processor can execute all instructions, including those for I/O control and storage manipulation, whereas problem state restricts access to sensitive operations, such as modifying control registers or issuing interrupts, to maintain system security.[5][8] This mode is determined by a designated bit in the PSW, for example, bit 15 set to 0 for supervisor state and 1 for problem state in System/360.[5] Problem state further limits access to certain PSW fields, such as protection keys, to avoid tampering with system controls.[5][8] In System/360, initial privilege enforcement combined the supervisor bit with key-based protection, where the PSW's 4-bit protection key (bits 8-11) is matched against storage keys for 2,048-byte memory blocks to block invalid accesses, triggering a protection exception on mismatch.[5] Subsequent architectures retained this foundation but added layers like PSW-key masks in control registers to authorize specific keys only in problem state.[8] These mechanisms collectively restrict problem-state programs from altering critical PSW elements, such as interruption masks or addressing controls.[5][11] Compatibility modes in the PSW bridge architectural generations by emulating legacy formats and addressing schemes. The short PSW, an 8-byte format in z/Architecture, supports 24-bit and 31-bit legacy addressing on 64-bit processors, enabling older applications to run without modification during initial program load or mode transitions.[11] In System/370, Extended Control (EC) mode activates virtual addressing by setting PSW bit 12 to 1, allowing dynamic address translation via segment and page tables for up to 16 megabytes of logical address space, while Basic Control mode (bit 12 = 0) preserves System/360 compatibility without translation.[8] Mode switching between privileged and compatibility states is managed through the Load PSW (LPSW) instruction, a privileged operation that replaces the current PSW with values from a specified operand address, but only validly from supervisor state to avoid security risks.[5][8] The processor validates transitions, such as prohibiting a direct switch to supervisor state from problem state without an intervening interruption like a supervisor call, which would otherwise cause a specification exception if PSW bits are invalid.[5][11] Interruptions automatically store the old PSW and load a new one from fixed locations, facilitating controlled mode changes.[8] Attempts to violate privilege rules, such as executing a restricted instruction in problem state, invoke protection or operation exceptions that halt execution and transfer control to a handler via PSW update.[5][8] In contemporary z/OS environments, PSW modes underpin hypervisor virtualization by isolating guest OS privileges through address-space controls and mode enforcement.[11] The evolution of PSW modes reflects a progression from System/360's rudimentary key-based protection and supervisor bit to more sophisticated features in later systems.[5] System/370 introduced EC mode for virtual addressing alongside AMODE and SMODE indicators to support 24-bit and 31-bit compatibility.[8] z/Architecture further extended this with 64-bit addressing via PSW bits 31-32, ensuring legacy code portability while enhancing virtualization capabilities.[11]Formats by Architecture
System/360 Format
The Program Status Word (PSW) in the IBM System/360 architecture is a 64-bit doubleword that encapsulates essential control information for program execution, including interruption masks, status indicators, and the address of the next instruction to be fetched.[4] It is always treated as residing at a location with an even address and is loaded as a complete unit, with the operand address for the Load PSW (LPSW) instruction required to be on a doubleword boundary (low-order bits 0-2 zero); otherwise, a specification exception occurs.[4] The PSW's bit layout is as follows, with bits numbered 0 (most significant) to 63 (least significant):| Bits | Field | Description |
|---|---|---|
| 0-7 | System Mask | Eight bits controlling interruption classes: bits 0-6 mask I/O channels 0-6, bit 7 masks external interruptions (e.g., timer or external signals); a 1 enables interruptions in that class, while 0 disables them but allows pending conditions to accumulate.[4] |
| 8-11 | Protection Key | Four-bit field (values 0-15) that specifies the storage protection key for the current program; it is compared against the key of each 2,048-byte (2K) block of storage accessed—if they match or the PSW key is 0, access is permitted; if the protection feature is not installed, this field must be zeros, or a specification exception results.[4] |
| 12 | Compatibility Flag (A-bit) | Selects the sign code for decimal results: 0 for EBCDIC (zone 1111), 1 for USASCII-8 (zone 0101); this bit is unused in non-decimal operations.[4] |
| 13 | Machine-Check Mask (M-bit) | Controls machine-check interruptions: 1 enables them, 0 disables but allows pending checks.[4] |
| 14 | Wait State (W-bit) | Indicates processor state: 1 places the CPU in a wait state (no instruction execution, responsive to interruptions), 0 indicates running state.[4] |
| 15 | Problem State (P-bit) | Defines execution mode: 1 for problem state (user mode, restricting privileged instructions), 0 for supervisor state (full access).[4] |
| 16-31 | Reserved | Zeros in the current PSW; during interruption processing, these bits store the 16-bit interruption code identifying the cause (e.g., 0x0004 for supervisor call).[4] |
| 32-33 | Instruction Length Code (ILC) | Two bits indicating the length of the interrupted or last-executed instruction in halfwords: 00 (2 bytes), 01 (4 bytes), 10 (6 bytes); value 11 is reserved.[4] |
| 34-35 | Condition Code (CC) | Two bits summarizing the result of the previous instruction: 0 indicates equal/zero, 1 low/less than zero, 2 high/greater than zero, 3 overflow or special condition (e.g., unnormalized result or test under mask failure).[4] |
| 36-39 | Program Mask | Four bits masking program exceptions: bit 36 for fixed-point overflow, bit 37 for decimal overflow, bit 38 for exponent underflow, bit 39 for significance (loss in floating-point); 1 enables interruption on occurrence, 0 suppresses it but sets the condition code.[4] |
| 40-63 | Instruction Address | Right-justified 24-bit address of the next instruction byte to execute; bit 63 is always 0, providing addressing up to 16 megabytes of storage.[4] |
System/370 Format
The Program Status Word (PSW) in the IBM System/370 architecture maintains backward compatibility with the System/360 through its Basic Control (BC) mode while introducing enhancements in Extended Control (EC) mode to support expanded addressing and additional control features. In BC mode, the 64-bit PSW format is identical to that of the System/360, ensuring seamless execution of legacy programs in non-virtual environments without modifications. This mode limits addressing to 24 bits, positioning the instruction address in bits 40-63, with bits 0-39 dedicated to interruption masks, condition code, program mask, and reserved fields set to zero for compatibility.[14] In contrast, EC mode employs a full 64-bit PSW that incorporates System/370-specific extensions, including a protection key, timing facility bit, and support for 31-bit addressing, enabling up to 2 gigabytes of addressable storage. This mode is the default for System/370 operations and is used when saving the PSW during interruptions, where the old PSW is stored at real locations 0-63 and the new PSW loaded from 64-127. The EC PSW structure allocates bits 0-4 for the I/O interruption mask, which selectively enables interruptions from up to five I/O channels; bit 5 for DAT mode (1 enables dynamic address translation); bit 6 for the external interruption mask (enabling signals from external devices); and bit 7 for the problem state bit (1 denotes restricted user-mode privileges, 0 indicates supervisor mode). Bits 8-11 hold the PSW key, a 4-bit value that governs access to main storage blocks during real addressing. Bit 12 is the machine-check mask; bit 13 is the wait state (1 indicates the CPU is paused and not fetching instructions). Bits 14-17 are reserved and must be zero. Bits 18-19 form the condition code, a 2-bit value reflecting the outcome of the last instruction (e.g., 0 for equal/comparable, 1 for low/greater, 2 for high/less, 3 for overflow or special conditions). Bits 20-23 form the program mask, controlling whether certain program exceptions (such as fixed-point overflow in bit 20 or decimal overflow in bit 21) cause interruptions. Bit 24 as the T-bit for the timing facility, which when set to 1 enables CPU timer interrupts for performance monitoring; and bits 25-31 as reserved (must be zero). Bit 32 serves as the addressing-mode bit (AM bit), with 0 specifying 24-bit addressing (for compatibility, placing the 24-bit instruction address in bits 40-63 and requiring bits 33-39 to be zero) and 1 enabling 31-bit addressing (using bits 33-63 directly for the full 31-bit instruction address). In DAT-off mode (dynamic address translation disabled), the AM bit acts as the extension bit to toggle between these addressing modes without invoking virtual storage mechanisms. Bits 33-63 then contain the instruction address for the next sequential execution, either 24 bits (right-justified when AM=0) or 31 bits (fully utilized when AM=1). This design supports the transition to larger memory configurations while preserving the ability to run System/360 code in BC mode.[14]| Bit Positions | Field | Description |
|---|---|---|
| 0-4 | I/O Mask | Enables I/O interruptions for channels 0-4 (1=enabled). |
| 5 | DAT Mode | 1=DAT on (virtual addressing enabled); 0=real addressing. |
| 6 | External Mask | 1=enables external interruptions; 0=masked. |
| 7 | Problem State | 1=problem (user) state; 0=supervisor state. |
| 8-11 | PSW Key | 4-bit storage protection key for real-mode access checks. |
| 12 | Machine-Check Mask | 1=enables machine-check interruptions. |
| 13 | Wait State | 1=CPU in wait state (no instruction fetch); 0=executing. |
| 14-17 | Reserved | Must be 0. |
| 18-19 | Condition Code (CC) | 2-bit status: 0=equal/normal, 1=low/greater, 2=high/less, 3=overflow/special. |
| 20-23 | Program Mask | Controls exceptions (e.g., bit 20=fixed-point overflow, bit 21=decimal overflow). |
| 24 | T-Bit (Timing) | 1=enables CPU timer for timing facility interruptions. |
| 25-31 | Reserved | Must be 0. |
| 32 | Addressing Mode (AM) | 0=24-bit addressing; 1=31-bit addressing (extension bit in DAT-off). |
| 33-63 | Instruction Address | Next instruction location: 24-bit (bits 40-63, bits 33-39=0 when AM=0) or 31-bit (full range when AM=1). |
S/370 Extended Architecture Format
The Program Status Word (PSW) in System/370 Extended Architecture (S/370-XA) operates exclusively in extended control (EC) mode, extending the 64-bit format from the prior System/370 architecture to support 31-bit addressing and advanced virtual storage management. Bits 0-15 retain the same structure as the System/370 EC mode PSW, encompassing the condition code (bits 0-1), program mask (bits 2-5), I/O mask (bit 6), external mask (bit 7), PSW key (bits 8-11), machine-check mask (bit 12), wait state (bit 13), problem state (bit 14), and address-space control (ASC) bit (bit 15, where 0 indicates primary space and 1 indicates secondary space). This continuity ensures basic compatibility for legacy code execution within the enhanced framework.[15] Key enhancements appear in the upper bits, introducing fields for address-space management and extended addressing. Bit 16 specifies the addressing mode (AMODE), determining whether 24-bit or 31-bit addressing is active. Bit 17 indicates supervisor key validity, affecting storage protection enforcement. Bits 18-23 hold the primary ASN key, while bits 24-31 contain the secondary ASN, collectively forming the address-space control elements that identify and validate the current virtual address space. These ASN fields enable the association of processes with specific address spaces, supporting up to 65,536 distinct 2 GB address spaces through dynamic address translation (DAT). Bit 32 through bit 63 comprise the 31-bit instruction address, with bit 32 serving as the addressing mode bit (always set to 1 for 31-bit mode in full XA operation) and bits 33-63 providing the effective 31-bit pointer to the next instruction, aligned such that bit 0 of the address is implicitly zero.[15] The new address-space control fields (bits 16-31) represent a fundamental shift toward virtualization, allowing multiple independent address spaces without relying solely on control registers for ASN assignment. DAT mode, which enables virtual-to-real address translation, is controlled by PSW bit 5 (set to 1 for on) in conjunction with control register 0 bit 5; when active, it leverages two-level page and segment tables to map the 31-bit virtual addresses. This setup permits real and virtual storage up to 2 GB (2^{31} bytes), a significant expansion from the 16 MB limit of 24-bit addressing in System/370. Programs operating in 31-bit mode can access the full range, but transitions between modes require explicit instructions to avoid addressing exceptions.[15] Adopting S/370-XA necessitates updated linkage conventions, such as the PROGRAM CALL and PROGRAM RETURN instructions, to properly stack and restore the extended PSW fields during subroutine calls or context switches. Legacy System/370 PSW formats, lacking the new bits 16-31 and the extended instruction address, trigger access exceptions or specification exceptions when loaded in XA mode, enforcing a clean migration path for operating systems and applications. This design prioritizes backward compatibility for 24-bit programs running under DAT-on while mandating 31-bit awareness for new virtual storage features.[15]Enterprise Systems Architecture Format
The Program Status Word (PSW) in the Enterprise Systems Architecture (ESA) format, particularly for ESA/390 in extended control (EC) mode, is a 64-bit structure that extends the System/370 Extended Architecture (XA) design with refinements tailored to enterprise-scale computing environments. Introduced with the S/390 processors in 1990, this format supports 31-bit addressing while maintaining backward compatibility with prior architectures, enabling seamless operation in logically partitioned systems. The PSW governs critical aspects of program execution, including interrupt handling, address space selection, and floating-point operations, with specific bits dedicated to masking exceptions and specifying operational modes.[16] Building on XA, the ESA PSW incorporates bit 22 as the hexadecimal floating-point (HFP) exponent underflow mask, which was renamed and refined from earlier implementations to control underflow handling—setting the result to zero when the bit is zero or normalizing the fraction when it is one. Bits 24-31 handle space-switch events, which facilitate controlled transitions between primary, secondary, access-register, and home address spaces during operations such as program calls or transfers. Bits 32-63 store the 31-bit instruction address, allowing programs to operate within a 2 GB virtual address space per region. These elements ensure robust support for multi-tasking and virtualization in enterprise settings.[16] ESA enhancements emphasize integration with advanced services, including the EXCP macro for low-level I/O control, where PSW bits enable direct channel command word (CCW) chaining without operating system intervention. The PSW also includes provisions for access register specification through its address space control (ASC) field, permitting up to 16 access registers (0-15) to designate dataspaces and regions via access-list-entry tokens (ALETs). This supports efficient private space operations beyond traditional primary/secondary spaces. Compatibility is preserved by retaining XA PSW formats and adding a dedicated mode for System/370 emulation, allowing legacy applications to run unaltered on S/390 hardware. As part of the 1990s shift to scalable enterprise systems, ESA's PSW design facilitated the consolidation of mainframe workloads in partitioned environments.[16] Key field specifics include bit 16, which designates the addressing mode (AMODE) as part of the ASC configuration, and bit 14, which indicates problem state (zero for supervisor, one for problem state). ASN (access space number) fields, inherited from XA and managed via control registers 3 and 4, integrate with the PSW's ASC bits to enable multi-space operations, where each space is limited to 2 GB under 31-bit addressing. The following table summarizes the primary PSW fields relevant to ESA/390 EC mode:| Bit Position | Field Name | Description |
|---|---|---|
| 22 | HFP Exponent Underflow Mask | Controls underflow response: 0 sets result to zero; 1 normalizes fraction. |
| 24-31 | Space-Switch Event | Manages events for address space transitions (e.g., via PROGRAM CALL). |
| 32-63 | Instruction Address | 31-bit address of the next instruction to execute (bits 33-63 effective). |
| 16 | AMODE (in ASC) | Specifies addressing mode within address space control (00/01/10/11 codes). |
| 14 | Problem State | 0 for supervisor (privileged); 1 for problem (user) state. |
| ASC (15-17) | Address Space Control | Selects mode: primary (00), access-register (01), secondary (10), home (11); integrates ASN for multi-space access up to 2 GB per space. |
z/Architecture Format
The z/Architecture format defines the Program Status Word (PSW) for IBM Z mainframes, emphasizing 64-bit addressing capabilities introduced to handle vast memory spaces in enterprise computing. This 128-bit long PSW supersedes prior 64-bit formats by incorporating extended fields for address space management and protection, enabling operations on systems supporting up to 16 exabytes of virtual memory. It builds briefly on the Enterprise Systems Architecture (ESA) foundation but introduces incompatible changes for full 64-bit support, aligning with the architectural shift toward larger-scale processing as seen in successors to System/370.[17] The long PSW structure spans 128 bits, with specific fields allocated as follows:| Bits | Field | Description |
|---|---|---|
| 0–55 | Format and Control | Includes interruption masks (e.g., I/O mask bits 0-4 at 0-4, external at 6), wait state (13), problem state (14), address-space control (17-19), machine-check mask (12), and other control bits such as DAT mode (5) and PSW key (8–11). These govern execution state, privilege levels, and interruption handling. |
| 56–57 | Condition Code (CC) | A 2-bit code (values 0–3) indicating the outcome of the most recent instruction, used for branching decisions and status checks. |
| 58–61 | Program Mask | Controls responses to exceptions like fixed-point overflow (58), decimal overflow (59), HFP overflow (60), significance (61). |
| 62–63 | Other Masks | Additional masks for exponent overflow/underflow. |
| 64–127 | Instruction Address | 64-bit address of the next instruction to execute. |