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Stuck-at fault

A stuck-at fault is a widely used fault model in digital circuit testing that assumes a signal line or net is permanently fixed at a logic value of 0 (stuck-at-0) or 1 (stuck-at-1), regardless of the intended input or control signals driving it.^[1] This model represents common manufacturing defects, such as opens, shorts, or contact failures, that cause the affected line to exhibit a constant logical behavior at the gate level.^[2] In practice, stuck-at faults are categorized into single stuck-at faults, where only one line is affected, and multiple stuck-at faults, involving any combination of lines stuck at 0 or 1 across the circuit (totaling $3^k - 1 possible faults for k potential sites).^[3] The model assumes faults occur at interconnections between Boolean gates like AND, OR, NAND, NOR, and NOT, and that a single fanout branch may be independently faulty.^[1] Its importance lies in enabling structural testing approaches that avoid exhaustive input combinations—impractical for complex integrated circuits with billions of transistors—by instead applying targeted test patterns to propagate faulty values to observable outputs.^[2] Stuck-at faults play a central role in automatic test pattern generation (ATPG) tools and fault simulation software, where test vectors are derived to detect faults by sensitizing paths and measuring coverage, often aiming for over 99% for single faults.^[1] Key properties enhance efficiency: fault equivalence groups indistinguishable faults (e.g., collapsing up to 62.5% of the fault set in simple circuits), while dominance further reduces the set by identifying tests that cover multiple faults (e.g., to 47% collapse ratio).^[3] The checkpoint theorem states that tests targeting faults at primary inputs and fanout branches detect all single and multiple stuck-at faults in combinational circuits.^[3] Introduced by R.D. Eldred in his 1959 paper "Test Routines Based on Symbolic Logical Statements" as a practical alternative to full enumeration testing, the stuck-at model has become a cornerstone of design-for-testability (DFT) methodologies, though it has limitations in capturing timing-related or dynamic defects in modern technologies like CMOS.^[2]^[4] Despite these, its simplicity and tool support make it the primary target for ensuring reliability in VLSI and ASIC designs.^[3]

Fundamentals

Definition and Basic Concepts

A stuck-at fault is a fault model used in digital circuit testing, where a signal line or node in a combinational or sequential circuit is permanently fixed to a constant logic value of either 0 or 1, irrespective of the inputs applied to the circuit.^[5] This abstraction represents various physical manufacturing defects, such as open circuits, shorts between lines, or transistor failures, by capturing their effect at the logical level rather than modeling the precise physical mechanism. Unlike physical defect models, which operate at the analog or device level, the stuck-at model is a behavioral and logical abstraction designed to facilitate efficient simulation and automatic test pattern generation for verifying circuit functionality.^[5] The model employs binary logic values, with a stuck-at-0 (s-a-0) fault indicating the node is fixed at logic low (ground or 0V), and a stuck-at-1 (s-a-1) fault indicating it is fixed at logic high (Vdd or supply voltage). In fault simulation tools, an undefined state (X) may be used to represent unknown or uninitialized values during propagation analysis, but the primary focus remains on binary s-a-0 and s-a-1 faults to model realistic defect behaviors. This terminology applies to nodes in digital circuits, which include primary inputs, primary outputs, internal wires connecting components, and storage elements in sequential logic. Stuck-at faults occur within the context of digital circuits composed of Boolean logic gates, such as AND, OR, and NAND, where signals propagate through interconnected nodes to compute outputs based on input combinations.^[5] For instance, consider a two-input AND gate with inputs A and B, normally producing output 0 for input pairs (0,0) or (0,1). If the output node experiences an s-a-1 fault, it will incorrectly output 1 for these inputs, mimicking a short to Vdd that overrides the gate's logic.

Historical Development

The stuck-at fault model originated in the late 1950s as a response to the growing complexity of digital circuit testing, predating the widespread adoption of integrated circuits. In 1959, R. D. Eldred introduced foundational concepts for structural testing in his paper on symbolic logic statements for verifying digital systems, emphasizing the need for efficient test routines to detect logical inconsistencies without exhaustive enumeration.^[4] This work laid the groundwork for abstracting physical defects into logical faults, focusing on signal lines fixed at constant values (0 or 1), which addressed the impracticality of complete functional testing for increasingly large circuits. The model was formally defined and named in 1961 by J. M. Galey, R. E. Norby, and J. P. Roth.^[5] During the 1960s and 1970s, the model gained prominence with the rise of transistor-transistor logic (TTL) circuits, where its simplicity in representing manufacturing defects made it a standard for test generation. J. P. Roth's 1966 D-algorithm formalized path sensitization techniques specifically for stuck-at faults, enabling systematic automatic test pattern generation (ATPG) and integrating the model into early testing tools. By the 1970s and into the 1980s, TTL manufacturers routinely advertised integrated circuit reliability in terms of stuck-at fault coverage percentages, often exceeding 99%, which solidified the model's industry acceptance due to its correlation with observed defect detection rates. The transition to complementary metal-oxide-semiconductor (CMOS) technology in the 1980s retained the stuck-at model's core utility but highlighted its limitations for emerging defect types, such as stuck-open faults where transistor paths fail to conduct without altering steady-state logic levels. Despite these gaps, the model persisted into the 21st century for very-large-scale integration (VLSI) testing, valued for its abstraction from physical details and effectiveness across design styles. In recent years, design-for-testability (DFT) methodologies continue to emphasize stuck-at faults as a baseline, increasingly alongside hybrid approaches incorporating delay and bridging models to address nanoscale challenges.^[6]

Types of Stuck-at Faults

Single Stuck-at Fault

The single stuck-at fault model assumes that exactly one line—whether an input, output, node, or interconnect—in the digital circuit is permanently fixed at a logic value of 0 (stuck-at-0) or 1 (stuck-at-1), while all other lines and components operate correctly under normal logic functions.^[7] This isolation to a single fault simplifies analysis and modeling, enabling efficient test generation without considering interactions among multiple defects.^[3] The model abstracts physical defects such as opens, shorts, or transistor failures into logical behaviors, focusing on observability at primary outputs. In a circuit with n lines (including inputs, internal nodes, and outputs), there are 2n possible single stuck-at faults, as each line can exhibit either a stuck-at-0 or stuck-at-1 condition.^[3] However, not all are unique due to structural properties of logic gates. Fault equivalence arises when two or more faults produce identical output responses for every possible input vector, meaning the same set of tests detects all equivalent faults.^[7] This reduces the effective number of faults to consider during testing; for instance, in a 2-input NAND gate, a stuck-at-0 on input A, a stuck-at-0 on input B, and a stuck-at-1 on the output are all equivalent, as each forces the output to logic 1 for all input combinations.^[7]

Fault Location	Stuck-at Value	Equivalent Behavior in 2-Input NAND Gate
Input A	0	Output fixed at 1 for all inputs
Input B	0	Output fixed at 1 for all inputs
Output	1	Output fixed at 1 for all inputs

Equivalence collapsing thus minimizes test set size by targeting representative faults from each class, often reducing the fault list by 30-50% in combinational circuits.^[3] Fault dominance provides further optimization, where one fault (the dominant) is detected by every test that detects another (the dominated) fault, but not necessarily vice versa.^[7] For example, in a 2-input OR gate, a stuck-at-1 on the output dominates stuck-at-1 faults on either input, since every test that detects an input stuck-at-1 fault (setting all inputs to 0 for normal output 0) also detects the output stuck-at-1 (faulty output 1). Dominance is particularly useful for gates with controlling values, allowing testers to prioritize harder-to-detect faults and collapse the list further—e.g., from 24 potential faults to 10 unique classes in a simple circuit—without losing coverage.^[7] In simulation, single stuck-at faults are injected by overriding the computed logic value at the fault site with the fixed stuck value (0 or 1) during each time step, then propagating effects through the circuit to observe differences at outputs.^[3] This method enables efficient verification of test vectors against the 2n fault population, adjusted for equivalence and dominance to focus on representative classes.^[7]

Multiple Stuck-at Faults

Multiple stuck-at faults occur when two or more signal lines in a digital circuit are simultaneously fixed at a constant logic value of 0 (stuck-at-0) or 1 (stuck-at-1), independent of their intended inputs.^[1] This model extends the single stuck-at fault by considering concurrent defects on multiple lines, where each affected line can independently assume one of the two stuck values. For a circuit with k potential fault sites, the total number of possible multiple stuck-at faults is $3^k - [1](/page/1), accounting for each site being fault-free, stuck-at-0, or stuck-at-1, while excluding the fully fault-free case.^[1] In practice, multiple stuck-at faults better reflect real-world manufacturing defects, such as those arising from lithography variations or contamination, which often produce clustered or simultaneous issues rather than isolated ones.^[8] However, exhaustive modeling and testing for all combinations become computationally infeasible due to the exponential growth in fault space, prompting reliance on approximations or statistical coverage metrics.^[1] Detection of multiple stuck-at faults benefits from incidental or "windfall" coverage provided by test sets designed for single stuck-at faults, where patterns sensitizing a single path often propagate effects from unintended multiple faults to observable outputs. For instance, in the Intel 181 ALU circuit, a complete single stuck-at fault test set achieves 99.963% coverage of all possible double stuck-at faults through such serendipitous detection.^[1] This high overlap reduces the need for dedicated multiple-fault tests in many scenarios, though full enumeration requires fault simulation to verify propagation for specific combinations. Challenges in multiple stuck-at fault detection arise primarily from masking effects, where the presence of one fault alters the circuit's logic behavior in a way that conceals the observable impact of another fault. For example, in a simple combinational circuit with inputs A, B, C, D and outputs involving gates E and F, the test vector ABCD=1010 detects single faults at B/1 and D/1 but fails to detect the multiple fault (E/1, F/1) due to masking, necessitating additional patterns for confirmation.^[1] Addressing these requires advanced simulation techniques to enumerate and evaluate fault interactions, often involving fault dictionaries or probabilistic models. Compared to single stuck-at faults, which scale linearly with the number of lines (2n possibilities), multiple faults introduce exponential complexity, making targeted test generation impractical for large circuits without simplifications.^[1] Practical testing thus rarely aims to explicitly cover all multiples, instead leveraging single-fault tests for broad incidental detection while using simulation for high-risk scenarios. Algorithms for multiple stuck-at fault test generation exist, including methods that model arbitrary multiples as equivalent single faults through auxiliary gate insertions, as proposed in early work on large-circuit testing. These approaches, such as those using single-fault test sets to achieve high multiple-fault coverage, form the basis for efficient ATPG extensions, though they trade completeness for scalability.

Fault Detection Methods

Test Vector Generation

Test vector generation for stuck-at faults relies on the fundamental principle that a test vector detects a specific fault if it produces a differing output between the fault-free circuit and the faulty circuit under the same input application.^[9] This requires activating the fault—driving the faulty line to the opposite of its stuck value—and propagating the resulting discrepancy to an observable point, such as a primary output or flip-flop input.^[9] Path sensitization is the core technique for achieving this detection, involving the selection of a path from the faulty line to an output and assignment of input values to ensure the fault effect propagates along that path without interference from side inputs.^[10] For a stuck-at fault on line l, the process begins by setting inputs to activate the fault (e.g., forcing l to logic 1 for a stuck-at-0 fault), then sensitizing the path by controlling on-path signals to maintain the error while setting off-path signals to non-controlling values (0 for AND/OR gates, 1 for NAND/NOR gates).^[10] Justification follows to determine primary input values that support these assignments, ensuring the path is fully sensitized.^[10] Controllability measures the ease of setting a node to a desired logic value (0 or 1) from primary inputs, while observability quantifies how readily a node's value or fault effect can be propagated to a primary output.^[10] High controllability facilitates fault activation by allowing precise control over internal nodes, whereas high observability ensures the fault effect is visible, reducing the complexity of path sensitization.^[10] These metrics guide manual vector design by highlighting testable nodes and potential redundancies in circuit structures. In a manual example, consider a stuck-at-0 fault on input A of a 2-input AND gate with inputs A and B. To detect this fault, apply the test vector A=1, B=1, yielding an expected output of 1 in the fault-free gate but 0 in the faulty one, as the stuck input blocks the logic 1 propagation.^[11] Path sensitization here involves activating the fault by setting A to 1 and ensuring B=1 propagates the discrepancy directly to the output, requiring no further justification in this simple case.^[11] For a complete test set covering all single stuck-at faults in a 2-input NAND gate, the vectors 01, 10, and 11 suffice, detecting faults on inputs A-sa0, A-sa1, B-sa0, B-sa1, and output Z-sa0, Z-sa1, while 00 is unnecessary for single faults.^[12] These vectors systematically activate and propagate effects: for instance, 11 detects input stuck-at-0 faults by expecting Z=0 but observing Z=1 when an input is stuck at 0, and output stuck-at-1 by expecting Z=0 but observing Z=1.^[12] To verify detection, fault simulation injects the assumed fault into the circuit model and compares responses to the test vectors. Deductive simulation propagates sets of potential faults through the fault-free circuit using symbolic lists, efficiently handling multiple faults in a single pass for binary-valued stuck-at models.^[13] Concurrent simulation, in contrast, models both fault-free and faulty behaviors event-driven, scheduling changes only for affected signals to support flexible fault propagation across gate types.^[13] The effectiveness of a test set is evaluated using the fault coverage metric, defined as the percentage of modeled stuck-at faults detected by the vectors at the gate level.^[12] This metric provides a standardized measure of test quality, with complete coverage implying detection of all single detectable faults, though practical targets often exceed 95% to account for unmodeled defects.^[12]

Automatic Test Pattern Generation (ATPG)

Automatic Test Pattern Generation (ATPG) encompasses software tools that automatically produce test vectors to detect stuck-at faults in digital circuits, typically achieving fault coverage of 95-99% in modern designs.^[14] These tools employ algorithmic techniques to target specific faults by activating and propagating the fault effect to an observable output while ensuring consistency in signal assignments. ATPG is essential for combinational and scan-based sequential circuits, integrating with electronic design automation (EDA) flows to generate efficient test sets that minimize pattern count while maximizing coverage. The D-algorithm, developed by J. P. Roth in 1966, represents a foundational path sensitization method for ATPG. It utilizes a decision tree to explore signal assignments, introducing symbolic values D (indicating a difference where the fault-free circuit evaluates to 1 and the faulty to 0) and \bar{D} (fault-free 0, faulty 1) to abstractly represent fault effects without enumerating all possibilities. The algorithm proceeds in three key steps: first, fault activation by assigning values to set the faulty line to its opposite stuck value, creating a D or \bar{D} at the site; second, propagation by sensitizing a path from the fault site to a primary output or scan flip-flop, ensuring the difference reaches an observable point; and third, consistency checking via forward and backward implications to resolve conflicts in the assignment graph. This approach systematically builds test vectors but can suffer from high computational complexity due to extensive backtracking in large circuits. To address the inefficiencies of the D-algorithm, the PODEM (Path-Oriented DEcision Making) algorithm, proposed by Prabhakar Goel in 1981, reformulates test generation as a pseudoboolean satisfiability problem. It focuses on assigning values only to primary inputs and uses guided backtracking with implications to propagate constraints through the circuit, avoiding the exhaustive table lookups of the D-algorithm. By employing a heuristic decision tree that branches on input variables and checks satisfiability via Boolean constraints, PODEM significantly reduces search space and improves scalability for larger combinational circuits, often generating tests with fewer backtracks. Building on PODEM, the FAN (Fanout-oriented) algorithm, introduced by Hideo Fujiwara and Takeshi Shimono in 1983, enhances efficiency through fault-oriented branching and multiple backtrace techniques. It incorporates structural heuristics, such as unique sensitizing paths and dynamic assignment of implications at fanout points, to guide the search toward feasible solutions more rapidly. FAN propagates fault effects using gate-specific rules; for instance, in a Boolean AND gate, a D at one input propagates to the output only if all other inputs are assigned to 1, formalized as the implication where the output becomes D under the condition that the conjunction of non-faulty inputs equals 1. This targeted propagation minimizes unnecessary assignments and accelerates test generation for complex circuits. During ATPG, untestable faults are identified and handled, such as redundant stuck-at-1 faults on AND gate outputs, which cannot produce a detectable difference due to logical equivalence with fault-free behavior. These are marked as untestable, excluding them from coverage reports to focus resources on detectable faults. In contemporary practice, commercial ATPG tools like Synopsys TetraMAX integrate these algorithmic principles with design-for-testability (DFT) features, such as scan chains, to generate high-coverage patterns for stuck-at faults in large-scale VLSI designs.^[15] TetraMAX employs advanced variants of FAN-like methods, supporting collapsed fault simulation and parallel processing to achieve near-100% coverage efficiently within EDA suites.^[15]

Applications and Limitations

Use in Circuit Testing

In post-manufacturing testing of integrated circuits (ICs), stuck-at fault patterns generated via automatic test pattern generation (ATPG) are applied to detect defects by loading them into the chip through scan chains or boundary scan (IEEE 1149.1/JTAG) architectures. Scan chains connect flip-flops into a shift register, allowing test vectors to be serially shifted in and responses shifted out for comparison against expected fault-free (golden) outputs using automated test equipment (ATE). Boundary scan, implemented at I/O pins, facilitates similar pattern application for interconnect testing without physical probes, identifying issues like shorts or opens that manifest as stuck-at behaviors. This process ensures defective chips are screened out early, improving overall production yield.^[16]^[17]^[18] Fault coverage, defined as the percentage of detectable stuck-at faults identified by the test set, serves as a key metric in circuit testing, with industry targets typically exceeding 95% for production ICs to minimize test escapes and correlate with yield prediction models. Higher coverage, such as 97-99%, reduces latent defects that could lead to field failures, though achieving it requires balancing pattern count against test time. For example, in yield estimation, stuck-at coverage directly influences defect level projections, where a 96.6% coverage might predict field reject rates around 10,000 parts per million.^[19]^[20]^[21] Design for Testability (DFT) enhances stuck-at fault testing by incorporating scan flip-flops, which reconfigure sequential circuits as combinational logic during test mode, enabling ATPG tools to target faults more effectively and often achieving 85-98% coverage. Built-In Self-Test (BIST) further integrates stuck-at patterns on-chip, using pseudo-random or deterministic sequences to generate and compact responses autonomously, reducing reliance on external ATE for at-speed validation. These DFT elements add minimal overhead (1-5% area) but significantly boost testability in complex designs.^[16]^[17]^[22] The stuck-at fault model originated as a dominant approach in the TTL era of the 1970s-1980s for board-level testing of discrete logic, where manual and bed-of-nails fixtures applied patterns to verify interconnections. By 2025, it remains a baseline in VLSI flows, integrated into SoC testing via JTAG for hierarchical validation from die to system levels. In automotive and aerospace sectors, stuck-at testing supports reliability certification under standards like ISO 26262, ensuring high diagnostic coverage for safety-critical functions. For a representative VLSI chip with 1 million gates, compressed patterns can target 98% stuck-at coverage, compressing data volume by up to 100x while maintaining detection efficacy.^[23]^[24]^[25]^[26]

Limitations and Complementary Techniques

The stuck-at fault model assumes static logic behavior, where a signal line is permanently fixed at a logic value regardless of input stimuli, thereby failing to capture dynamic defects such as timing-related delay or transition faults that manifest under operational speeds.^[27] Bridging faults, involving unintended shorts between signal lines, are also inadequately represented, as they can produce non-classical logic outcomes like wired-AND or wired-OR behaviors not equivalent to simple stuck-at conditions.^[28] Similarly, stuck-open faults in CMOS circuits, which occur due to transistor opens, require two-pattern tests to sensitize and detect, as a single vector may not reveal the fault's impact on circuit function.^[29] In CMOS technologies, the stuck-at model exhibits further limitations, as single-pattern tests often fail to detect transistor-level opens, and the model overlooks quiescent current (IDDQ) variations that signal leakage or bridging defects without altering logic outputs.^[30] For instance, only a small percentage of opens and bridges can be pseudo-modeled as stuck-at faults, leading to incomplete coverage.^[30] Additionally, redundant faults in self-correcting or irredundant circuits remain unobservable under stuck-at testing, as these defects do not propagate to observable outputs due to inherent design redundancies.^[31] In modern nanoscale VLSI processes as of 2025, the stuck-at model struggles with atomic-scale defects that introduce variability beyond binary logic fixation, resulting in low coverage for multi-gate interactions and emerging issues like process variations.^[32] For 3D integrated circuits (ICs), traditional stuck-at testing provides baseline coverage but inadequately addresses inter-layer via defects and through-silicon via (TSV) faults, which often require delay-sensitive models to achieve comprehensive detection.^[33] To address these shortcomings, complementary techniques such as IDDQ testing measure supply current to detect CMOS leaks and bridges invisible to voltage-based stuck-at tests, offering higher sensitivity to physical defects.^[34] Transition fault models target timing defects by verifying signal transitions within clock cycles, capturing delays missed by static stuck-at patterns.^[27] Bridging fault models, including wired-AND/OR simulations, explicitly account for shorts between lines, enabling targeted test generation.^[35] Hybrid approaches treat stuck-at as a foundational baseline, augmented by at-speed testing for transition faults to ensure functional timing integrity in high-performance designs.^[33] In contemporary 2025 flows, AI-enhanced diagnosis integrates machine learning with stuck-at simulations to predict and isolate complex faults, improving accuracy in nanoscale and 3D ICs through pattern recognition of failure data.^[36] For example, a bridging fault between two adjacent lines may not manifest as a stuck-at equivalent, necessitating dedicated bridging simulations to activate and observe the short's dominant logic effect.^[28]

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