Intel 8087
The Intel 8087, officially known as the Numeric Data Processor (NDP), is a floating-point coprocessor chip released by Intel in 1980 to enhance numeric computation capabilities for the 8086 and 8088 microprocessors, as well as the i432 architecture.[1][2] It performs high-speed arithmetic and comparison operations on a range of data types, including single-precision (32-bit), double-precision (64-bit), and extended-precision (80-bit) floating-point numbers, alongside integer and packed binary-coded decimal formats, enabling efficient handling of complex mathematical tasks that would otherwise burden the host CPU.[3][4] Development of the 8087 began in 1976 under the leadership of Intel engineer John Palmer, with mathematician William Kahan serving as a key consultant to ensure mathematical accuracy and portability.[4][2] Fabricated using HMOS technology with approximately 40,000 transistors, the chip integrates a microprogrammed control unit, an 80-bit register stack for operands, and an on-chip ROM containing a comprehensive math library that supports transcendental functions like sine, cosine, logarithm, and exponentiation, alongside basic operations such as addition, subtraction, multiplication, and division.[2][3] The 8087 communicates with the host processor via a shared 20-bit address bus and 16-bit data bus, using escape instructions (ESC) in the 8086 instruction set to invoke its operations, and it signals busy states through dedicated pins to synchronize execution.[3] A defining aspect of the 8087 is its foundational influence on the IEEE 754 floating-point standard, ratified in 1985; its specifications for precisions, exponent ranges, special values like Not-a-Number (NaN) and infinities, and the innovative concept of gradual underflow via subnormal numbers were disclosed by Kahan and Palmer to the IEEE P754 committee in the late 1970s, shaping the K-C-S draft that became the basis for the standard.[4][2] This design prioritized Intel's "REALMATH" goals of high performance, ease of use, and consistent results across software environments, making it essential for early personal computers and scientific applications requiring precise real-number calculations.[3] The 8087's architecture set precedents for subsequent coprocessors like the 80287 and integrated FPUs in later x86 processors, marking a pivotal advancement in microprocessor numeric processing during the late 1970s and early 1980s.[1][4]History and Development
Background and Design Goals
In the late 1970s, Intel initiated development of the 8087 Numeric Data Processor to address the limitations of the 8086 microprocessor, which lacked native support for floating-point arithmetic essential for scientific and engineering applications. Development began in 1976 under the leadership of John Palmer, with mathematician William Kahan serving as a key consultant to ensure mathematical accuracy.[1] The 8086, introduced in 1978, prioritized integer operations for general-purpose computing, leaving complex numerical tasks to software emulation that was both slow and error-prone, motivating the creation of a dedicated coprocessor to accelerate computations like addition, subtraction, multiplication, division, and square root by offloading them from the host CPU.[5] This effort aligned with the growing demand for affordable, high-performance personal computing systems capable of handling advanced mathematical workloads without requiring expensive mainframe upgrades.[6] Key design goals emphasized high-speed performance through microcoded execution, enabling efficient handling of numeric instructions while maintaining tight integration with the 8086 via a shared bus and coprocessing protocol.[5] The architecture adopted a stack-based model to reduce register management overhead, allowing seamless operand handling in numeric operations.[1] Compatibility was prioritized by using escape instructions in 8086 software to invoke 8087 functions, ensuring minimal changes to existing codebases and promoting adoption in embedded and desktop systems.[5] These objectives drew partial influence from earlier numeric processors like the Intel 8231, but focused on deeper synchronization with the 8086/8088 family for overlapped execution.[5] The project was led by Intel's arithmetic unit team, with architectural design by John F. Palmer and Bruce Ravenel, and implementation handled by Rafi Nave's group in Israel; prototypes were ready by 1979, culminating in the 8087's release in 1980 as Intel's largest and most complex microprocessor to date.[1][5]Announcement and Production
The Intel 8087 numeric coprocessor was announced by Intel in June 1980, initially specified to operate at a 5 MHz clock speed. First commercial shipments began in 1980, with widespread availability achieved by 1981.[7] Production of the 8087 utilized Intel's HMOS III manufacturing process, starting with a 4.5 μm feature size that was later refined to 3 μm for improved efficiency.[8] The die contained approximately 40,000 transistors, reflecting the chip's complex design for handling floating-point operations.[8] A key factor in the 8087's early adoption was the inclusion of an optional socket on the motherboard of the IBM PC, launched in 1981, which allowed users to add the coprocessor for enhanced numeric performance. Despite its high initial cost of $150 to $300, this design choice facilitated integration into personal computing systems and drove sales among developers of math-intensive applications.[9] Early production encountered challenges, including yield issues stemming from the chip's high transistor density and intricate microcode ROM implementation, which contributed to delays in scaling output.[7] Overall production continued into the mid-1990s to support legacy 8086-based systems.Physical and Electrical Characteristics
Manufacturing Process
The Intel 8087 numeric data processor was fabricated using an N-channel depletion-load silicon gate high-performance MOS (HMOS) process, which enabled high-speed operation while maintaining compatibility with the 8086 microprocessor family.[10] This HMOS III technology featured minimum dimensions of approximately 4 μm for polysilicon spacing and 5 μm for diffusion regions, reflecting the state-of-the-art semiconductor fabrication techniques of the early 1980s that balanced density and yield.[9] Later production runs achieved a process shrink to around 3 μm, improving performance and reducing costs without altering the core design.[10] The silicon die measured roughly 5 mm by 6 mm and contained approximately 40,000 transistors, as determined through detailed reverse engineering of delidded chips.[9] This transistor budget supported essential components such as a microcode ROM for instruction decoding and control, along with dedicated arithmetic pipelines for floating-point operations, pushing the boundaries of NMOS integration at the time.[11] A key innovation in the chip's layout was the hardware implementation of the CORDIC (COordinate Rotation DIgital Computer) algorithm for computing transcendental functions like sine, cosine, tangent, and logarithms; this approach used simple shift-and-add operations with pre-stored ROM constants (such as arctan(2^{-n}) values) instead of resource-intensive multipliers, thereby optimizing silicon area and execution speed to just 16 cycles per iteration.[12] To manage power while enhancing transistor performance, the 8087 incorporated a substrate bias circuit that generated a negative voltage (approximately -3 V) from the single +5 V supply using on-chip charge pumps.[11] This bias reduced leakage currents and improved switching speeds in the NMOS devices. Typical power dissipation was around 2 W when operating at 5 MHz, with maximum ratings up to 2.4 W under full load, making it suitable for integration into contemporary PC systems without excessive thermal demands.[13]Package and Pinout
The Intel 8087 is housed in a 40-pin Ceramic Dual In-line Package (CERDIP) measuring 52.5 mm in length, 13.8 mm in width, and 5.1 mm in height.[14] This package type provides robust hermetic sealing suitable for commercial applications and facilitates direct integration with 8086/8088-based systems via a standard DIP socket. The pinout configuration supports multiplexed operation with the host CPU, featuring 20 shared address/data lines labeled AD0 through AD19 for bidirectional transfer of operands and results.[14] Control signals include BUSY# (active low) to indicate the coprocessor is executing an instruction and cannot accept new commands, ERROR# (active low) to flag arithmetic exceptions or invalid operations, and REQUEST# (active low) for the 8087 to request bus control from the CPU during data fetches. Additional pins encompass standard bus interface signals such as CLK for synchronization, RESET for initialization, INTR for interrupt generation, and power connections with VCC at +5 V and multiple GND returns for stable operation.| Key Pin Category | Pins | Function |
|---|---|---|
| Address/Data | AD0–AD19 | Multiplexed lines for 20-bit addressing and 16-bit data I/O, compatible with 8086/8088 bus.[14] |
| Control/Status | BUSY#, ERROR#, REQUEST# | BUSY# signals active computation; ERROR# reports faults; REQUEST# handles bus arbitration.[14] |
| Power/Ground | VCC, GND (multiple) | +5 V supply and grounds for TTL-level signaling.[14] |