Non-maskable interrupt
A non-maskable interrupt (NMI) is a hardware-generated signal in computer processors that cannot be disabled or ignored through standard interrupt-masking techniques, ensuring immediate response to critical system conditions.[1] These interrupts are typically delivered via a dedicated input line separate from those used for regular interrupts, allowing them to preempt ongoing operations without interference.[1] In contrast to maskable interrupts, which can be temporarily blocked by the processor (for example, by clearing the interrupt enable flag in x86 architectures), NMIs maintain full priority and are serviced even when masking is active, making them essential for unignorable events like hardware malfunctions.[2] This design prevents scenarios where vital signals, such as error detections, could be lost during periods of interrupt suppression, thereby enhancing system reliability.[1] NMIs are implemented across major processor architectures with specific handling mechanisms; in x86 systems, they are processed via interrupt vector 2 in the Interrupt Descriptor Table (IDT), often triggered by events like parity errors.[2] In ARM A-profile processors, support for NMIs was extended in 2021 to enable features like performance profiling and debugging, using configurable priorities in the Generic Interrupt Controller (GIC) and separate acknowledgment registers.[3] Common applications include signaling fatal hardware errors that may precede a system crash, monitoring for lockups via watchdog timers, and facilitating low-level diagnostics in real-time environments.[1]Fundamentals
Definition and purpose
A non-maskable interrupt (NMI) is a hardware interrupt that cannot be disabled or ignored by the processor using standard interrupt masking techniques, ensuring it always receives immediate attention regardless of the system's current interrupt state.[4][1] This distinguishes NMIs from other interrupts by their unyielding nature, as they operate independently of any maskable interrupt controller settings.[5] The primary purpose of an NMI is to address critical, high-priority events that demand instantaneous processor response to avert system instability, data corruption, or complete failure.[6] These events are typically non-recoverable hardware issues where delaying action could lead to irreversible damage, such as imminent system crashes or loss of operational integrity.[1] By design, NMIs facilitate emergency measures like data preservation or diagnostic logging before the system halts.[7] Key characteristics of NMIs include their assignment to the highest interrupt priority level, where they preempt all maskable interrupts and cannot themselves be preempted, guaranteeing minimal latency in response.[5] They are triggered asynchronously by dedicated hardware signals, often via a separate interrupt line, prompting an immediate context switch to execute a specialized NMI handler routine that preserves the processor state for efficient recovery or analysis.[1][5] Common triggering events for NMIs encompass watchdog timer overflows, which signal software hangs or lockups; power failure warnings that enable last-minute data backups; and thermal shutdown signals to mitigate overheating risks.[6][7] These examples illustrate NMIs' role in safeguarding system reliability during unforeseen hardware crises.[4]Comparison with maskable interrupts
Maskable interrupts are hardware or software signals that the processor can temporarily disable or ignore through dedicated control mechanisms, such as flags in status registers, to ensure uninterrupted execution during critical operations or to manage system priorities.[1] This capability allows software to defer less urgent interruptions, facilitating atomic code execution and efficient resource allocation in multitasking environments.[8] In contrast, non-maskable interrupts (NMIs) completely bypass these masking mechanisms, guaranteeing their service regardless of the processor's interrupt enable state; for example, in x86 architectures, NMIs ignore the Interrupt Flag (IF) in the EFLAGS register, which otherwise blocks maskable interrupts.[9] Maskable interrupts support hierarchical prioritization managed by dedicated hardware like the Programmable Interrupt Controller (PIC) or Advanced Programmable Interrupt Controller (APIC), enabling the system to rank and queue sources based on urgency.[9] NMIs, however, operate outside this framework with inherent highest priority, invoking their handlers directly without deferral or queuing.[10] The design of NMIs introduces key trade-offs: they ensure reliable, immediate response to vital conditions but may intrude on protected code sections where maskable interrupts are disabled, risking interference with ongoing atomic operations or shared resource updates.[11] Conversely, maskable interrupts promote flexible multitasking and controlled handling but carry the potential for overlooked events if disabled at the moment of assertion, particularly during error-prone intervals.[12]| Aspect | Maskable Interrupts | Non-Maskable Interrupts |
|---|---|---|
| Masking Capability | Can be disabled globally or selectively (e.g., via IF flag in x86)[9] | Cannot be disabled or ignored by software or flags[1] |
| Priority Handling | Supports prioritization and queuing via controllers (e.g., PIC/APIC)[9] | Inherently highest priority; no queuing or deferral[10] |
| Typical Sources | Peripheral I/O devices, timers, and software events[12] | Critical hardware faults like memory errors or power issues[10] |
| Handler Invocation | Routed through vector table after priority resolution and masking check[9] | Immediate execution via dedicated mechanism, preempting all others[1] |