Three-state logic
Three-state logic, also known as tri-state logic, is a fundamental concept in digital electronics where circuit outputs can assume one of three distinct states: logic high (representing 1), logic low (representing 0), or high-impedance (Hi-Z), a floating state that electrically isolates the output as if disconnected.[1] This third state enables multiple devices to share common signal lines, such as data buses, without causing electrical conflicts or contention that could damage components or corrupt signals.[2] At its core, three-state logic is realized through tri-state buffers or drivers, which are specialized digital circuits featuring two primary inputs: a data input and an enable (or control) input.[1] When the enable signal is active (e.g., logic high for active-high configurations), the output mirrors the data input, functioning as a standard non-inverting or inverting buffer to amplify or isolate signals.[3] Conversely, when the enable is inactive, the output enters the Hi-Z state, drawing negligible current and behaving like an open circuit, regardless of the data input.[1] Common implementations include integrated circuits like the 74LS244 (octal buffer) or 74HC245 (bidirectional transceiver), often built using CMOS or TTL technologies for compatibility with various voltage levels.[2] The primary advantage of three-state logic lies in its ability to support multiplexed bus architectures, where decoders or control logic ensure only one driver is active at a time on a shared line.[3] This design reduces wiring complexity, lowers power consumption in idle states, and enhances scalability in integrated systems.[1] In computer architecture, it is indispensable for connecting memory, processors, and peripherals to address and data buses, facilitating efficient bidirectional communication.[2] Variations include active-low enable pins for inverted control and bidirectional buffers for read/write operations, with fan-out capabilities supporting up to 20 standard loads in TTL variants.[1]Fundamentals
Definition and Purpose
Three-state logic, also known as tri-state logic, refers to a type of digital circuit output that can assume one of three distinct states: a logic high (representing 1), a logic low (representing 0), or a high-impedance state (often denoted as Z), in which the output is electrically disconnected from the rest of the circuit, effectively presenting no load to connected lines.[4] This high-impedance state allows the output to float without influencing the signal on shared lines, extending beyond the binary states of traditional two-state logic gates. The primary purpose of three-state logic is to facilitate efficient resource sharing in electronic systems, particularly by enabling multiple devices to connect to a single common signal line, or bus, without causing electrical conflicts known as bus contention. In this setup, only one device at a time actively drives the bus to a high or low state, while others remain in the high-impedance mode, preventing interference and allowing for signal multiplexing where data from various sources can be selectively routed over the same pathway.[4] This capability is essential for reducing wiring complexity and improving scalability in integrated circuits and digital systems. Three-state logic originated in the late 1960s amid the rapid development of transistor-transistor logic (TTL) integrated circuits, which addressed the limitations of earlier two-state logic in handling increasingly complex interconnections in computing hardware. Specifically, it was introduced by engineer Dale Mrazek at National Semiconductor in 1967 as an enhancement to the 7400 series TTL family, originally developed by Texas Instruments, enabling the first commercial tri-state devices for bus-oriented applications.[5] This innovation built on the foundational binary logic gate concepts but provided a practical extension for shared communication lines in emerging digital architectures.States and Electrical Characteristics
In three-state logic, the output can assume one of three distinct states, each characterized by specific voltage levels and impedance properties. The logic high state (denoted as '1') occurs when the output is actively driven to a voltage near the supply voltage, VCC, typically +5 V in traditional TTL implementations. In this state, the output acts as a current source, capable of sourcing up to several milliamperes (e.g., 2.6 mA minimum for VOH = 2.4 V in buffer devices like the SN54LS125A) to maintain the line high against connected loads.[6] The logic low state (denoted as '0') drives the output to a voltage close to ground (0 V), functioning as a current sink that pulls the line low. For TTL devices, the maximum low-level output voltage, VOL, is 0.4 V when sinking 12 mA (as specified for devices like the SN54LS125A), ensuring reliable low signaling without excessive voltage drop. This state exhibits low output impedance, typically in the range of 50–100 Ω, allowing effective drive of capacitive or resistive loads.[6] The high-impedance state (denoted as 'Z') renders the output effectively disconnected from the circuit, behaving as an open circuit with output impedance modeled as Z_{\text{out}} \approx \infty, in contrast to the 50–100 Ω impedance of the active high or low states. This state features very high impedance (typically in the range of hundreds of kΩ to several MΩ depending on the logic family and conditions), with off-state leakage current typically much less than 1 μA but with maximum values of up to ±20 μA in TTL and ±10 μA in CMOS implementations (e.g., at VCC = 5.5 V), preventing loading effects on shared lines driven by other devices.[6][7] Electrically, these states vary between logic families. In TTL, input high voltage threshold (VIH) is at least 2 V and input low (VIL) at most 0.8 V, with output high (VOH) minimum 2.4 V and low (VOL) maximum 0.4 V, providing noise margins of about 0.4 V. CMOS implementations, such as HCT series compatible with TTL levels, offer similar thresholds (VIH ≥ 2 V, VIL ≤ 0.8 V) but achieve higher VOH (up to 4.4 V minimum at low current) and lower VOL (0.1 V maximum), with superior noise margins exceeding 1 V due to rail-to-rail outputs. In the Z state, CMOS exhibits particularly low power dissipation, as the output transistors are off, resulting in negligible static current (typically <1 μA per gate) compared to active states where dynamic switching consumes power proportional to load capacitance and frequency.[6][7]Operation
High-Impedance Mechanism
The high-impedance state in three-state logic devices is achieved through internal circuitry that isolates the output node from the power supply and ground when the enable signal is inactive, effectively creating an open circuit with very high output impedance, typically on the order of megohms.[8] This isolation prevents the device from sourcing or sinking current, allowing other devices to drive the shared line without contention. In CMOS implementations, a common approach uses a tri-state buffer or inverter where the output path incorporates a transmission gate formed by a PMOS transistor and an NMOS transistor in parallel, controlled by complementary enable signals. When the enable input (EN) is low, the PMOS is off (gate high) and the NMOS is off (gate low), disconnecting the logic circuitry from the output and resulting in the high-impedance (Z) state regardless of the input.[9] For a tri-state inverter variant, additional inverter stages restore the logic level during active operation, but the enable mechanism similarly gates the output transistors to float the pin when disabled. A textual schematic breakdown illustrates this: the input feeds an inverter pair to generate the output logic; this inverted signal then drives the gates of a pull-up PMOS and pull-down NMOS in the output stage; a separate enable inverter provides EN-bar to the gate of a series PMOS and EN to the gate of a series NMOS, ensuring both are non-conducting in the Z state.[9] In TTL devices, such as the 74LS244 octal buffer, the high-impedance state is realized by modifying the standard totem-pole output configuration with an enable transistor that disables both the upper Darlington pair (for high output) and the lower NPN transistor (for low output). When the output-enable input (G) is high, this control transistor turns off the base drives to the output stage, floating the collector-emitter path and isolating the output.[1] The totem-pole structure normally provides low-impedance drive (high for sourcing ~400 μA, low for sinking ~8 mA), but in Z mode, the output impedance rises dramatically, mimicking an open connection. A simplified schematic description shows: the input logic drives phase-splitter transistors; the enable signal gates a PNP or additional NPN to cut off current to the output Darlington (Q3-Q4 for high) and totem-pole lower (Q5), leaving the output pin undriven.[1] Transitioning into or out of the high-impedance state introduces propagation delays due to the time required to charge/discharge internal nodes and the output capacitance. In standard TTL like the 74LS244, the disable time from low to Z (tPLZ) is approximately 10-20 ns, and from high to Z (tPHZ) is 15-25 ns, measured under typical conditions (VCC=5 V, CL=5 pF).[10] These delays ensure reliable bus arbitration but must be considered in high-speed designs to avoid glitches during state changes.[10]Enable and Disable Processes
In three-state logic, the enable process activates the output buffer through an enable signal, typically denoted as EN, which can be configured as active-high or active-low. When asserted—for instance, logic high for active-high designs—the buffer connects the input data signal D to the output Q, driving it to a logic low (0) or high (1) state accordingly, thereby allowing the device to participate in bus communication. This activation requires adherence to timing parameters such as setup time (the minimum duration the data must be stable before the enable transition) and hold time (the minimum duration after the transition), with examples in 3.3 V CMOS buffers like the SN74LVC1G125 specifying a setup time of approximately 2 ns.[11] The propagation delay from enable assertion to output stabilization is also critical, around 4 ns typical in such devices.[11] The disable process occurs when the enable signal is deasserted, causing the output to transition to the high-impedance state (Z), effectively isolating the device from the bus and preventing it from influencing other connected components. This deassertion typically takes a disable time (t_dis) of 4.6 ns or less in high-speed buffers at 3.3 V, during which the output impedance rises to several megaohms, mimicking an open circuit.[12] However, if multiple tri-state devices share a bus and their enable signals are not properly synchronized, brief contention may arise, where outputs momentarily drive conflicting levels, potentially leading to increased current draw or logic errors.[13] To mitigate this, disable timing must overlap minimally with other devices' enable periods, often managed through clocked control.[14] Control logic for three-state outputs commonly employs simple combinational gates, such as AND or OR structures integrated within the buffer, to combine the enable signal with the data input. The output behavior can be represented symbolically as: if EN = 1, then Q = D; if EN = 0, then Q = Z (where Z denotes high-impedance). This logic ensures the device only drives the bus when enabled, as illustrated in the following truth table for an active-high enable configuration:| EN | D | Q |
|---|---|---|
| 1 | 0 | 0 |
| 1 | 1 | 1 |
| 0 | 0 | Z |
| 0 | 1 | Z |