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Power gating

Power gating is a low-power circuit design technique employed in integrated circuits, particularly in application-specific integrated circuits (ASICs) and system-on-chip (SoCs), to minimize static leakage power consumption by selectively shutting off the power supply to inactive logic blocks or cells through the use of sleep transistors.^[1] This method operates by partitioning the chip into power domains—some always-on for essential functions and others switchable—allowing fine-grained control where power can be gated to individual modules without affecting active regions.^[1] Originating from multi-threshold CMOS (MTCMOS) approaches, power gating has become a standard practice in nanoscale VLSI designs to combat the increasing dominance of subthreshold leakage currents as transistor sizes shrink below 90 nm.^[2] At its core, power gating inserts high-threshold-voltage (high-Vt) sleep transistors—either header switches (pMOS) between the actual power supply (VDD) and the virtual power supply (VDDV), or footer switches (nMOS) between the virtual ground (VSSV) and the actual ground (VSS)—to isolate idle circuits from the main power rails during sleep mode, effectively reducing leakage by factors of 10 to 50 times compared to always-on operation.^[1] Complementary isolation cells prevent erroneous signal propagation from powered-off domains to active ones, while state-retention flip-flops preserve critical data during power-down transitions, ensuring seamless mode switching.^[2] Design methodologies involve hierarchical switch sizing to balance area overhead (typically 5-15%) and wakeup latency, alongside power grid analysis tools to mitigate IR drop and electromigration issues in the power delivery network.^[2] Despite its effectiveness, power gating introduces challenges such as increased design complexity, including design-for-test (DFT) considerations for multi-domain verification and small timing penalties from insertion logic and state recovery sequences.^[1] Hybrid implementations often combine it with other techniques like multi-Vt cell libraries or dynamic voltage scaling for further optimization, and advancements continue to focus on reducing switch sizes and transition energies to enhance applicability in high-performance mobile and server processors.^[2]

Introduction

Definition and Purpose

Power gating is a low-power design technique employed in integrated circuit (IC) design to mitigate power consumption by disconnecting the power supply from inactive logic blocks within CMOS circuits. This method utilizes high-threshold voltage (HVT) sleep transistors, also known as power switches, to effectively isolate these blocks from the primary power rails.^[3]^[4] The primary purpose of power gating is to substantially reduce leakage power dissipation during standby or idle modes, where circuits are not actively switching but still consume significant static power due to subthreshold leakage currents. By implementing power gating, subthreshold leakage can be reduced by up to three orders of magnitude, enabling more efficient energy management in deep-submicron technologies where leakage dominates overall power usage.^[5] In operation, power switches—typically implemented as footer transistors (NMOS between the logic and ground) or header transistors (PMOS between the logic and VDD)—are turned off to isolate inactive blocks, causing the virtual supply rails to discharge or charge to near-zero voltage relative to the power domain. This collapse of the virtual rails severs the leakage paths, minimizing current flow through the gated logic without affecting active portions of the circuit.^[6] For instance, in CMOS designs, power gating targets unused combinational and sequential logic blocks, allowing them to enter a zero-power state, while elements like clock distribution networks remain powered to maintain synchronization across the chip.^[3]

Historical Context

Power gating emerged as a response to the increasing dominance of leakage power in CMOS integrated circuits during the late 1990s, particularly as process nodes scaled below 0.18 μm, where subthreshold and gate leakage currents began to significantly outpace dynamic power dissipation.^[7] Early efforts focused on multi-threshold CMOS (MTCMOS) techniques to mitigate standby leakage while preserving performance in active modes. The foundational MTCMOS approach, which inserts high-threshold sleep transistors to isolate logic blocks from power supplies during idle periods, was introduced by Mutoh et al. in 1995, enabling low-voltage operation with reduced leakage in high-speed digital circuits. This innovation laid the groundwork for power gating by demonstrating how threshold voltage engineering could balance speed and power efficiency in deep submicron technologies.^[8] Key milestones in practical implementation occurred around 2000–2002, with the first applications in low-power application-specific integrated circuits (ASICs) targeting embedded systems. A seminal contribution was the Gated-Vdd technique proposed by Powell et al. in 2000, which applied power gating to deep-submicron cache memories using header transistors to cut off virtual supply rails, achieving substantial leakage reductions without excessive area overhead.^[9] By 2002, similar methods were integrated into processor designs, marking the shift from theoretical concepts to deployable circuit-level solutions. Widespread adoption accelerated post-2005, driven by the 90 nm process node where leakage constituted up to 50% of total power in mobile and embedded devices; techniques like MTCMOS power gating became standard in battery-constrained applications, such as wireless SoCs, to enable ultra-low standby currents.^[10] Influential IEEE works, including Keshavarzi et al.'s 1997 analysis of intrinsic leakage mechanisms, further underscored the urgency of such methods by quantifying how scaling exacerbated standby power in sub-0.25 μm CMOS.^[7] The integration of power gating as a standard technique in high-volume processors was exemplified by its incorporation in Intel's 45 nm process nodes starting in 2007, where it complemented high-k metal gate transistors to address escalating leakage in server and client CPUs.^[11] Over the subsequent decade, power gating evolved from simple block-level implementations—using large sleep transistors for entire modules—to more sophisticated hierarchical and distributed schemes, particularly in sub-10 nm nodes by the 2020s. These advanced variants employ multi-level isolation (e.g., fine-grained gating within clusters) to minimize wakeup latency and overhead while scaling to billions of transistors, as seen in modern designs for mobile SoCs and data centers incorporating gate-all-around (GAA) nanosheet transistors.^[12] This progression reflects ongoing adaptations to process variations and interconnect dominance at advanced nodes, with recent advancements including optimized power gating in neural processing units (NPUs) for AI workloads, achieving up to 33% energy savings as of 2024.^[13]^[14]

Fundamentals of Power Consumption

Static and Dynamic Power in ICs

In integrated circuits (ICs), particularly those fabricated using complementary metal-oxide-semiconductor (CMOS) technology, total power consumption is the sum of dynamic and static components, expressed as P_{total} = P_{dynamic} + P_{static}. This partitioning is fundamental to understanding energy efficiency challenges in modern electronics, where both active operation and idle states contribute to overall dissipation. Dynamic power arises from charging and discharging capacitances during logic transitions, while static power stems from unintended current flows even when the circuit is not switching. As ICs scale to smaller process nodes, the relative contributions of these components shift, impacting design strategies for low-power systems. Dynamic power dissipation in CMOS ICs is primarily due to the switching activity of transistors and is given by the formula P_{dynamic} = \alpha C V^2 f, where \alpha is the activity factor representing the probability of a node switching per clock cycle, C is the load capacitance, V is the supply voltage, and f is the operating frequency. This component dominates during active computation, as it scales quadratically with voltage and linearly with frequency and capacitance, making it sensitive to workload intensity and clock speed. For instance, in high-performance processors, dynamic power can account for the majority of consumption under full utilization, but optimizations like voltage scaling directly mitigate it. Static power, in contrast, is independent of clock frequency and activity, calculated as P_{static} = I_{leak} V, where I_{leak} encompasses leakage currents such as subthreshold, gate, and junction types, and V is the supply voltage. It persists during standby or low-activity periods, consuming energy continuously and generating heat that can exacerbate further leakage through temperature dependence. With CMOS scaling, static power has grown exponentially due to shorter channel lengths and thinner gate oxides, leading to increased subthreshold leakage. The breakdown of Dennard scaling around 2004-2006 marked a critical shift, as voltage reductions stalled to control leakage, causing static power to overtake dynamic power in standby modes and necessitate advanced power management techniques. In advanced process nodes like 7 nm, static power can constitute 30-50% of total consumption in active scenarios for certain designs.^[15]

Role of Leakage Current

Leakage current in CMOS integrated circuits arises primarily from the off-state behavior of MOSFETs, where even when the transistor is intended to be off (V_{GS} < V_{th}), a small current flows between the drain and source due to weak inversion of the channel. This off-state conduction is exacerbated by short-channel effects, such as threshold voltage (V_{th}) roll-off, where scaling the channel length below approximately 100 nm reduces V_{th} because the gate's electrostatic control weakens, allowing source and drain fields to influence the channel more significantly. As a result, the effective V_{th} decreases, increasing the subthreshold leakage and contributing to higher static power dissipation in scaled technologies. The dominant leakage mechanisms in modern CMOS devices include subthreshold leakage, gate oxide tunneling, junction band-to-band tunneling, and gate-induced drain leakage (GIDL). Subthreshold leakage, the most prevalent in standby modes, occurs via diffusion of minority carriers in the weak inversion region and is modeled by the equation:

I_{sub} = I_0 \exp\left( \frac{V_{GS} - V_{th}}{n V_T} \right) \left(1 - \exp\left(-\frac{V_{DS}}{V_T}\right)\right)

where I_0 is a process-dependent constant, V_{th} is the threshold voltage, n is the subthreshold swing parameter (≈1-2), V_T is the thermal voltage (kT/q ≈26 mV at room temperature), V_{GS} is the gate-source voltage, and V_{DS} is the drain-source voltage. The exponential term reflects the gate voltage dependence while the saturation factor accounts for short-channel behavior. Gate oxide tunneling involves quantum mechanical direct or Fowler-Nordheim tunneling through the thin gate dielectric (typically <2 nm in advanced nodes), becoming significant as oxide thickness scales.^[16] Junction band-to-band tunneling generates electron-hole pairs across the reverse-biased source/drain junctions via quantum effects, while GIDL arises from high transverse fields at the gate-drain overlap, lowering the potential barrier and enabling band-to-band tunneling near the drain. Leakage current exhibits strong temperature and voltage dependencies, amplifying its impact in operating conditions. Subthreshold leakage roughly doubles for every 10-15°C temperature rise due to the exponential increase in carrier mobility and the reduction in V_{th} (by about 1-2 mV/°C), which lowers the energy barrier for diffusion.^[17] Gate oxide and junction tunneling components show weaker temperature dependence but increase with voltage, as higher V_{DS} or V_{GD} enhances field strength and tunneling probability. Process variations, including random dopant fluctuations and line-edge roughness, can amplify leakage by 3-5× across dies, as they cause local V_{th} mismatches that disproportionately affect the exponential subthreshold term. In mobile system-on-chips (SoCs), unchecked leakage can consume 20-40% of standby power, severely limiting battery life in always-on devices like smartphones where idle periods dominate usage. Power gating mitigates this by collapsing the virtual ground supply to inactive blocks, reducing leakage to less than 1% of the original standby power through complete elimination of V_{DS}-driven components.

Core Techniques

Coarse-Grain Power Gating

Coarse-grain power gating applies power switches to large functional modules, such as entire CPU cores or memory banks, utilizing shared sleep transistors to disconnect the power supply from inactive blocks and thereby suppress leakage currents. This method partitions the chip into distinct power domains, where high-threshold-voltage (high-Vt) sleep transistors act as current switches to isolate unused regions from the main supply. By targeting broad areas rather than individual cells, it simplifies the design process while effectively addressing static power dissipation in modern scaled technologies.^[19]^[20] Implementation typically involves footer or header configurations of sleep transistors, often PMOS headers for superior leakage control, placed between the global power rails and local virtual VDD or GND rails dedicated to the block. These virtual rails distribute power within the domain, with transistor sizing optimized to limit voltage drops (e.g., to under 50 mV IR drop at operational frequencies like 250 MHz). During wake-up, a controlled sequence ramps the voltage gradually—using techniques like soft-start mechanisms limiting in-rush currents to around 80 mA over 100 ns—to prevent excessive transient currents and ensure reliable reactivation without stressing the circuit.^[19]^[20] The technique provides low area overhead, generally 1-5% due to shared switches and minimal additional routing, and supports straightforward partitioning at the register-transfer level (RTL) for module-level control. In idle blocks, it achieves substantial power savings, up to 90-99% reduction in leakage power, making it suitable for scenarios with infrequent activity. For instance, it is employed in ARM-based architectures like big.LITTLE for clustering and powering down inactive cores, enabling efficient heterogeneous processing while maintaining quick state retention for resumption.^[21]^[20]

Fine-Grain Power Gating

Fine-grain power gating involves inserting sleep transistors directly adjacent to individual standard cells or small clusters of logic gates within a design, enabling precise control over power supply to inactive portions of the circuit. This approach typically leverages multi-threshold CMOS (MTCMOS) libraries, where low-threshold voltage (low-Vt) transistors are used for high-performance logic paths, while high-threshold voltage (high-Vt) sleep transistors act as switches to isolate and cut off power to those paths during idle periods.^[22]^[23] In implementation, sleep transistors are placed to create local virtual power and ground rails for each cluster, allowing dynamic enabling or disabling based on real-time activity monitoring. Techniques such as MTCMOS facilitate this by stacking high-Vt transistors in series with the logic, minimizing leakage while maintaining performance in active modes; control signals from activity detectors or schedulers toggle these switches to power down unused gates without disrupting adjacent active logic.^[22]^[24] This method offers superior granularity for scenarios with partial circuit activity, enabling power savings in densely utilized designs by targeting only idle elements. It also reduces IR drop compared to broader gating strategies, as localized switches limit current paths and voltage gradients during transitions. Wake-up latencies are typically under 1 μs due to the small capacitance of individual clusters, contrasting with longer delays possible in unoptimized coarser approaches.^[25]^[20] However, fine-grain power gating incurs higher area overhead, often 10-20% due to the proliferation of sleep transistors and associated routing. The increased complexity in routing virtual rails and managing control signals can complicate physical design flows. An example application is in FPGA fabrics, where sleep transistors are integrated at the lookup table or interconnect level to power gate reconfigurable logic blocks, achieving up to 38% total power reduction in 100 nm technology while supporting dynamic reconfiguration.^[26]^[27]

Supporting Mechanisms

Isolation Cells

Isolation cells are essential components in power-gated designs, serving to electrically and logically isolate powered-off domains from active ones, thereby preventing the propagation of undefined or floating signals that could cause glitches, short-circuit currents, or logical errors in the always-on circuitry.^[28] These cells are strategically placed at the boundaries between power domains, particularly at the outputs of the power-gated blocks, to ensure that signals entering active domains remain in safe, predictable states during power-down transitions.^[29] By clamping outputs to known logic levels, isolation cells mitigate risks associated with unpowered logic, such as indeterminate voltages (often denoted as 'X' in simulations) that might otherwise propagate and disrupt circuit functionality.^[30] Common types of isolation cells include clamp cells, which utilize simple logic gates like AND or OR to tie outputs to a safe value—such as logic 0 via an AND gate with an enable signal or logic 1 via an OR gate—when the power domain is shut off.^[29] Buffer isolation cells function similarly but incorporate buffering to maintain signal integrity without altering the logic path during normal operation. Level shifters, while primarily for multi-voltage domains, are sometimes integrated as isolation cells in power gating to handle voltage level transitions at domain interfaces, ensuring compatibility between domains operating at different supply levels.^[31] These cells are typically implemented using standard-cell libraries and reside in the always-on power domain to avoid their own power dependency.^[28] In operation, isolation cells are controlled by a sleep or enable signal derived from the power gating controller; during sleep mode, the signal activates the clamping mechanism, holding outputs at stable states (e.g., 0 or 1) to prevent floating inputs in downstream logic.^[29] Upon wake-up, the control signal deactivates the clamp, allowing the cell to operate as a transparent buffer or pass-through element, restoring normal signal flow with negligible additional delay—often equivalent to a single gate stage in the critical path.^[30] This design ensures minimal impact on overall circuit performance while effectively isolating the domains.^[32] The insertion of isolation cells is typically automated during the synthesis and place-and-route phases of the design flow, guided by power intent specifications in formats like Unified Power Format (UPF). Tools such as Synopsys IC Compiler analyze domain boundaries and automatically place isolation cells, optimizing their proximity to power switches to reduce routing overhead and potential metastability issues at interfaces.^[33] This automation ensures comprehensive coverage, with verification flows targeting these cells to confirm correct hookup and functionality, thereby enhancing design reliability in multi-domain SoCs.^[28]

Retention Registers

Retention registers are specialized sequential elements employed in power-gated integrated circuits to preserve the internal state of critical flip-flops during power-off phases, preventing data loss and facilitating swift restoration of operations upon reactivation.^[34] These mechanisms ensure that only essential state information is retained with low power overhead, allowing the main logic to be fully powered down while avoiding the need to reload data from external storage, which would otherwise introduce significant latency.^[35] By isolating storage nodes or using dedicated low-leakage structures, retention registers minimize leakage current in idle modes, making them indispensable for applications requiring frequent power state transitions, such as processor register files.^[36] Common types of retention registers include those utilizing separate retention power rails, where a dedicated always-on supply maintains state; scan-based retention approaches that leverage scan chains for state capture and restore; and flip-flop designs featuring isolated storage nodes, such as master-slave configurations with the slave latch powered independently.^[37] In dual-rail designs, the master latch operates on the switchable primary supply (VDD), while the slave latch connects to an always-on secondary supply (VCC), ensuring data integrity even as the main power domain collapses.^[34] Scan-based variants integrate retention functionality into existing design-for-test structures, reducing the need for custom cells but potentially complicating test flows.^[35] During operation, when entering sleep mode, the primary power supply to the logic block is gated off, causing the main flip-flop circuitry to lose state, while the retention elements—often operating at reduced voltages around 0.5 V—hold the bit values in a stable, low-leakage configuration.^[38] Upon wake-up, power is restored to the main domain, and the retained state is transparently propagated back to the active flip-flops, typically within nanoseconds, enabling near-instantaneous resumption of computation without software intervention.^[36] This process relies on careful sequencing to avoid glitches, often coordinated with isolation cells to manage signals crossing power domains.^[37] The primary trade-offs of retention registers involve increased area overhead, typically adding 5-10% to the overall design footprint due to additional transistors and dual power routing, though advanced multibit sharing techniques can mitigate this to near-zero incremental cost per flop.^[36] They also introduce minor active-mode power penalties from extra leakage paths and potential timing delays in clock-to-output paths owing to high-threshold voltage devices used for retention stability.^[34] Despite these costs, the benefits in enabling fast context switching and reducing overall system power in processors outweigh the drawbacks, particularly in scenarios with high idle times.^[35]

Design Parameters

Switch Sizing and Efficiency

The sizing of sleep transistors in power gating circuits is critical to balance performance, power efficiency, and area overhead, primarily determined by the required current handling capacity and allowable voltage drop across the switch. The width W of a sleep transistor is approximately calculated using the MOSFET linear region current equation to ensure the IR drop remains below 5% of the supply voltage:

W \approx \frac{I_{\text{load}} L}{\mu C_{\text{ox}} (V_{\text{gs}} - V_{\text{th}}) \Delta V},

where I_{\text{load}} is the maximum load current, L is the channel length, \mu is the carrier mobility, C_{\text{ox}} is the oxide capacitance per unit area, V_{\text{gs}} is the gate-source voltage, V_{\text{th}} is the threshold voltage, and \Delta V is the allowable voltage drop.^[39] This formula provides an initial estimate assuming small \Delta V, and is refined through simulations to account for process variations. For high-current applications, such as large logic blocks, sleep transistors are often arranged in parallel stacks to distribute the load and reduce on-resistance without excessive area penalty.^[40] Efficiency in power gating switches is quantified by their impact on leakage in sleep mode and voltage overhead in active mode. In sleep mode, power gating achieves a leakage reduction factor of 10-100x compared to non-gated circuits by isolating the logic from the supply, minimizing subthreshold and gate leakage currents.^[41] In active mode, the voltage drop is given by V_{\text{drop}} = I \cdot R_{\text{on}}, where the on-resistance R_{\text{on}} is inversely proportional to the transistor width (R_{\text{on}} \sim 1/W), typically limiting performance degradation to under 10% for properly sized switches.^[40] Optimization of switch sizing involves adaptive techniques tailored to circuit demands, often employing SPICE simulations to iterate on width and stack configurations for minimal IR drop and noise. For large circuit blocks, multi-stage switch architectures are used to limit wake-up current spikes exceeding 1 A, which can otherwise cause ground bounce and supply instability during mode transitions.^[42] Transistor-level tuning is commonly performed using tools like Cadence Virtuoso, enabling precise modeling of device parameters in advanced nodes.^[43]

Overhead and Trade-offs

Power gating implementations introduce notable area overheads primarily due to the addition of sleep transistors and associated isolation cells, typically ranging from 5% to 15% of the total circuit area, with the overhead scaling inversely with the granularity of the gating—coarser designs exhibit lower relative costs.^[1] Fine-grained approaches, while offering precise control, can exacerbate this overhead by requiring more distributed switches, potentially reaching the upper end of this range in complex SoCs. Performance impacts arise during mode transitions, including wake-up latencies of 10 μs to 1 ms, which depend on the size of the power domain and the charging time through sleep transistors, delaying resumption of operations in time-sensitive applications.^[45] Ground bounce noise, caused by rapid discharge currents during wake-up, can induce voltage fluctuations up to hundreds of millivolts, potentially leading to functional failures or timing violations if not mitigated through stepwise activation techniques.^[46] Key trade-offs in power gating involve balancing energy savings against delay penalties; for instance, deeper sleep states yield higher leakage reduction (up to 99% in some cases) but increase transition energy costs and latency, making the technique most suitable for bursty workloads where idle periods exceed the break-even time—typically several microseconds to milliseconds. In energy-constrained designs, this often results in a 10-20% performance degradation for a given power budget, particularly in fine-grained implementations. Verification poses significant challenges in multi-domain designs, where asynchronous power-up sequences across domains can lead to race conditions and signal integrity issues, requiring extensive simulation and formal methods to ensure robust isolation and recovery.^[47] To mitigate these overheads, hybrid approaches combining power gating with dynamic voltage and frequency scaling (DVFS) allow finer energy-delay trade-offs by scaling voltage during active periods while gating idle blocks, reducing overall wake-up penalties and improving suitability for variable workloads without excessive area costs.^[48]

Applications and Advances

Integration in Modern SoCs

In contemporary system-on-chips (SoCs), power gating is extensively deployed to address escalating leakage currents in advanced process nodes, particularly in mobile platforms where battery life is paramount. For example, Qualcomm's Snapdragon series processors incorporate power gating mechanisms, enabling selective shutdown of idle components to minimize static power dissipation.^[49] This approach extends to modern iterations fabricated on 5 nm and 3 nm nodes in the 2020s, allowing individual CPU cores to enter low-power states during varying workloads using techniques like clock gating, thereby optimizing energy efficiency in heterogeneous architectures.^[50] Similarly, Apple's A-series processors, powering iOS devices, employ hierarchical power gating across CPU and GPU clusters, where larger domains can be isolated at the cluster level while finer controls manage intra-cluster inactivity, supporting seamless transitions between performance peaks and idle modes. Emerging trends in SoC design further integrate power gating with advanced packaging technologies, such as 3D ICs, where per-layer gating isolates stacked dies to curb inter-layer leakage and thermal hotspots. In these structures, power distribution networks are optimized to support granular shutdowns, reducing overall system power by targeting inactive vertical tiers without disrupting active computation layers.^[51] In AI accelerators, fine-grained power gating is leveraged to exploit sparsity patterns; for instance, Google's Tensor Processing Units (TPUs) inspire designs like ReGate, which dynamically gates hardware components during sparse neural network operations, deactivating unused multiply-accumulate units to align power delivery with dataflow sparsity. Recent advances, such as ReGate introduced in 2025, enable up to 32.8% energy reduction in neural processing units through hardware-software co-design.^[15] The practical benefits of such integrations are evident in mobile SoCs, where power gating contributes to significant reductions in total power consumption under mixed workloads, primarily by slashing leakage in standby scenarios. This enables extended battery life in low-activity connected standby modes for smartphones and wearables. Looking ahead, as SoCs scale to sub-3 nm nodes with FinFET-to-gate-all-around (GAA) transitions, advanced power gating becomes essential to mitigate quantum tunneling leakage, which exacerbates subthreshold currents in ultra-thin channels; simulations indicate that GAA structures with integrated gating can maintain sub-10 μA/μm off-state currents despite these challenges.^[52]^[53]

Comparison with Other Power Management Techniques

Power gating primarily targets static leakage power by completely disconnecting the power supply to inactive circuit blocks, effectively turning them off, whereas clock gating focuses on reducing dynamic power consumption by halting clock signals to prevent unnecessary toggling in idle modules.^[54] This distinction makes clock gating suitable for short-term inactivity where switching activity is low but leakage persists, while power gating achieves near-zero leakage but incurs additional wake-up latency due to the time required to restore power and stabilize the circuit.^[55] The two techniques are frequently combined in digital designs to address both power components comprehensively, as their integration can yield synergistic reductions in total energy without excessive overhead.^[54] In contrast to dynamic voltage and frequency scaling (DVFS), which dynamically adjusts supply voltage and operating frequency to lower both dynamic and static power during active workloads, power gating is optimized for standby or idle states where circuits are not computing.^[56] DVFS provides fine-grained control for performance-critical tasks but offers limited benefits during prolonged inactivity, whereas power gating excels in deep sleep modes by eliminating leakage entirely.^[57] Hybrid approaches incorporating both in system-on-chips (SoCs) can achieve up to twice the energy savings in standby compared to DVFS alone, particularly for workloads with variable activity patterns.^[57] Body biasing, or adaptive threshold voltage tuning through substrate bias, mitigates leakage by elevating the transistor threshold during low-activity phases without fully isolating the circuit, making it less disruptive for near-active operation but less effective for complete power cutoff.^[58] Power gating, by contrast, provides a more aggressive solution for deep sleep by severing the power connection, resulting in substantially higher leakage reduction—often orders of magnitude greater—though at the cost of state restoration overhead.^[59] This positions body biasing as a complementary technique for active or light-sleep modes, while power gating is preferred for scenarios demanding maximal standby efficiency. The choice among these techniques depends on workload analysis, including activity profiles and idle durations; power gating is most advantageous for extended idle periods exceeding approximately 10 μs, where the energy overhead of activation is amortized by leakage savings, unlike clock gating or DVFS which suit shorter or active intervals.^[60]

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[PDF] Power Optimization in Design Compiler Datasheet - Synopsys
Power Compiler takes UPF input and automatically inserts power management cells such as isolation, level-shifter, retention register, power gating and always-on ...
[35]
Power Gating Retention - Semiconductor Engineering
State retention registers require two types of power supplies: a switchable power supply and an always-on power supply. This introduces some complications ...
[36]
Scalable sequence-constrained retention register minimization in ...
Retention registers are utilized in power gating design to hold design state during power down and to allow safe and fast system reactivation.
[37]
[PDF] High Performance State Retention with Power Gating applied to ...
ABSTRACT. Power management is of increasing concern and challenge to SOC and product designers [1], [2]. Power Gating (PG) is now well.
[38]
Retention cells - VLSI Tutorials
Retention cells are sequential cells that can hold their internal state when the primary power supply is shut down and has the ability to restore the state ...
[39]
[PDF] Reliable State Retention-Based Embedded Processors ... - CORE
It can be observed that the idle power is lowest for an unprotected system with retention voltage Vret = 0.5V when compared with hardware error correction and ...
[40]
[PDF] Sleep Transistor Sizing Using Timing Criticality and Temporal Currents
Abstract— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the ...Missing: principles | Show results with:principles
[41]
[PDF] Sleep Transistor Sizing and Control for Resonant Supply Noise ...
Aug 29, 2007 · Power gating is realized by sleep transistors which disconnect the power supply from the circuit when the chip is in idle mode [1]. The optimal.Missing: principles seminal
[42]
[PDF] Ultra-Low Power Design Approaches for IoT - Hot Chips
♢ power gating is much less effective (I on. /I off degradation). ♢ typical leakage reduction: 10-100X. ♢ NT: small leakage reduction, ST: no leakage reduction ...
[43]
[PDF] A Three-Step Power-Gating Turn-on Technique for Controlling ...
Aug 20, 2010 · To suppress the ground bounce noise with a minimal wake-up time penalty, a three-step turn-on strategy and its corresponding power-gating ...
[44]
[PDF] Power Gating Design for Standard-Cell-Like-Structured ASICs
In this paper, we apply power gating to structured. ASICs for leakage power reduction. We present a power-gated via-configurable logic block (PGVCLB) and a ...Missing: mobile | Show results with:mobile
[45]
A Survey on Power Gating Techniques in Low Power VLSI Design | Semantic Scholar
### Summary of Power Gating Techniques in Low Power VLSI Design
[46]
https://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2003/islped03/pdffiles/01_5.pdf
[47]
[PDF] Ultra-low power design for iot sensors: energy harvesting and power ...
Power gating implementation reduced sleep mode power ... wake-up latency ranging from 10 μs to 1 ms depending on the complexity of power-gated domains.
[48]
[PDF] Understanding and Minimizing Ground Bounce During Mode ...
This paper investigates the ground bounce caused by large discharge current through a sleep transistor during the mode transition of the power gating structure.
[49]
[PDF] Comparative Study on Power Gating Techniques for Lower Power ...
Aug 13, 2018 · The power gating is one of the most popular reduction leakage techniques. We make comparison among various power gating schemes in terms of ...
[50]
[PDF] When Clock, Power and Reset Domains Collide - DVCon Proceedings
Multi-domain verification is the only way to ensure that all inter-domain issues are explored and verified with complete confidence. I. INTRODUCTION. Many new ...
[51]
[PDF] DarkGates: A Hybrid Power-Gating Architecture to Mitigate the ... - Ethz
To keep the power consumption of the compute domain within its allocated power budget, the PMU applies DVFS to. 1) reduce the CPU cores' power consumption and 2 ...
[52]
[PDF] Qualcomm® Snapdragon™ 600 Processor APQ8064 Data Sheet
Feb 10, 2016 · Low power features: ❒. Power gating within LPASS core. ❒. QDSP6 supports L2 cache data retention during power collapse. ❒. Supported modes ...
[53]
Qualcomm Oryon CPU | New custom Snapdragon CPU design
The 2nd generation Qualcomm Oryon CPU brought improved speeds and efficiency with a new data prefetcher and clock gating techniques on a 3nm process node.
[54]
GateBleed: Exploiting On-Core Accelerator Power Gating for High ...
Oct 17, 2025 · While power-gating does reduce power consumption, power-gating also incurs an extra measurable latency when waking up a powered-off component, ...Missing: series | Show results with:series
[55]
Power distribution network for a three-plane 3D IC with power gating,...
For 3D systems, power gating is critical due to higher and heterogeneous integration where the amount of nonswitching circuits can be significantly high. Thus, ...Missing: per- | Show results with:per-
[56]
Performance Limit of Gate-All-Around S i Nanowire Field-Effect ...
Nov 30, 2022 · In this paper, the performance limit of the GAA S i NWFET with a 1-nm diameter is investigated by utilizing ab initio quantum transport simulations.<|control11|><|separator|>
[57]
NS-GAAFET Compact Modeling: Technological Challenges in Sub ...
In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance.
[58]
Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously
**Summary of Key Points on Clock Gating and Power Gating:**
[59]
https://ieeexplore.ieee.org/document/4751925
[60]
Comparison between power gating and DVFS from the viewpoint of energy efficiency
**Summary of Abstract on Power Gating vs. DVFS Energy Efficiency:**
[61]
https://ieeexplore.ieee.org/document/5224259
[62]
https://ieeexplore.ieee.org/document/5510265
[63]
https://ieeexplore.ieee.org/document/4751925
[64]
https://ieeexplore.ieee.org/document/5993643