Transmission gate
A transmission gate, also known as a pass gate or analog switch in complementary metal-oxide-semiconductor (CMOS) technology, is a bidirectional electronic switch composed of an n-channel MOSFET (NMOS) and a p-channel MOSFET (PMOS) connected in parallel, with complementary control signals applied to their gates to enable or disable signal transmission between input and output nodes while providing full voltage swing from ground to supply voltage.[1][2][3] The structure of a transmission gate leverages the complementary strengths of NMOS and PMOS transistors: the NMOS efficiently passes low voltages (logic 0), while the PMOS handles high voltages (logic 1) without degradation due to threshold voltage drops, unlike single-transistor pass gates.[2][3] Operation occurs when the control signal is high (enabling the gate): the NMOS gate receives a logic 1, turning it on, and the PMOS gate receives the inverted signal (logic 0), also turning it on, creating a low-resistance path for the signal.[1] Conversely, when the control is low, both transistors are off, isolating the nodes with high impedance.[1] This configuration requires only two transistors, making it compact, and its equivalent resistance varies with output voltage, typically modeled as region-dependent for timing analysis.[1][2] Transmission gates offer significant advantages over pass transistors by restoring full signal levels, improving noise margins, and enabling efficient bidirectional flow without restoration circuitry, which reduces area and power consumption in integrated circuits.[3][2] They are widely applied in CMOS VLSI designs for functions such as multiplexing, where a 2:1 multiplexer can be implemented with just four transistors using two transmission gates controlled by a select signal; in latches and flip-flops for clocked storage; as tristate buffers for bus switching; and in arithmetic circuits like adders for optimized carry propagation, achieving up to 20% delay reduction in tapered chains.[4][5] These uses highlight their role in enhancing performance, area efficiency, and power in modern digital systems.[5][4]Physical Structure
Transistor Configuration
A transmission gate in CMOS technology comprises an n-channel metal-oxide-semiconductor field-effect transistor (NMOS) and a p-channel metal-oxide-semiconductor field-effect transistor (PMOS) connected in parallel between two nodes, which function bidirectionally as input and output terminals.[6] The drain and source terminals of both transistors are interconnected and shared, facilitating symmetric conduction in either direction without predefined polarity.[7] In standard CMOS fabrication, the NMOS body connects to ground and the PMOS body to the positive supply voltage, which helps manage body effect by maintaining fixed substrate potentials relative to the power rails.[8] This parallel configuration leverages the complementary strengths of the transistors: the NMOS provides low resistance for transmitting ground-referenced low-voltage signals (strong logic 0), while the PMOS offers low resistance for supply-referenced high-voltage signals (strong logic 1).[9] Together, they achieve full rail-to-rail analog or digital signal transmission with minimal voltage degradation, unlike single-transistor pass gates that suffer threshold voltage drops.[10] The transmission gate emerged in the context of CMOS logic development during the 1960s and 1970s, building on the complementary MOS circuit configuration patented in 1963 and integrated into early dynamic logic designs for low-power switching.[11] The NMOS and PMOS gates receive complementary control signals to enable or disable conduction simultaneously.[6]Control Mechanism
The control mechanism of a transmission gate relies on complementary input signals applied to the gates of its NMOS and PMOS transistors to enable precise switching. The NMOS transistor's gate is driven by a clock signal (CLK), which activates the NMOS when CLK is high (logic 1, at VDD), allowing strong conduction for low-voltage signals. Concurrently, the PMOS transistor's gate is driven by the inverted clock signal (CLK̅), which activates the PMOS when CLK̅ is low (logic 0, at VSS or ground), ensuring strong conduction for high-voltage signals. This complementary clocking ensures both transistors turn on and off simultaneously, creating a bidirectional low-resistance path for analog or digital signals.[12] To generate the inverted signal CLK̅, a CMOS inverter is typically employed, taking CLK as input and producing the complement with minimal delay and full rail-to-rail swing. This setup guarantees synchronized activation of the parallel NMOS and PMOS transistors, preventing any timing skew that could degrade performance. The inverter's output drives the PMOS gate directly, forming an integrated control structure common in CMOS designs.[12] Control signals must operate at full supply voltage levels (VDD for high and VSS for low) to minimize threshold voltage drops and achieve optimal transmission. Partial voltage swings, such as those below VDD - |Vth| for PMOS or above Vth for NMOS, lead to degraded on-resistance and signal attenuation, compromising the gate's ability to pass full-range signals without distortion.[12] In the on-state, the effective resistance R_{on} of the transmission gate is the parallel combination of the individual transistor resistances, given byR_{on} = \frac{R_{NMOS} R_{PMOS}}{R_{NMOS} + R_{PMOS}},
where the NMOS resistance is
R_{NMOS} = \frac{1}{\mu_n C_{ox} \left( \frac{W}{L} \right)_n (V_{GS} - V_{th_n})},
and the PMOS resistance follows analogously as
R_{PMOS} = \frac{1}{\mu_p C_{ox} \left( \frac{W}{L} \right)_p (V_{SG} - |V_{th_p}|)},
assuming linear-region operation with full gate-source voltages (VGS = VDD for NMOS and VSG = VDD for PMOS). These expressions highlight the dependence on process parameters like carrier mobility (\mu), oxide capacitance (C_{ox}), and transistor aspect ratios (W/L), which are sized to balance R_{NMOS} and R_{PMOS} for minimal R_{on} (typically 1-10 k\Omega).[13]