Reset vector
In computer architecture, a reset vector is a predefined memory address that specifies the starting location for program execution immediately following a processor reset, such as upon power-on or a hardware reset signal, typically containing the initial boot code or handler routine that initializes the system.[1] This vector ensures reliable and deterministic startup by directing the processor to a fixed entry point in non-volatile memory, often as part of an exception or interrupt vector table.[2] The purpose of the reset vector is to provide a secure and efficient boot mechanism, where the processor fetches the address from a dedicated memory location and branches to it, loading essential configurations like stack pointers and enabling subsequent software initialization.[3] In many architectures, it is the first entry in the vector table, distinguishing it from other vectors for interrupts or exceptions by its role in cold starts without prior context.[4] Common implementations vary by processor family; for instance, in ARM-based systems, the reset vector is located at offset 0x04 in the vector table (defaulting to address 0x00000004), read after setting the main stack pointer, and can be relocated via the Vector Table Offset Register (VTOR).[4] In Intel's Nios II processors, it is a configurable physical address offset from a selected memory module's base, always pointing to reset exception code in read-only memory.[3] Similarly, RISC-V architectures support dual reset vectors at low (e.g., 0x00000000) and high addresses for flexibility in embedded systems.[5] Historically and in practice, reset vectors are hardcoded or minimally configurable to prevent boot failures, with addresses like 0x00000000 for low-endian starts or 0xFFFE/0xFFFF for high-memory placements in 8- or 16-bit microcontrollers, ensuring compatibility across power cycles and fault recoveries.[1] Their design influences system reliability, as misalignment or corruption can lead to undefined behavior, underscoring their critical role in firmware and operating system bootstrapping.[2]Fundamentals
Definition
In computer architecture, the reset vector is a fixed memory address to which the central processing unit (CPU) transfers control upon receiving a reset signal, such as power-on or a hardware reset, to execute the first instruction of the initialization sequence. This address points to the starting location of boot code, often stored in nonvolatile memory like ROM, ensuring the processor begins operation in a defined state.[6][3] The concept of the reset vector originated in early microprocessors of the 1970s, exemplified by the Intel 8080, where activation of the RESET input pin clears the program counter to 0000H and initiates execution from that memory location, without altering other registers like the accumulator or flags.[7] In modern designs, such as ARM architectures, the reset vector is typically located at a configurable low address (0x00000000) or high address (0xFFFF0000), determined by a control register bit, and resides within an exception vector table.[8] Key components of a reset vector include a dedicated physical address—often 16-bit or 32-bit in width—that is either hardcoded into the processor's logic or derived from a base register offset, always bypassing memory management units for direct access.[3][9] Unlike interrupt vectors, which form a configurable table of addresses for handling asynchronous events and can be masked or relocated during runtime, the reset vector remains static and non-maskable, as the processor enters a privileged mode with interrupts disabled upon reset to guarantee unimpeded system startup.[6][8]Purpose
The reset vector plays a pivotal role in processor initialization by providing a fixed, reliable address that the program counter loads immediately after a reset, ensuring execution begins at a predetermined location containing bootstrap code. This mechanism directs the processor to perform essential startup tasks, including hardware configuration, memory clearing, and the setup of critical registers such as the stack pointer and program counter, thereby establishing a deterministic and controlled boot sequence.[8][10] In terms of system reliability, the reset vector is crucial for avoiding undefined states that could result from residual power conditions or prior execution artifacts, particularly in embedded and real-time systems where fault tolerance is essential. By halting ongoing instructions and transitioning to a supervisor or privileged mode with interrupts disabled, it guarantees a clean operational baseline, enabling robust recovery from power fluctuations or errors. This is especially vital during power-on reset (POR), where the vector activates to initialize special function registers to known values while general-purpose RAM enters an indeterminate state that must be explicitly managed.[8][11][10] Misconfiguration of the reset vector, such as pointing to an invalid or unprogrammed address, can result in severe operational failures, including system hangs due to execution of garbage code, incomplete hardware initialization leading to peripheral malfunctions, or unintended low-power modes that prevent normal startup. If the vector directs to corrupted memory locations, it may exacerbate these issues by executing unreliable instructions from the outset, undermining overall system stability and potentially exposing vulnerabilities in fault-prone environments.[11][10]Implementation
Mechanism
Upon assertion of the reset signal, typically triggered by an external reset pin, power-on event, or internal logic such as a watchdog timer, the processor immediately halts any ongoing instruction execution to ensure a clean state transition.[12][8] This hardware-initiated process initializes critical components, including clearing or setting the program counter (PC) to a predefined value and resetting registers to their default states, preventing undefined behavior from prior operations.[12] Once the reset signal de-asserts, the processor loads the address stored in the reset vector—often the first entry in a vector table at an offset such as 0x0000—directly into the PC.[12] This address points to the initial instruction in system memory, usually ROM, which is then fetched and executed sequentially to begin the boot process.[8] The vector table serves as a structured array of pointers for various exceptions, with the reset entry ensuring reliable startup.[12] The reset mechanism has the highest priority, inherently disabling all maskable interrupts and asynchronous exceptions to avoid interference during startup.[8] This non-maskable nature ensures the processor cannot ignore or defer the reset, even if interrupts were enabled prior to assertion, allowing exclusive focus on initialization routines.[12] If the reset vector address is invalid or points to inaccessible memory, the processor may trap to a default error handler or enter an infinite loop to prevent erratic execution and signal a hardware or configuration issue.[12] Post-reset register values not explicitly defined are considered unknown, underscoring the need for robust hardware design to guarantee a valid vector.[8]Configuration
In processor designs, reset vectors are typically set during manufacturing or provisioning using immutable storage mechanisms to ensure reliable initialization. One common method involves hardwiring the vector in read-only memory (ROM), where the initial boot code, including the reset handler, is embedded directly into on-chip boot ROM that executes immediately upon power-on or reset. Alternatively, one-time programmable (OTP) memory or e-fuses allow configuration of the reset address or boot parameters by blowing fuses during production, permanently selecting boot modes or device configurations without altering the core vector location.[13] For greater flexibility, the vector can be loaded from external non-volatile sources like flash memory during the boot process, where the boot ROM reads configuration registers and transfers control to a designated flash address containing the vector table.[14] Protection of the reset vector is critical to prevent unauthorized modifications that could compromise system integrity. Write-protection is often enforced through hardware mechanisms, such as locking flash sectors containing the vector to disable erase or overwrite operations post-provisioning, emulating ROM-like immutability. Hardware locks, including debug interface disables (e.g., JTAG/SWD), further safeguard the vector by restricting access in secure states, while secure boot features verify the vector's authenticity using cryptographic keys stored in OTP or locked flash before execution.[14] These protections establish a root of trust, ensuring the vector remains unaltered during runtime or by external attacks. Developers configure the reset vector's placement in firmware using development tools that map code to specific memory addresses. Assemblers generate object files with vector code, while linkers combine these into executables by specifying sections in linker scripts; for instance, a script may define a.reset or .vectors section aligned to the processor's reset address (e.g., 0x00000000), ensuring the handler is positioned correctly for loading into the program counter. This process allows precise control over the vector's location during build-time, facilitating integration with bootloaders or operating systems.
Configurability of reset vectors varies by processor complexity to balance security and adaptability. In simple microcontrollers (MCUs), vectors are often fixed at a hardcoded address in ROM or flash for minimal overhead and high reliability in resource-constrained environments.[14] In contrast, advanced system-on-chips (SoCs), particularly multi-core designs, support relocatable vectors configurable via registers like ARM's RVBAR_EL3, allowing dynamic adjustment for virtualization, secure partitioning, or core-specific bootstraps while maintaining protection through programmable locks.[15] This relocatability enhances flexibility in heterogeneous systems without sacrificing immutability of the initial entry point.