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Flash memory

Flash memory is a type of non-volatile semiconductor memory that retains stored data even without power and can be electrically erased and reprogrammed in blocks rather than byte by byte, distinguishing it from earlier EEPROM technologies.^[1] It employs floating-gate transistors, where electrical charges trapped in a floating gate within the transistor's insulation layer determine the stored bit value (typically 0 or 1, though multi-level cells store more).^[2] This architecture enables high-density storage, fast block-level erasure (hence the "flash" name, inspired by its rapid clearing like a camera flash), and relatively low cost per bit, making it ideal for applications requiring durable, rewritable data retention.^[1] The technology was invented by Fujio Masuoka and his team at Toshiba in the early 1980s as part of a secret project to create a more efficient non-volatile memory.^[1] Masuoka first demonstrated a NOR-type flash memory prototype at the 1984 IEEE International Electron Devices Meeting. Intel commercialized NOR flash in 1988, while Toshiba introduced NAND flash in 1989, which offered even higher density due to its serial cell arrangement, sparking rapid market growth fueled by shrinking transistor sizes and applications in digital cameras, mobile devices, and solid-state drives (SSDs).^[1] By the 2010s, advancements like 3D NAND stacking allowed terabyte-scale capacities while addressing planar scaling limits. As of 2025, further innovations like 300+ layer 3D NAND have pushed capacities to petabyte levels in enterprise storage.^[3]^[4] Flash memory exists in two main architectures: NOR flash, which connects cells in parallel for fast random access and direct code execution (execute-in-place, or XIP), suiting it for boot code and embedded systems with densities up to several gigabits (as of 2025); and NAND flash, which arranges cells in series for higher density (up to 2 Tb+), lower cost per gigabyte, and faster sequential writes, but requires controllers for error correction, wear leveling, and bad block management due to its block-oriented operations.^[5] NOR offers higher endurance (up to 100,000 program/erase cycles) and is used in automotive systems, wearables, and industrial PCs, while NAND dominates mass storage in SSDs, smartphones, USB drives, and data centers, with variants like SLC (single-level cell) for reliability, MLC/TLC/QLC for density.^[5] Despite limitations like finite endurance and electron leakage over time, flash memory's versatility has made it ubiquitous in consumer electronics, enterprise storage, and even space missions.^[1]

History

Early concepts and invention

The development of flash memory was motivated by the limitations of earlier non-volatile memories like electrically erasable programmable read-only memory (EEPROM), which allowed byte-by-byte erasure but suffered from slow erasure times, limited endurance cycles (typically around 10,000 to 1 million per cell), and higher manufacturing costs due to requiring two transistors per bit, making it impractical for large-capacity storage applications.^[6] Researchers sought a solution that could erase data in larger blocks simultaneously, enabling faster operations, denser cell structures with a single transistor per bit, and cost-effective scaling for high-density non-volatile memory.^[7] Fujio Masuoka, a researcher at Toshiba Corporation in Japan, played a pivotal role in inventing flash memory during the 1980s. In 1984, Masuoka and his team developed the first NOR-type flash memory cell, utilizing a floating-gate structure with triple polysilicon technology that allowed electrical erasure of the entire memory array in a single "flash" operation, named for its rapid erasure akin to a camera flash.^[7] This prototype was presented at the IEEE International Electron Devices Meeting (IEDM) in December 1984, where Masuoka detailed a 64-kbit device demonstrating non-volatility, in-system rewritability, and compatibility with existing EPROM fabrication processes.^[8] Masuoka filed the original patents for this NOR flash technology, establishing the foundational intellectual property for block-erasable non-volatile memory.^[8] Building on the NOR design, Masuoka introduced NAND flash memory in 1987 to achieve even higher densities. The NAND structure arranged cells in series, reducing cell area by approximately 30% compared to NOR while enabling ultra-high-density storage suitable for applications beyond 1 Mbit.^[9] This innovation was prototyped as a 1-Mbit device and presented at the 1987 IEEE IEDM, highlighting its potential for scalable, low-cost mass storage through serial access and contactless cell arrays.^[9] Masuoka also secured patents for the NAND architecture, further advancing the field.^[8] Early prototypes of both NOR and NAND flash faced significant technical challenges, including the need for high voltages—around 20 V for programming and erasing via Fowler-Nordheim tunneling—which complicated integration with low-voltage logic circuits and increased power consumption.^[10] Additionally, despite the groundbreaking potential, there was initial lack of industry interest; Toshiba provided Masuoka only a modest bonus of a few hundred dollars for his inventions and even attempted to demote him, leading to his resignation in 1994 amid disputes over recognition and royalties.^[11]^[12] These hurdles delayed widespread adoption until subsequent refinements addressed reliability and compatibility issues.

Commercialization and adoption

The commercialization of flash memory began in the late 1980s, marking a pivotal shift toward electrically erasable non-volatile storage suitable for portable electronics. In 1988, Intel introduced the first commercial NOR flash memory chip, a 256-kilobit device that enabled random access and code execution directly from the memory, positioning it as a successor to ultraviolet-erasable EPROMs. This was followed by Toshiba's 1989 release of the first commercial NAND flash chips, starting with a 1-megabit capacity and scaling to 4-megabit by year's end, which emphasized high-density block-based storage for cost-sensitive applications.^[1] These initial products were priced at around $20 per 256-kilobit chip, equivalent to roughly $640 per megabyte, reflecting early manufacturing challenges but offering a compelling value over traditional EPROMs due to electrical erasability without specialized equipment.^[13] Early adoption in the 1990s focused on consumer and industrial devices where size, power efficiency, and reprogrammability were critical. Flash memory quickly found use in digital cameras, such as the 1995 Casio QV-10, which replaced film with removable flash cards for image storage, and in laptops for BIOS firmware updates, reducing reliance on slower EEPROMs.^[14] By the mid-1990s, capacities reached 1-megabit routinely, with pricing dropping to under $10 per chip, enabling broader integration into PDAs and embedded systems.^[15] The technology's advantages—faster block erase times (milliseconds versus seconds for byte-level EEPROM operations) and lower cost per bit (due to denser cell structures)—drove its replacement of EPROMs in prototyping and EEPROMs in high-volume storage, with flash achieving up to 10 times the density at half the price by 1995.^[16] Key partnerships accelerated standardization and market penetration. In 1988, former Intel engineers founded SanDisk, which collaborated with Toshiba to develop flash-based storage solutions, leading to the 1997 formation of the MultiMediaCard (MMC) standard by SanDisk, Siemens, and later Nokia.^[17] The MMC, a compact NAND-based card with initial 2-megabyte capacities, targeted mobile phones and early digital audio players, standardizing interfaces for interchangeable storage and boosting adoption in portable devices.^[18] By the late 1990s, these efforts had propelled flash memory into mainstream use, with annual revenues surpassing $1 billion and enabling the portable computing revolution.^[19]

Technological evolution

Following the commercialization of flash memory in the late 1990s, a key advancement in the early 2000s was the introduction of charge-trap flash (CTF), which replaced the traditional floating-gate structure with discrete charge-trapping sites in a dielectric layer, such as silicon nitride, to improve reliability by reducing charge leakage and enhancing data retention.^[20]^[21] This shift, first implemented by AMD and Fujitsu in 2002, addressed scaling limitations of floating-gate technology below 45 nm, enabling higher densities while maintaining endurance and minimizing defects' impact on performance.^[20]^[22] To increase storage density without proportionally expanding die size, multi-level cell (MLC) architectures emerged in the 2000s, storing 2 bits per cell by distinguishing four voltage states, which doubled capacity compared to single-level cells (SLC) and gained widespread adoption in consumer devices like SSDs and memory cards.^[23] Building on this, triple-level cell (TLC) technology, storing 3 bits per cell with eight voltage levels, was commercialized in the 2010s, starting with Samsung's mass production in 2010, further boosting density for mainstream applications despite trade-offs in write endurance.^[24] Quad-level cell (QLC), with 4 bits per cell and 16 states, followed in 2018 through joint efforts by Intel and Micron, enabling terabit-scale chips suitable for archival and read-intensive workloads.^[25] Most recently, penta-level cell (PLC) technology, storing 5 bits per cell, was unveiled by SK Hynix in 2024, pushing density limits for high-capacity enterprise storage.^[26] A pivotal architectural shift occurred in 2013 with Samsung's introduction of V-NAND, the first mass-produced 3D NAND flash using vertical stacking of memory cells in a charge-trap structure, which overcame planar scaling barriers by layering cells upward rather than shrinking laterally.^[27] This vertical channel design improved efficiency and yield, evolving rapidly to exceed 200 layers by 2025 through innovations like multi-tier stacking and advanced etching techniques, significantly enhancing bit density and performance for data centers and mobile devices.^[28] In 2024–2025, advancements tailored flash for AI workloads included Macronix's compute-in-memory 3D NOR flash, which integrates processing logic within the memory array to accelerate edge AI inference by reducing data movement overhead and enabling direct matrix operations.^[26] Complementing this, SanDisk developed High Bandwidth Flash (HBF), a NAND-based solution using wafer bonding to achieve HBM-like read bandwidth while providing 8–16 times the capacity, targeting memory-centric AI systems for large-scale model training and inference.^[29]

Operating principles

Core mechanisms

Flash memory relies on the storage of electrical charge in an isolated layer within a metal-oxide-semiconductor field-effect transistor (MOSFET) to enable non-volatile data retention. The foundational device structure is the floating-gate MOSFET, developed by Dawon Kahng and Simon Sze in 1967, consisting of a control gate—typically made of poly-silicon—overlying a conductive floating gate that serves as the charge storage element.^[30] This floating gate is electrically isolated, allowing injected charges to modulate the transistor's threshold voltage and represent binary states without continuous power supply.^[30] The isolation of the floating gate is achieved through surrounding oxide layers: a thin tunnel oxide (typically silicon dioxide, ~7–10 nm thick) between the floating gate and the substrate channel, and a thicker blocking oxide or inter-poly dielectric between the floating gate and control gate. These oxide layers provide high potential barriers (approximately 3.1 eV for SiO₂) that trap electrons on the floating gate, ensuring long-term non-volatility by minimizing thermal emission or leakage currents under normal operating conditions.^[31] Fowler-Nordheim tunneling governs the quantum mechanical transport of charges across these oxides, enabling programming and erasure by applying high electric fields (~10 MV/cm) to bend the potential barrier into a triangular shape, allowing electrons to tunnel through without significant impact ionization.^[32] The tunneling current density J is described by the Fowler-Nordheim equation:

J = \frac{q^3 E^2}{8 \pi h \phi} \exp\left( -\frac{8 \pi \sqrt{2 m \phi^3}}{3 q h E} \right)

where q is the electron charge, E is the electric field strength, \phi is the work function or barrier height, h is Planck's constant, and m is the electron effective mass.^[32] As an alternative to the continuous conductive floating gate, charge-trap flash (CTF) employs a non-conductive nitride layer (typically Si₃N₄) as the charge storage medium, where electrons are captured in discrete traps rather than delocalized across a conductor.^[33] This structure mitigates inter-cell capacitive coupling effects that plague floating-gate devices during scaling, as charge redistribution in a shared floating gate can inadvertently alter neighboring cell thresholds; in CTF, localized trapping confines interference to adjacent oxide regions.^[33] Like floating-gate variants, CTF maintains non-volatility through surrounding oxide layers that isolate the nitride trap sites, with similar Fowler-Nordheim mechanisms for charge injection, though the discrete traps enhance reliability in densely packed arrays.^[33]

Programming and erasing

Programming in flash memory cells typically involves injecting electrons onto the floating gate to store a logical '0', while erasing removes these electrons to reset the cell to a logical '1'. In some early flash memory designs, such as certain NOR-type cells, programming was achieved through hot-carrier injection, where high-energy electrons generated near the drain are accelerated into the floating gate under a positive gate voltage of around 12 V and a drain voltage of 6-7 V. Programming and erasing mechanisms vary by architecture: NOR flash typically uses channel hot electron injection for programming and Fowler-Nordheim (FN) tunneling for erasing, while NAND flash employs FN tunneling for both operations, enabling quantum mechanical tunneling of electrons through a thin oxide layer under high electric fields exceeding 10 MV/cm.^[34] These operations require high voltages, typically 15-20 V for programming and up to 20 V for erasing, far exceeding the standard supply voltages of 1.8-5 V in integrated circuits. To generate these voltages internally without external high-voltage supplies, flash memory chips incorporate on-chip charge pump circuits, such as Dickson or cross-coupled types, that boost the low supply voltage through capacitive multiplication and regulation. The erase process involves bulk erasure of multiple cells simultaneously, often an entire block, by applying a high positive voltage (around 15-20 V) to the substrate or source/drain regions while grounding the control gate, facilitating FN tunneling of electrons from the floating gate to the substrate and thereby resetting the cells to the erased '1' state with a low threshold voltage.^[35] This collective erasure contrasts with byte-level operations in other memory types and ensures efficient clearing of large data sectors. To achieve precise control during programming and prevent over-programming that could lead to threshold voltage overshoot, flash memory employs incremental stepping pulse programming (ISPP), where programming pulses of increasing amplitude (typically stepping by 0.2-0.5 V) are applied iteratively, followed by verification reads to adjust the next pulse until the target threshold voltage is reached. This method, introduced in early NAND flash designs, tightens the distribution of programmed cell threshold voltages, enhancing reliability in multi-level cell applications.

Architectural variations

Flash memory architectures vary primarily between NOR and NAND types, each optimized for different access patterns and density requirements. In NOR flash, memory cells are arranged in parallel rows, with one end of each cell connected to a source line and the other directly to a bit line, mimicking a NOR gate structure. This parallel organization enables random access akin to RAM, where address lines map the entire memory range for short read times. As a result, NOR is particularly suitable for executing code directly from the memory without needing to load it into a separate RAM.^[36] NAND flash, by contrast, connects multiple memory cells—typically 32 to 128—in series to form strings, which are then grouped into pages and blocks for organized storage. This serial string configuration achieves higher density, with a unit cell area approximately 60% smaller than NOR's due to reduced wiring overhead. Access operations in NAND are page-based, typically involving 2KB pages plus spare areas for error correction, making it efficient for sequential read and write patterns but less ideal for random access.^[37] To overcome planar scaling limits, 3D integration has become prominent in NAND architectures, stacking multiple layers of memory cells vertically to boost capacity while maintaining cost efficiency. Modern 3D NAND architectures typically employ charge trap flash (CTF) for the charge storage layer to enable better scaling and minimize cell-to-cell interference compared to traditional floating-gate designs.^[38] In these designs, vertical channels run through the stacked layers, surrounded by gate-all-around structures for control. Bit Cost Scalable (BiCS) technology, developed by Toshiba, exemplifies this approach with vertically stacked gates—including lower and upper select gates alongside control gates—formed around polycrystalline silicon channels in a gate-first process.^[39] Specifically, in vertical NAND, fabrication involves etching channel holes through the entire stack of layers using plasma techniques, then filling these holes with polysilicon to create the conductive channel path essential for charge transport.^[40] This vertical orientation allows for hundreds of layers in modern implementations, significantly enhancing bit density over traditional 2D layouts.^[39]

Flash memory types

NOR flash

NOR flash memory employs a parallel array structure where memory cells are connected such that each cell's drain is tied to a shared bit line, and sources are connected to a common source line, enabling individual access to bytes or words for random read and write operations.^[41] This configuration, often referred to as a NOR-type array, contrasts with series-connected architectures by allowing direct addressing without the need for block-level operations, which supports efficient code execution directly from the memory.^[42] Programming in NOR flash is achieved through channel hot electron (CHE) injection, where high voltages on the control gate and drain accelerate electrons from the channel into the floating gate, raising the threshold voltage to store a logic '0'.^[43] Erasing occurs via Fowler-Nordheim (FN) tunneling, in which electrons are removed from the floating gate to the substrate under a high negative bias on the control gate, lowering the threshold voltage for a logic '1' state; this process typically affects sectors or blocks simultaneously.^[43] These mechanisms ensure reliable non-volatile storage but require careful voltage management to avoid over-programming. NOR flash typically offers an endurance of up to 100,000 program/erase (P/E) cycles per cell, providing robust longevity for applications demanding frequent updates, with densities reaching 1-2 Gb in commercial devices.^[5] Its key advantage lies in execute-in-place (XIP) capability, facilitated by fast random-access reads and the ability to perform byte/word writes, allowing microcontrollers to run code directly from the flash without loading into RAM, thus reducing system costs and boot times in embedded environments.^[44]

NAND flash

NAND flash memory utilizes a distinctive string-based architecture to achieve high storage density. In this design, a NAND string comprises 32 to 128 memory cells connected in series, forming a compact vertical or horizontal chain that minimizes interconnects and maximizes efficiency.^[45] At each end of the string, select transistors—typically a string select transistor (SST) and a ground select transistor (GST)—are integrated to isolate the string during operations and connect it to the bit line and source line, respectively.^[46] This serial arrangement, as detailed in core architectural variations, enables efficient sharing of control lines across multiple strings, contributing to the overall scalability of NAND arrays.^[47] Programming in NAND flash occurs at the page level, where data is written simultaneously across all cells in a row, with typical page sizes ranging from 4 to 16 KB including spare areas for metadata.^[47] Erasure, however, is a block-level operation that resets an entire group of pages—usually 128 to 512 KB in size—to a uniform erased state, as individual cell erasure is not feasible due to the shared substrate in the string structure.^[47] These granularities optimize for sequential access patterns, distinguishing NAND from other flash types by prioritizing bulk operations over fine-grained updates. To boost throughput, contemporary NAND controllers leverage multi-plane operations, partitioning each die into independent planes that can execute concurrent reads, programs, or erases without interference. This parallelism, often supporting 2 to 4 planes per die, can multiply effective bandwidth by allowing interleaved commands across planes. Integrated error correction further enhances reliability, with low-density parity-check (LDPC) codes becoming standard for correcting raw bit error rates that increase with shrinking cell sizes and multi-bit storage.^[48] LDPC's iterative decoding provides superior performance over earlier BCH codes, enabling sustained operation in high-density environments.^[48] NAND flash maintains density leadership through advancements in 3D stacking, where cells are layered vertically in a charge-trap architecture to overcome planar scaling limits.^[49] By 2025, this has enabled single-die capacities up to 2 Tb via over 300-layer stacks, supporting quad-level cell (QLC) technology for cost-effective mass storage.^[49] Such vertical integration not only amplifies bit density but also improves endurance and speed compared to two-dimensional predecessors.^[49]

Advanced and emerging variants

Flash memory has evolved beyond basic single-level cell (SLC) configurations to include multi-level cell (MLC) variants that store multiple bits per cell, enabling higher storage density at the cost of reduced endurance and reliability. SLC stores 1 bit per cell and offers high endurance, typically supporting 50,000 to 100,000 write/erase cycles, making it suitable for applications requiring frequent updates.^[3] In contrast, MLC (2 bits/cell), TLC (3 bits/cell), QLC (4 bits/cell), and emerging PLC (5 bits/cell) architectures increase density by distinguishing more voltage states, but they exhibit progressively lower endurance—often dropping to 1,000–3,000 cycles for TLC and below 1,000 for QLC—due to increased susceptibility to read/write disturbances and charge retention issues.^[50] These trade-offs prioritize capacity for consumer storage while necessitating advanced error correction to maintain reliability.^[3] Advancements in 3D NOR flash address density limitations of planar designs, with Macronix pioneering a 3D NOR architecture that stacks memory layers vertically to achieve higher capacities and faster read speeds. Debuted at electronica 2024, this technology reduces reliance on DRAM by integrating compute-in-memory capabilities, enabling efficient AI inference at the edge through in-situ processing that minimizes data movement.^[51]^[26] The 3D structure supports up to 32 layers initially, improving performance for embedded AI tasks while maintaining NOR's random access advantages.^[52] High Bandwidth Flash (HBF), a NAND-based variant developed by SanDisk, targets AI workloads by delivering DRAM-like speeds in a denser, non-volatile package to overcome memory bandwidth bottlenecks. Announced in 2025, HBF leverages advanced wafer bonding and BiCS NAND stacking to provide 8 to 16 times the capacity of High Bandwidth Memory (HBM) while matching its read bandwidth, enabling larger AI models to reside directly on GPUs.^[29] In collaboration with SK Hynix for standardization, initial samples are slated for late 2026, with prototypes demonstrated at Flash Memory Summit 2025 focusing on AI inference acceleration.^[53]^[54] Flash evolutions toward persistent memory interfaces draw inspiration from technologies like Optane, with 3D stackable architectures enabling storage-class memory (SCM) roles that bridge DRAM speed and NAND capacity. Macronix's 3D AND-type flash, for instance, supports fast-read SCM operations in high-density configurations, facilitating byte-addressable persistence for data-intensive computing without full DRAM replacement.^[55] While hybrids with MRAM or FeRAM explore enhanced endurance, flash-centric variants emphasize scalable, cost-effective persistence for AI and edge applications.^[26]

Physical and performance characteristics

Capacity and scalability

Flash memory's capacity has advanced significantly through innovations in cell density and vertical stacking, enabling terabyte-scale storage in compact forms. Modern NAND flash commonly employs multi-level cell (MLC) technologies, storing multiple bits per cell to boost density without proportionally increasing physical size. For instance, triple-level cell (TLC) configurations store three bits per cell, while quad-level cell (QLC) achieves four bits per cell, with QLC now comprising over 20% of the PC market in 2025.^[56]^[57]^[56] Experimental demonstrations have even reached seven bits per cell in 3D flash prototypes, hinting at further density gains.^[58] Vertical scaling via 3D architectures further amplifies capacity by stacking memory cells in layers, with leading manufacturers producing over 200 layers by 2025. Samsung's eighth-generation V-NAND, for example, utilizes 236 layers.^[59] Similarly, SK Hynix's 238-layer TLC process supports high-volume production, while Micron has mass-produced 238-layer NAND.^[59]^[60] By late 2025, advancements like Samsung's tenth-generation V-NAND exceeding 400 layers have entered mass production, enabling even higher densities.^[61] These multi-hundred-layer stacks enable SSDs with capacities exceeding 8 TB in standard form factors, driven by the shift from planar to vertical channel structures. However, scaling to higher densities introduces physical challenges that limit further improvements. Cell-to-cell interference, where programming one cell affects neighboring ones, persists as a key issue, though 3D NAND reduces it by about 40% compared to planar designs due to greater physical separation.^[62] In tall 3D stacks exceeding 200 layers, string current reduction becomes prominent, as the elongated channel paths increase resistance and diminish drive current, complicating read and write operations.^[63]^[64] Material engineering, such as optimized dielectrics and channel materials, is employed to mitigate these effects and sustain reliability.^[65] Looking ahead, projections indicate continued capacity expansion, with petabyte-scale SSDs entering production by 2030 through layer counts surpassing 1,000.^[66] Enterprise SSD market shipments are forecasted to reach 1,078 exabytes annually by 2030, fueled by AI and data center demands.^[67] Extreme ultraviolet (EUV) lithography plays a crucial role in enabling sub-10nm nodes for peripheral circuitry and finer patterning in 3D NAND, supporting z-pitch scaling below 50 nm.^[68]^[69] These advancements have driven down costs, with 3D stacking contributing to a long-term decline from higher levels in prior generations.^[70] Overall, NAND flash density has increased over a million-fold since its inception, primarily through bit-per-cell multiplication and layer stacking.^[71]

Speed and endurance

Flash memory's performance is characterized by its read and write speeds, which vary significantly between NOR and NAND architectures, as well as endurance limits defined by program/erase (P/E) cycles. NOR flash excels in random read operations, achieving transfer rates up to 400 MB/s through direct memory access and fast sensing mechanisms, making it suitable for code execution in embedded systems.^[72] In contrast, NAND flash prioritizes sequential throughput, with modern NVMe-based SSDs delivering over 10 GB/s in sequential reads, as demonstrated by enterprise drives like the Micron 7600 series reaching 12 GB/s.^[73] These speeds are enabled by parallel data paths and high-bandwidth interfaces, though random reads in NAND are typically slower due to its block-oriented structure. Write endurance in flash memory is constrained by the number of P/E cycles a cell can withstand before degradation, with single-level cell (SLC) NAND offering up to 100,000 cycles for high-reliability applications.^[74] Multi-level variants trade endurance for density: triple-level cell (TLC) sustains around 3,000 cycles, while quad-level cell (QLC) drops below 1,000 cycles, limiting its use in write-intensive scenarios.^[75] To mitigate uneven wear, wear-leveling algorithms distribute writes across cells, extending overall device lifespan by balancing usage.^[76] Read speeds in flash are fundamentally limited by sensing amplifiers, which detect small voltage differences in cells and typically operate in the range of 50-100 ns per access, bottlenecking parallel operations in dense arrays.^[77] Performance optimizations, such as SLC caching in TLC NAND drives, temporarily map writes to pseudo-SLC regions for faster initial throughput—up to several GB/s—before folding data to native TLC, as seen in Micron's Adaptive Write Technology.^[78] In enterprise benchmarks by 2025, SSDs like the Phison Pascari X200P achieve over 3 million random read IOPS, highlighting optimizations in controller design and NAND stacking for high-concurrency workloads.^[79]

Limitations and reliability

One fundamental limitation of flash memory is the block erasure requirement, which necessitates erasing an entire block of cells before reprogramming any portion of it, as individual bits or pages cannot be directly overwritten. This constraint arises from the physics of charge storage in floating-gate or charge-trap structures, where erasing involves applying a high voltage to remove electrons collectively from the block. As a result, operations like garbage collection in flash-based storage systems lead to write amplification, where significantly more data is written to the medium than the user intends, increasing overhead and wear.^[80]^[81] Data retention in flash memory is another key constraint, typically specified at around 10 years under room-temperature conditions for commercial devices, though this duration shortens with elevated temperatures and prior wear due to gradual leakage of trapped charges through the tunnel oxide. The primary mechanism involves thermal emission of electrons from the storage layer, exacerbated by stress-induced defects that create leakage paths, leading to threshold voltage shifts and potential data errors over time. High temperatures accelerate this process exponentially, following Arrhenius-like behavior observed in accelerated bake tests across multiple technology nodes.^[82]^[83]^[84] Memory wear manifests primarily through progressive degradation of the tunnel oxide layer during repeated program/erase cycles, culminating in irreversible breakdown that traps excessive charge or creates conductive paths, thereby limiting the device's lifespan. This oxide wear is driven by phenomena such as anode hole injection and local field enhancements at the silicon-oxide interface, which accumulate defects and reduce the insulating properties over cycles typically ranging from thousands to hundreds of thousands, depending on the architecture. Additionally, read disturb effects arise from repeated read operations on a cell or page, where the pass voltage applied to unselected cells in the array causes electron injection or hole trapping, gradually shifting their threshold voltages toward erroneous states.^[81]^[85] In dense memory arrays, program and erase disturbs further compromise reliability, as high voltages applied to target cells inadvertently affect neighboring cells through coupling or leakage currents, leading to unintended threshold voltage alterations. For instance, during programming, adjacent cells may experience charge gain via substrate injection, while erase operations can induce soft breakdowns in nearby oxides. Exposure to X-ray radiation introduces additional risks by generating trapped charges in the gate dielectrics or oxide layers, resulting in charge loss or gain that degrades read margins, particularly evident after high-dose exposures or during subsequent retention periods. These limitations collectively underscore the need for careful management of operational stresses to maintain flash memory integrity.^[86]^[87]^[88]

Applications

Embedded and firmware uses

Flash memory plays a crucial role in embedded systems and firmware applications, where non-volatility, low power consumption, and compact form factors are essential for boot processes and code execution in resource-constrained devices. Serial NOR flash, typically interfaced via SPI, is extensively used for storing BIOS and UEFI firmware in personal computers, safeguarding critical settings like UEFI variables and preventing rollback attacks through features such as replay-protected memory block (RPMC). These devices offer densities ranging from 512 Kbit to 512 Mbit in standard configurations, with stacked variants like SpiStack enabling up to 512 MB or more by combining multiple dies for code storage needs. ^[89] ^[90] ^[91] This architecture supports execute-in-place capabilities, allowing direct code execution from the flash without RAM transfer. In smartphones and portable devices, embedded standards such as eMMC and UFS provide integrated NAND flash solutions for operating system boot and application storage. eMMC, or embedded MultiMediaCard, functions as a managed NAND interface that simplifies integration and delivers reliable performance for mobile mass storage. ^[92] UFS has emerged as the preferred successor, with UFS 4.0 offering sequential read speeds of up to 4.2 GB/s and write speeds up to 2.8 GB/s, facilitating rapid data access in high-end smartphones as of 2025. ^[93] ^[94] Field-programmable gate arrays (FPGAs) rely on flash memory to store configuration bitstreams, which are loaded into the FPGA's volatile SRAM at power-on or boot to define the device's logic functionality. SPI NOR flash is commonly selected for this purpose due to its fast random access and compatibility with FPGA configuration modes, ensuring reliable reconfiguration without persistent external programming. ^[95] ^[96] Automotive and industrial embedded systems demand flash memory qualified under AEC-Q100 standards to endure extreme conditions, including temperatures from -40°C to +125°C and vibrations. AEC-Q100-compliant NOR flash, such as Infineon's SEMPER series, incorporates error correction and cyclic redundancy checks for enhanced reliability in safety-critical applications like engine control units and industrial controllers. ^[97] Similarly, managed NAND solutions like Micron's UFS meet these qualifications, supporting robust operation in vehicle infotainment and sensor systems. ^[98] ^[99]

Storage and computing integration

Solid-state drives (SSDs) based on flash memory have become the primary storage solution in modern computing systems, largely replacing traditional hard disk drives (HDDs) due to their superior speed, reliability, and energy efficiency. The NVMe protocol, optimized for flash storage, has evolved significantly to leverage high-bandwidth interfaces like PCIe 5.0, enabling sequential read and write speeds exceeding 14 GB/s in contemporary implementations.^[100] By 2025, consumer-grade SSDs routinely offer capacities greater than 8 TB, such as the Samsung 9100 Pro, facilitating seamless integration into personal computers, laptops, and workstations for operating system boot times and application loading that are orders of magnitude faster than HDDs.^[101] Hybrid storage systems combine SSDs with remaining HDD tiers for cost-effective tiering, where flash handles frequent access patterns while HDDs manage bulk data, optimizing overall system performance in desktops and servers.^[102] Specialized flash file systems address the unique constraints of NAND flash, such as limited write cycles and block-level operations, to ensure efficient storage integration. The Flash-Friendly File System (F2FS), developed by Samsung, employs multi-head logging and hot/cold data separation to implement wear-leveling, distributing writes evenly across flash blocks to extend device lifespan, while relying on the underlying flash translation layer (FTL) for bad block detection and management during garbage collection.^[103] Similarly, Yet Another Flash File System (YAFFS), designed for embedded NAND environments, achieves wear-leveling through garbage collection that relocates valid data and erases dirty blocks, with bad blocks explicitly marked using spare area bytes during formatting and scanning to prevent data corruption.^[104] These file systems enable direct flash access in computing setups, minimizing overhead from traditional file systems ill-suited for flash's erase-before-write mechanism, which is handled at the block level as detailed in reliability discussions.^[103] Flash memory has also explored roles as a persistent alternative to volatile RAM, bridging the gap between DRAM speed and non-volatile storage. Intel's Optane, utilizing 3D XPoint technology, served as a byte-addressable persistent memory module that accelerated data-intensive workloads by providing DRAM-like latency with data retention across power cycles, but production was phased out by September 2022 due to market challenges.^[105] Post-Optane research continues in hybrid persistent memory architectures, including combinations of embedded DRAM (eDRAM) with flash for caching and persistence, aiming to sustain low-latency access in memory hierarchies without full DRAM replacement.^[106] In data centers, all-flash arrays (AFAs) dominate high-performance storage by eliminating HDD bottlenecks, delivering latencies under 100 μs for random reads compared to 5-10 ms on HDDs, which significantly reduces tail latency in cloud services and virtualized environments.^[102] This shift enables scalable computing integration, where AFAs support NVMe-over-Fabrics for disaggregated storage, enhancing throughput for big data analytics and AI training while lowering power consumption relative to hybrid HDD setups.^[107]

Specialized and future roles

Flash memory is increasingly adapted for archival storage applications, particularly through high-retention quad-level cell (QLC) variants designed for cold data that requires long-term preservation with minimal access. These QLC cells, storing four bits per cell in 3D NAND structures, achieve data retention of up to 1 year at 55°C for lightly used cells when combined with advanced error correction codes (ECC) such as low-density parity-check (LDPC) algorithms to mitigate retention-induced bit errors. For instance, predictive models for error bit placement in 3D QLC NAND enable optimized data layout in archival systems, ensuring reliability for backup and long-term digital preservation by compensating for charge leakage over time.^[108]^[109]^[110] In AI and edge computing, high-bandwidth flash (HBF) emerges as a specialized variant that facilitates in-memory processing by providing NAND-based memory with bandwidth approaching high-bandwidth memory (HBM), up to 64 GB/s, while offering 8 to 16 times the capacity for storing large AI models directly on-device. HBF architectures, developed by companies like SanDisk, enable mixture-of-experts AI inference at the edge by parallelizing access to multiple 3D NAND arrays, reducing latency for tasks like real-time image recognition in smartphones. Complementing this, compute-in-memory (CIM) implementations using NOR flash minimize data movement between storage and processors by performing matrix-vector multiplications within the memory array, leveraging split-gate NOR cells for low-power analog computations that store weights non-volatily and achieve up to 2.7 times better energy efficiency in deep neural network inference compared to traditional von Neumann architectures.^[111]^[112]^[113]^[114]^[115] For Internet of Things (IoT) devices and wearables, ultra-low power flash variants prioritize extended battery life through optimized serial NOR architectures with deep power-down currents as low as 7 nA and active currents under 4 mA, enabling always-on functionality in energy-constrained environments like sensors and fitness trackers. These include Macronix's MX25R series, which reduces power consumption by 60% over standard NOR flash via efficient read/write operations at 1.65V to 3.6V, supporting firmware storage and data logging in medical wearables. Additionally, SD Express cards, leveraging PCIe and NVMe protocols over the SD interface, provide high-speed portable storage up to 2 TB with read speeds exceeding 985 MB/s, ideal for high-resolution video capture in portable IoT cameras and AR glasses without compromising form factor.^[116]^[117]^[118]^[119] Flash memory is also utilized in space missions, where radiation-hardened variants withstand cosmic rays and extreme environments in satellites and probes, providing reliable non-volatile storage for telemetry data and onboard computing.^[120] Looking ahead, flash memory is poised for integration with quantum-resistant encryption to safeguard data against future quantum computing threats, incorporating post-quantum cryptography (PQC) algorithms like Kyber directly into storage controllers for secure key encapsulation in embedded systems. By 2030, flash-based disaggregated memory pools using Compute Express Link (CXL) interfaces are expected to enable scalable, shared memory architectures in data centers, allowing dynamic allocation of NAND resources across multiple compute nodes to support AI workloads, with projections indicating significant CXL adoption in memory systems. This evolution builds on emerging penta-level cell (PLC) variants, which store five bits per cell for higher density in such pooled systems.^[121]^[122]^[123]^[124]^[125]

Industry overview

Key manufacturers

Samsung Electronics is the leading manufacturer of NAND flash memory, renowned for pioneering 3D V-NAND technology that stacks memory cells vertically to increase density and capacity. In 2025, Samsung commands approximately 31% of the global NAND flash market share, driven by its advancements in high-layer-count 3D NAND and broad portfolio spanning consumer to enterprise applications.^[126] SK Hynix, another dominant player, has established itself as a pioneer in PLC (penta-level cell) NAND, enabling five bits per cell for enhanced storage efficiency, and maintains a strong presence in enterprise-grade SSDs optimized for data centers and AI workloads. The company bolstered its NAND capabilities through the acquisition of Intel's NAND and SSD business in 2021, with the transaction fully completed by early 2025, allowing SK Hynix to integrate Intel's technology and expand its production footprint. In 2025, SK Hynix holds about 18% of the NAND market, with its SK Group affiliates reaching a 21% revenue share in the second quarter.^[126]^[127]^[128]^[129] Micron Technology, SanDisk, and Kioxia form a critical tier of NAND producers, often collaborating on technology development to advance layer counts and cell technologies like QLC (quad-level cell), which stores four bits per cell for cost-effective high-capacity storage. These firms have jointly pushed QLC adoption in 3D NAND, with Micron achieving first production of 200+ layer QLC in 2024 for client and data center use, while Kioxia and SanDisk introduced 218-layer BiCS FLASH supporting both TLC and QLC configurations. Emerging collaborations, such as those involving China's Yangtze Memory Technologies Corp. (YMTC), highlight international efforts to scale production, with YMTC partnering on advanced bonding techniques for next-generation NAND. In the NAND market, these players collectively hold significant shares, with Micron, SanDisk, and Kioxia each around 10-15% in 2025.^[130]^[131]^[132]^[133] Among other notable manufacturers, Macronix International leads in NOR flash memory through its innovative SPI NOR and 3D NOR technologies tailored for embedded applications requiring fast random access. SanDisk, which became independent in early 2025 following a corporate spin-off from Western Digital, drives innovations in high-bandwidth flash (HBF), a NAND-based architecture designed to rival HBM for AI inference with superior capacity and edge computing suitability, including collaborations for standardization with partners like SK Hynix.^[134]^[53]^[135]

Market dynamics and trends

The global NAND flash market reached approximately $65 billion in 2025, fueled primarily by surging demand from AI applications and data centers, which accounted for a significant portion of enterprise solid-state drive (SSD) deployments. Annual bit shipments for NAND flash exceeded 3,200 exabits in 2024 and are projected to grow by 8-10% in 2025, reflecting robust inventory replenishment in consumer electronics and AI server builds. This expansion underscores the sector's scale, with total memory revenues, including NAND, approaching $200 billion for the year.^[136]^[137]^[60] Pricing dynamics in 2025 showed notable volatility for NAND, with contract and spot prices surging significantly year-over-year amid supply constraints from production cuts—such as SK Hynix and Micron reducing output by around 10% in the second half—and heightened AI-driven procurement. Prices more than doubled from mid-2025 levels, with TLC 1-terabit NAND rising from $4.80 in July to $10.70 in November, leading to overall year-over-year increases exceeding 100% by late 2025. In contrast, NOR flash prices remained relatively stable through much of 2025, though late-quarter pressures from cost escalations and supply tightness led to modest upward adjustments of 5-10%.^[138]^[139]^[140]^[141]^[142] Key growth drivers include escalating AI workloads necessitating high-performance storage solutions, such as those integrating advanced layer stacking for enhanced density, contributing to a projected 25-30% compound annual growth rate (CAGR) for the enterprise flash segment through 2030. This trajectory is supported by innovations in AI-optimized SSDs, which are expected to capture a larger share of data center investments. However, challenges persist, including US-China trade tensions that have imposed export controls on critical technologies, severely impacting Chinese firm YMTC's access to advanced equipment and market participation. Additionally, sustainability concerns loom large, as semiconductor fabrication facilities consume vast amounts of energy—often equivalent to small cities—prompting industry-wide efforts to reduce emissions and improve eco-friendly manufacturing processes.^[143]^[144]^[145]^[146]

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Samsung 9100 Pro 8TB SSD review: Bigger, badder, and better
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In this paper, we present the design and implemen- tation of F2FS, a new file system optimized for mod- ern flash storage devices. As far as we ...
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The Intel® Optane™ Memory products have reached End of Life production and they will no longer be supported on newer Intel® Processors starting with 12th ...Missing: phase eDRAM hybrids flash
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Persistent Memory Research in the Post-Optane Era
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RAIL: Predictable, Low Tail Latency for NVMe Flash
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High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory
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SEMPER™ Nano NOR flash is for hearables, wearables, and IoT, with compact footprint, low power, built-in ECC, and best-in-class low power.
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SanDisk's new 256GB microSD Express and 2TB microSD cards
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Why you need post quantum cryptography at the storage layer
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A quantum-safe authentication scheme for IoT devices using ...
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Market Landscape: Memory System and Connection Technologies ...
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The Next Five Years of Memory, And Why It Will Decide AI's Pace
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PLC flash: The next generation or a mirage? - Computer Weekly
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Top 5 NAND Flash Memory Manufacturers in the World as of 2025
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SK hynix completes the First Phase of Intel NAND and SSD ...
Dec 30, 2021 · SK hynix has acquired Intel's SSD business and Dalian NAND Flash Manufacturing Facility assets in China. The new entity will be branded ...
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NAND Flash Revenue Surged Over 20% in 2Q25, SK Group Market ...
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SK hynix completes its acquisition of Intel's NAND business - Evertiq
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Micron First to Production of 200+ Layer QLC NAND in Client and ...
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Kioxia and Western Digital Announce Newest 3D Flash Memory
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[127]
NAND Flash Memory 10.7 CAGR Growth Outlook 2025-2033
Rating 4.8 (1,980) Jun 18, 2025 · Samsung, Kioxia, Western Digital (WDC), Micron, SK Hynix, and Intel collectively hold over 90% of the market share, with Samsung and Kioxia ...
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Samsung will team up with its fiercest Chinese rival to ... - TechRadar
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NOR Flash Memory Market in 2025: Key Vendors and Top Chips ...
Aug 5, 2025 · In 2025, the NOR flash memory market can be estimated to reach around $3.2 billion and representing 4% of the total flash memory market.
[130]
Sandisk investor day outlines roadmap post WD spin-off
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Memory market surges beyond expectations: almost $200 billion in ...
Jun 19, 2025 · 2025 will mark a second consecutive year of record memory revenues, expected to exceed $190 billion with $129 billion and $65 billion for DRAM and NAND market ...
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NAND Flash Memory and DRAM Market Size | Industry Insights [2033]
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Memory Market Trends 2025: Price Surge & Supply Chain Risk
Oct 1, 2025 · The price outlook for the NAND Flash market in Q3 2025 is clearly bullish. The market is experiencing significant price rises across all ...
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NAND Flash Prices to Rise 5–10% in 4Q25, Driven by ... - TrendForce
Sep 25, 2025 · In 1H25, production cuts and shipment adjustments by client SSD suppliers have greatly decreased inventories, helping to restore market balance.
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NOR flash prices set to surge in 4Q25 on cost pressures, supply ...
Aug 26, 2025 · NOR flash prices set to surge in 4Q25 on cost pressures, supply constraints. After months of sluggish demand and weakened pricing, the NOR ...
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All Flash Array Market: Industry Analysis and Forecast
Historical Data: 2018 to 2023, Market Size in 2023: ; Forecast Period 2024 to 2030 CAGR: 24.27%, Market Size in 2030: ; Segments Covered: by Storage Architecture/ ...
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Enterprise Flash Storage Market Size, Competitors & Forecast
The enterprise flash storage market is forecasted to grow by USD 27.69 billion during 2024-2029, accelerating at a CAGR of 27.5% during the forecast period.
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Beijing's anger at 'extremely malicious' US move to ramp up ... - CNN
Sep 30, 2025 · The US action aims to stop sanctioned companies – including technology champion Huawei, memory chip giant YMTC and drone maker DJI – from ...
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https://www.trendforce.com/presscenter/news/20250925-12736.html