Vectored interrupt

A vectored interrupt is a type of hardware interrupt mechanism in computer architecture where an interrupting device or event supplies the processor with a unique vector number or address that directly points to the entry point of the corresponding interrupt service routine (ISR), stored in an interrupt vector table.^[1]^[2] This approach contrasts with non-vectored interrupts, which require the processor to execute a common handler that polls multiple devices to identify the source, introducing latency and inefficiency.^[1]^[2] Vectored interrupts enable faster response times by automating source identification through dedicated hardware connections or vector provision, making them essential in modern microprocessors for handling asynchronous events like I/O requests or timers.^[1]^[3] In operation, when an interrupt occurs, the device's controller sends its assigned vector number to the processor, which uses this to index the interrupt vector table—an array of pointers or addresses typically located in ROM or system memory—and loads the associated handler's starting address into the program counter (PC).^[2]^[1] The vector table is initialized during system startup, either manually by assigning fixed vectors to devices or automatically through hardware polling to detect and configure sources.^[2] For the interrupt to be serviced, several conditions must be satisfied, including the device being armed, the interrupt controller (e.g., NVIC in ARM-based systems) enabled, global interrupts active, and the interrupt's priority exceeding the current processor level.^[1] Upon handler execution, the processor saves the current context (e.g., PC and status registers) to allow resumption after handling.^[3] The concept of vectored interrupts has roots in early computer designs, with proposals for priority-based vectoring appearing as early as 1957 in discussions of multiprogramming systems like the IBM Stretch.^[3] Modern implementations vary: in architectures like ARM Cortex-M, vectors are fixed in a table starting at address 0x0000.0000, with examples including the SysTick_Handler at 0x0000.003C for periodic timing or GPIOPortF_Handler at 0x0000.00B8 for GPIO events.^[1] In x86 systems, the vector table (IDT) supports up to 256 entries, while RISC-V uses a base address configurable at runtime.^[3] These systems often incorporate priority levels to resolve simultaneous interrupts, queuing lower-priority ones until higher ones are resolved.^[3] Vectored interrupts remain a cornerstone of efficient real-time processing in embedded systems, operating systems, and general-purpose computing.^[1]^[2]

Fundamentals

Definition

A vectored interrupt is a type of hardware interrupt in which the interrupting device supplies a vector to the processor, which is either a direct memory address pointing to the interrupt service routine (ISR) or an index used to locate the ISR via a table lookup, enabling efficient dispatch to the appropriate handler.^[2]^[4] This mechanism supports direct or indirect jumping to the ISR, distinguishing it from simpler interrupt schemes by allowing the hardware to identify the specific source and routine without additional software intervention.^[5] Unlike polling-based input/output methods, where the processor repeatedly queries device statuses, vectored interrupts provide asynchronous notifications that enhance efficiency in multi-device environments by minimizing CPU overhead and enabling rapid response to events.^[6]

Basic Mechanism

In a vectored interrupt system, the process begins when a peripheral device asserts an interrupt signal to notify the processor of an event requiring attention, simultaneously providing a unique vector number that identifies the specific interrupt source.^[2] The processor acknowledges this signal, typically by halting the current instruction execution at an appropriate boundary, and receives the vector from the device through dedicated signaling.^[5] This vector directly determines the address of the corresponding interrupt service routine (ISR), enabling rapid dispatch without additional identification steps.^[1] Upon receiving the vector, the processor automatically saves the current execution context to preserve the state of the interrupted program. This hardware-managed step typically involves pushing essential registers—such as the program counter (PC), which holds the address of the next instruction, and status flags or registers indicating the processor's mode and condition—onto the system stack.^[5]^[1] The processor then uses the vector to compute or retrieve the starting address of the ISR and jumps to it, initiating the handler's execution.^[2] The ISR performs the necessary actions to service the interrupt, such as reading device status or transferring data, after which it signals completion. To return control to the original program, the ISR executes a dedicated return-from-interrupt instruction, often abbreviated as RTI, which restores the saved context by popping the PC and status registers from the stack, thereby resuming execution from the point of interruption.^[7]^[1] This mechanism enhances efficiency by eliminating the need for software polling or sequential querying of devices to identify the interrupt source, thereby minimizing latency and overhead in interrupt handling compared to non-vectored approaches.^[2]

Comparison to Other Interrupts

Non-Vectored Interrupts

Non-vectored interrupts are a type of interrupt mechanism in which the processor responds to an interrupt signal by jumping to a single, fixed entry point in memory, without receiving a specific vector address from the interrupting device; instead, the processor must then identify the source through additional steps such as polling the devices or using a daisy-chain arrangement.^[3] This approach contrasts with more advanced systems by relying on software or simple hardware logic to resolve the interrupt source after the initial signal.^[8] Historically, non-vectored interrupts were predominant in early computer systems during the 1950s, such as the UNIVAC 1103 introduced in 1953, where interrupts served as basic signals to halt normal processing, allowing overlapped execution of programs and device activities.^[3] These early implementations marked the initial adoption of interrupts to improve system efficiency over purely sequential processing, though they were limited to simple signaling without prioritization or direct routing.^[3] The primary operational drawbacks of non-vectored interrupts arise from the need for a polling loop, in which the processor sequentially queries each potential device to determine the interrupt source, or a daisy-chain resolution, where devices are wired in series to pass the interrupt acknowledgment signal until the requesting device claims it, both of which introduce significant latency in environments with multiple devices.^[9] Polling wastes processor cycles on non-interrupting devices, while daisy-chaining imposes a fixed priority based on physical wiring, potentially delaying lower-priority devices and complicating scalability as the number of peripherals grows.^[10] These limitations highlight the evolution toward vectored interrupts for faster, more direct handling in multi-device setups.^[3] Examples of non-vectored interrupts include simple single-device systems like early embedded controllers, where only one peripheral can interrupt and no source identification is needed, or software-polled I/O in systems such as the PDP-8 minicomputer, which uses a fixed memory address for all interrupts followed by polling to check status registers.^[3] In such cases, the mechanism suffices for low-complexity environments but becomes inefficient as system demands increase.^[9]

Autovectored Interrupts

Autovectored interrupts represent a hybrid form of vectored interrupt handling in which the hardware—typically the CPU or an external interrupt controller—automatically generates the interrupt vector corresponding to the active input line, eliminating the need for the interrupting device to provide the vector address itself. This approach relies on predefined mappings within the hardware to direct the processor to the appropriate interrupt service routine (ISR). Such interrupts are commonly implemented in early microprocessors to simplify interrupt processing while providing some level of automation beyond basic non-vectored schemes.^[11] The mechanism of autovectored interrupts generally involves priority resolution logic, such as priority encoders or daisy-chained controllers, that identifies the highest-priority interrupting input among multiple lines and selects a fixed vector associated with that line. In the Intel 8085 microprocessor, for example, the maskable interrupts RST 5.5, RST 6.5, and RST 7.5 are autovectored, automatically branching the program counter to hardcoded addresses: 002CH for RST 5.5, 0034H for RST 6.5, and 003CH for RST 7.5. Similarly, the Intel 8259 Programmable Interrupt Controller (PIC) employs internal priority encoding to resolve interrupts from its eight input lines (IR0–IR7) and generates an 8-bit vector during the interrupt acknowledge cycle; in early x86 real-mode configurations such as the IBM PC, the master PIC assigns vectors 08H through 0FH, while a cascaded slave PIC uses 70H through 77H for its lines.^[12]^[13]^[11]^[14] This hardware automation allows for efficient handling without software intervention to determine the source, though it requires initialization to set the vector base and spacing. Despite their efficiency, autovectored interrupts have notable limitations, including reduced flexibility compared to systems where devices supply custom vectors, as the predefined vectors per line prevent fine-grained customization for multiple devices sharing the same input. The number of supported interrupt lines is also constrained by the hardware design—typically eight per controller in devices like the 8259—necessitating cascading for larger systems, which adds complexity and potential latency. Additionally, since vectors are fixed or base-offset based, reconfiguring priorities or adding new interrupt types often requires hardware modifications or reprogramming, limiting adaptability in dynamic environments.^[13]^[11]

Implementation

Hardware Components

The hardware components enabling vectored interrupts primarily consist of interrupt request (IRQ) lines that connect peripheral devices to the central processing unit (CPU), allowing devices to signal interrupt conditions. These lines transmit electrical signals indicating the need for CPU attention, often encoded with priority levels to facilitate handling multiple requests. For instance, in the Motorola MC68000 microprocessor, three dedicated input pins—IPL0, IPL1, and IPL2—form a 3-bit IRQ interface that encodes seven priority levels (1–7), with level 7 being non-maskable.^[15] Similarly, the Zilog Z80 uses a single active-low INT pin (pin 18) for maskable IRQ requests, sampled at the end of each instruction cycle if enabled.^[16] The data bus serves as the pathway for vector transmission, carrying the interrupt vector from the interrupting device to the CPU during a dedicated acknowledge cycle. This bus enables the device to supply an address or offset that directs the CPU to the appropriate service routine. In early systems, support was typically provided for 8-bit or 16-bit vectors; the Z80's 8-bit bidirectional data bus (D7–D0, pins 1–8) allows a peripheral to place the lower 8 bits of the vector during the interrupt acknowledge phase, when the IORQ signal (pin 20) activates.^[16] The MC68000 employs a 16-bit data bus (D15–D0), where an external device asserts an 8-bit vector on D7–D0 during the 4-clock interrupt acknowledge cycle, signaled by the function code bus (FC2–FC0) and upper address lines (A19–A16) going high.^[15] An interrupt controller, often implemented as external circuitry or integrated logic, manages prioritization, buffering, and vector generation to resolve conflicts among multiple IRQ sources. This component arbitrates requests and ensures only the highest-priority vector proceeds, using daisy-chain or priority encoder mechanisms. In the Z80 ecosystem, peripherals like the Z80 PIO or SIO form a daisy-chain structure to serially resolve priorities and supply the vector without a central controller on the CPU itself.^[17] For the MC68000, external devices or a programmable interrupt controller (e.g., using a 74LS148 priority encoder) buffer and prioritize the seven IRQ levels before asserting the IPL pins, with the CPU fetching the vector if a device responds during acknowledgment.^[15] Masking and enabling of specific vectors occur through interrupt enable flags in the CPU's status registers, allowing selective disabling to prevent lower-priority interruptions during critical operations. These flags provide granular control at the circuit level, typically set or cleared via software but reflected in hardware registers. The Z80's interrupt enable flip-flops (IFF1 and IFF2) in its internal state logic mask all maskable interrupts when reset by a DI instruction, while the NMI input (pin 24) bypasses this for non-maskable events.^[16] In the MC68000, the status register's 3-bit interrupt mask (I2–I0) inhibits interrupts at or below the set level (0–7), adjustable only in supervisor mode, ensuring hardware-level enforcement of priorities.^[15] Representative examples of these components appear in classic microprocessors like the Z80 and MC68000, which feature dedicated vectored interrupt pins and buses for efficient vector handling. The Z80's INT and NMI pins, combined with its data bus and daisy-chain support, enable Mode 2 vectored interrupts where devices directly contribute to address formation.^[16] The MC68000's IPL pins, data bus, and address strobe (AS) integrate with external controllers to support user-vectored modes, providing 256 possible vectors via an 8-bit field.^[15]

Vector Table and Processing

The vector table, often referred to as the Interrupt Vector Table (IVT), is a contiguous array stored in system memory that maps interrupt vectors to the starting addresses of corresponding Interrupt Service Routines (ISRs). Each entry in the table typically consists of a 32-bit address or an offset pointing to the ISR, with the structure designed for efficient indirect addressing by the processor. In early microprocessor designs, such as those in the Intel 8086 family, the IVT was fixed at memory address 0x0000, occupying 1 KB to accommodate up to 256 possible interrupts, where each entry spans 4 bytes (a 16-bit offset followed by a 16-bit segment selector). In modern architectures like ARM Cortex-M, the table begins at a configurable base address (defaulting to 0x00000000) and uses 4-byte entries for exception and interrupt handlers, with the offset calculated as base + (vector number × 4).^[18] Upon receiving a vector number from the interrupt controller, the processor performs the following steps to handle the interrupt: first, it computes the table entry address by adding the vector number, scaled by the entry size (e.g., multiplied by 4 for 32-bit addresses in systems like the x86 real-mode IVT), to the table's base address; next, it fetches the ISR address from that entry; then, the processor saves the current program state (such as the program counter and status register) to the stack; finally, it loads the ISR address into the program counter and transfers control to the routine. This indirect addressing mechanism ensures rapid dispatch without software polling, typically completing in a few clock cycles after vector reception.^[19] The vector table is configured during system initialization, where the operating system or firmware populates each entry with the appropriate ISR address based on the hardware configuration. This setup occurs at boot time, often as part of the kernel or bootloader sequence, ensuring all supported interrupts are mapped before enabling the interrupt system.^[20] The table's size is determined by the maximum number of vectored interrupts supported by the architecture; for instance, ARM Cortex-M processors allocate space for up to 256 entries (16 fixed exceptions plus up to 240 interrupts), scalable via the Nested Vectored Interrupt Controller (NVIC) registers.^[21] For error handling, if an invalid vector is received—such as one exceeding the table's bounds or referencing an uninitialized entry—the processor typically traps to a default handler or invokes a fault exception to prevent erratic behavior. In ARM architectures, an invalid ISR address (e.g., one with the least significant bit set to 0, indicating a non-thumb executable) triggers a UsageFault, while out-of-range vectors lead to a HardFault escalation if unhandled.^[22] This mechanism ensures system integrity by routing anomalies to a recovery routine or diagnostic code, often configured as the final entry in the table.^[23]

Historical Development

Early Origins

The origins of interrupts trace back to 1953, when the UNIVAC 1103 became the first computer system to implement them, allowing devices to signal the processor asynchronously rather than relying solely on programmed polling in batch-oriented environments.^[3] This innovation addressed the inefficiencies of constant device checking, enabling more responsive I/O handling in early scientific computing applications.^[3] Vectored interrupts, which allow the interrupting device to supply a specific address or code directing the processor to the appropriate service routine, emerged in the late 1950s as an advancement over basic interrupt signaling. The IBM Stretch, designed in the mid-1950s and delivered in 1961, featured one of the earliest vectored systems, supporting multiple interrupt vectors per process to facilitate prioritized handling in multiprogrammed setups.^[3] Similarly, the Electrologica X1, developed in the Netherlands between 1957 and 1958, incorporated a vectored interrupt mechanism credited to E. W. Dijkstra, using up to seven distinct interrupt channels for efficient device coordination without extensive software polling.^[3] These designs marked a shift toward hardware-assisted vectoring, reducing latency in systems with growing numbers of peripherals. By the mid-1960s, vectored interrupts gained prominence in the transition to timesharing and real-time processing, driven by the need to manage multiple devices efficiently in multiprocessing environments. The IBM System/360, announced in 1964, introduced channel-based interrupts that provided detailed status words upon completion of I/O operations, enabling software to branch to device-specific handlers much like a vectored scheme, though reliant on fixed interruption codes in the Program Status Word for classification.^[24] This approach supported the demands of emerging interactive systems, where polling proved inadequate for concurrent user tasks and I/O events. The term "vectored interrupt" became formalized in technical literature during this period, reflecting its adoption in minicomputer architectures for streamlined real-time responsiveness.^[3]

Evolution in Modern Systems

In the 1970s and 1980s, vectored interrupts were integrated into early microprocessors with fixed vector schemes to support efficient handler dispatching. The Intel 8086, introduced in 1978, employed a fixed interrupt vector table (IVT) consisting of 256 entries, each pointing to a 4-byte segment:offset address for interrupt service routines, enabling direct hardware mapping without dynamic reconfiguration.^[25] This approach, while simple, limited flexibility in protected-mode environments. By the mid-1980s, the Intel 80386 processor marked a significant evolution by introducing the Interrupt Descriptor Table (IDT), a dynamic structure supporting up to 256 descriptors that include gate types (interrupt, trap, or task) and privilege levels, allowing programmable vector assignment and enhanced security through segment selectors. Modern architectures have scaled vectored interrupts to handle complex, multi-core systems with expansive vector spaces. The ARM Generic Interrupt Controller (GIC), standardized since the early 2000s and refined in versions like GICv3, supports over 1,000 interrupt sources—typically 16 software-generated interrupts (SGIs), 16 private peripheral interrupts (PPIs), and up to 1,024 shared peripheral interrupts (SPIs)—enabling prioritized routing across multi-core processors via distributor and redistributor components.^[26] In x86 systems, the Advanced Programmable Interrupt Controller (APIC), integrated since the Pentium era, facilitates vector routing in multi-core setups through its local APIC per core and I/O APIC for device interrupts, supporting up to 255 vectors (excluding reserved exceptions) with features like logical destination modes for targeted delivery to specific cores or clusters.^[25] Operating systems have adapted vectored interrupts by mapping hardware vectors to software handlers, incorporating virtualization layers for isolation. In Linux, the kernel uses the /proc/interrupts interface to expose mappings of hardware IRQs to vector numbers and handler counts, allowing dynamic affinity adjustments via irqbalance for multi-core load distribution. Windows kernels similarly abstract vectors through the Hardware Abstraction Layer (HAL), routing interrupts to drivers via IoConnectInterrupt and supporting affinity policies for performance tuning. Virtualization extensions, such as Intel VT-x, introduce hypervisor layers where interrupts cause VM exits to the host, with posted interrupts enabling direct guest delivery to minimize latency in nested environments.^[25]