Cyrix III
The Cyrix III is an x86-compatible microprocessor family developed by Cyrix Corporation and commercially released by VIA Technologies in February 2000 as a Socket 370 processor primarily targeted at low-cost desktop, mobile, and embedded computing applications.[1][2] The initial Cyrix III models were based on the Joshua core, a 0.18-micrometer CMOS design containing approximately 22 million transistors, which integrated a 64 KB unified L1 cache, a 256 KB on-die L2 cache, and support for MMX, 3DNow!, and Pentium Pro instruction set extensions including physical address extension (PAE).[3][4] Available in clock speeds ranging from 500 MHz to 600 MHz with a 100 MHz or 133 MHz front-side bus, the processor operated at core voltages around 2.0 V and was noted for its competitive integer performance in legacy workloads, though it lagged in floating-point and multimedia tasks compared to contemporaries like Intel's Pentium III or AMD's Athlon.[5][6] VIA's acquisition of Cyrix from National Semiconductor in mid-1999 enabled the Cyrix III's launch, marking it as the final processor branded under the Cyrix name before VIA rebranded the lineup to C3 and shifted to the more efficient Samuel core in late 2000, which featured a smaller 11 million transistor count, 128 KB total L1 cache, and no on-die L2 to reduce power consumption for thin-client and appliance markets.[1] Despite initial promise as a budget alternative, the Cyrix III faced challenges from Intel's dominance and compatibility issues, contributing to Cyrix's effective exit from the consumer CPU market by 2001, with production limited to a few thousand units per model.[3][6] Key features of the Cyrix III included integrated power management for mobile use, and compatibility with 440BX chipsets, making it suitable for upgrading older Pentium II systems without a full motherboard replacement.[4] However, thermal and yield issues with the Joshua core prompted VIA's rapid pivot to the Samuel architecture, which improved efficiency but renamed the product line, effectively ending the Cyrix III's short lifecycle amid the intensifying x86 competition in the early 2000s.[1]Development History
Design Origins
Cyrix's processor development began with 486-compatible designs in the early 1990s, such as the Cx486 series, which emphasized cost-effective upgrades for 386 systems while maintaining full x86 compatibility.[7] By the mid-1990s, the company advanced to the 6x86 (M1) and 6x86MX/MII (M II) processors, which introduced superscalar execution and MMX support to compete in the fifth-generation x86 market, focusing on higher instructions-per-cycle efficiency despite lower clock speeds compared to Intel's Pentium.[6] These efforts culminated in the transition to sixth-generation designs, with the Cyrix III representing an evolution toward Pentium III-era architectures, prioritizing x86 compatibility for the emerging Socket 370 platform to enable integration with standard motherboards supporting Intel's Coppermine processors.[4] The design goals for the Cyrix III centered on a superscalar architecture capable of dual-issue execution, incorporating two seven-stage integer pipelines and a dual-issue floating-point unit (FPU) with MMX and 3DNow! extensions, alongside speculative execution supporting up to four levels via a 512-entry branch target buffer for improved branch prediction.[4] This approach aimed to deliver competitive performance in integer and multimedia tasks while targeting low-power embedded systems and value-oriented desktop markets, where power management features like suspend mode, stop clock, sleep, and halt states reduced consumption compared to high-end rivals like the Intel Pentium III and AMD Athlon.[6] The architecture included dual-ported split L1 caches consisting of 64 KB instruction and 64 KB data, and 256 KB L2 cache to enhance efficiency in low-cost scenarios, with a focus on out-of-order completion and parallel instruction queuing for up to four MMX operations.[4] A key pre-acquisition milestone occurred in 1999, when Cyrix internally developed the Joshua core as the foundation for the Cyrix III, featuring approximately 22 million transistors fabricated on a 0.18 μm process for a compact die size of around 100 mm².[8] Derived from the earlier Cayenne core—initially described at the 1997 Microprocessor Forum as an extension of the M II—this design marked Cyrix's shift to a seven-stage superpipelined structure optimized for Socket 370's 133 MHz front-side bus and P6 interface signals.[6] To convey performance without relying solely on clock speeds, Cyrix employed its P-Rating system, which estimated equivalent performance relative to Intel Pentium processors in integer and 2D application benchmarks, rather than direct MHz comparisons. For instance, the Cyrix III-600 was rated as comparable to a Pentium III 600 MHz in integer tasks, despite operating at lower actual clocks (e.g., a PR533 model ran at 433 MHz), highlighting the architecture's higher instructions-per-cycle efficiency in targeted workloads.[4] This system, continued briefly into the Cyrix III era, underscored Cyrix's strategy to position its processors as value alternatives in performance-sensitive but cost-conscious segments.VIA Acquisition and Launch
In 1999, VIA Technologies acquired Cyrix Corporation from National Semiconductor for $167 million, a move announced on June 29 and finalized shortly thereafter, marking VIA's strategic entry into the x86 microprocessor market.[9][10] This acquisition provided VIA with Cyrix's intellectual property, engineering talent, and ongoing CPU designs, enabling the Taiwanese firm—previously focused on low-cost chipsets—to develop integrated processor solutions and challenge Intel's dominance in the budget PC segment.[11][10] VIA's motivations centered on creating affordable x86 alternatives, such as Celeron-like chips, to pair with its motherboard ecosystem and capitalize on the growing demand for cost-effective systems amid Intel's aggressive pricing.[10][11] Development of the Cyrix III, originally initiated under Cyrix's independent efforts, persisted through the acquisition and VIA's parallel purchase of Centaur Technology, but faced significant hurdles from organizational integration and resource reallocation.[6] These challenges, including layoffs at National and the consolidation of design teams, contributed to delays that pushed the processor beyond its initial timeline, missing the peak of the sixth-generation CPU lifecycle.[12][6] By early 2000, VIA had stabilized production using a 0.18-micron process from partners like TSMC, allowing the Cyrix III to proceed toward market entry as a budget-oriented option.[6] VIA launched the Cyrix III in February 2000, introducing initial models based on the Joshua core at clock speeds of 400 MHz (PR500) and 433 MHz (PR533), priced at $84 and $99 in 1,000-unit quantities, respectively.[1][6] Positioned as a low-cost alternative to Intel's Pentium III, the Cyrix III targeted value-driven systems with features like 256 KB L2 cache and compatibility with Socket 370 motherboards, emphasizing power efficiency over high-end performance.[1][10] Volume shipments began in April 2000, though early integration issues with VIA's chipsets limited broader adoption.[6]CPU Core Designs
Joshua Core
The Joshua core served as the foundational design for the initial pre-release versions of the Cyrix III processor, representing Cyrix's attempt to evolve its x86 architecture for the Socket 370 platform. Fabricated using a 0.18 μm CMOS process by National Semiconductor, the core contained approximately 22 million transistors, enabling a compact die while targeting mainstream performance in low-end PCs.[13] This design emphasized superscalar execution with speculative capabilities, allowing for improved instruction throughput compared to prior Cyrix offerings, though it operated at relatively modest clock speeds due to thermal and power constraints.[6] Architecturally, the Joshua core featured out-of-order completion of instructions, where exceptions and writes could occur non-sequentially to enhance efficiency, paired with a 7-stage pipeline for balanced integer processing.[4] Branch prediction was implemented via a 512-entry Branch Target Buffer (BTB), providing moderate accuracy for control flow speculation but limiting overall pipelining depth in branch-heavy workloads. The L1 cache was a unified 64 KiB with 4-way set associativity to support rapid access patterns, paired with a 256 KiB on-die L2 cache, 8-way set-associative, for secondary buffering.[6][4] The core included full MMX support for multimedia acceleration, enabling dual-issue execution of MMX instructions alongside basic 3DNow! extensions licensed from AMD.[6] As a typical Cyrix design, the Joshua core built directly on the 6x86MX/MII lineage, retaining elements like the X-Y integer execution units and a 256-byte L0 scratchpad cache while introducing custom optimizations such as enhanced write-combining buffers and proprietary instruction scheduling for integer-dominant tasks.[14] These Cyrix-specific tweaks delivered strong integer performance in office and legacy applications, often outperforming clock-equivalent competitors in non-floating-point benchmarks. However, the floating-point unit (FPU), while supporting dual-issue execution, remained a relative weak point with limited pipelining depth, resulting in subpar execution in FP-intensive scenarios like 3D graphics rendering.[3][4] To market its capabilities, Cyrix employed a P-Rating system, where, for instance, a 433 MHz Joshua variant was rated as equivalent to a Pentium III 600 in select integer metrics, though real-world FP performance fell short of such claims.[7] Despite these innovations, the Joshua core's high power draw and incomplete optimizations led VIA to pivot toward the more efficient Samuel core shortly after acquisition, marking Joshua's brief role as a transitional design in Cyrix's history.[6]Samuel Core
The Samuel core represented an evolutionary redesign of the Cyrix III architecture, shifting toward greater efficiency by leveraging elements from Centaur Technology's WinChip lineage following VIA's acquisition of both Cyrix and Centaur. Adapted for the Cyrix III line, this in-order execution core featured approximately 11 million transistors and was fabricated on a 0.18 μm CMOS process, enabling a smaller die size of about 75 mm² compared to its predecessor. This design pivot addressed the Joshua core's thermal challenges by prioritizing lower power consumption over complex out-of-order execution, making it suitable for mobile applications while maintaining compatibility with Socket 370 systems.[1][15][6] Key architectural features included dual 64 KiB L1 caches (instruction and data, each 4-way set associative), alongside support for MMX and 3DNow! extensions for multimedia processing. Unlike the Joshua core's floating-point performance limitations, the Samuel core integrated a full-speed FPU derived from Centaur's optimizations. Power efficiency was improved through dynamic voltage scaling and simplified pipeline structures, resulting in typical thermal design power ratings around 16 W at higher clocks, which facilitated better heat management for embedded and portable use—though it lacked an on-chip L2 cache. Post-acquisition integration of Centaur elements also introduced branch prediction enhancements, including a 64-entry, 4-way associative branch target buffer (BTB) alongside multiple branch history tables and a 16-entry return stack, boosting prediction accuracy for conditional jumps without significantly increasing complexity.[16][2][3] The Samuel core debuted in Cyrix III processors in mid-2000, but higher-speed variants at 650-700 MHz were introduced in January 2001, marking the final major update to the line before transitioning to the C3 branding and Samuel 2 iterations. These models operated at front-side bus speeds of 100 MHz with multiplier ratios up to 7x, targeting budget desktop and mobile segments where power savings were paramount.[3][1]Samuel 2 Core
The Samuel 2 core represented the final evolution in the Cyrix III lineup, building on the efficiency foundation of the prior Samuel core with targeted enhancements for improved performance and power efficiency. Fabricated using a 0.15 μm CMOS process by TSMC, it featured approximately 15 million transistors and a compact 52 mm² die size, enabling better clock scaling and lower power consumption compared to its 0.18 μm predecessor.[17][18] A key advancement was the addition of 64 KiB of on-die L2 cache, implemented as a 4-way set-associative, exclusive victim cache operating at full core speed, which significantly boosted data access efficiency for integer and multimedia workloads. The core retained the in-order, 12-stage pipeline architecture but incorporated refinements, including a 6-stage pipeline for the 80-bit floating-point unit (FPU) running at half core speed, allowing for optimized handling of x87 floating-point instructions through reduced latency in common operations. It achieved full compatibility with MMX and AMD 3DNow! extensions, providing robust support for multimedia acceleration without native SSE capabilities.[18][3][19] Released in February 2001 as part of the VIA Cyrix III branding—before the shift to the standalone VIA C3 name—the Samuel 2 debuted at clock speeds of 750 MHz, scaling up to 800 MHz with support for 100 MHz or 133 MHz front-side bus configurations. These models, including variants at 600, 667, 700, and 733 MHz, marked the last Cyrix III core design, with production limited due to VIA's rapid pivot to the subsequent Ezra core amid competitive pressures in the x86 market. The transition to the 0.15 μm process, while enabling higher frequencies, encountered initial yield challenges at TSMC's foundry, contributing to a short production window of under a year.[20][21][22]Models and Production
Model Specifications
The Cyrix III processor family, produced by VIA Technologies following its acquisition of Cyrix, encompassed several models differentiated by core architecture, clock speeds, and front-side bus (FSB) frequencies. These models were designed for Socket 370 compatibility and targeted low-cost desktop systems. The Joshua core models operated at 100 MHz FSB, while subsequent Samuel and Samuel 2 cores supported 133 MHz FSB for improved performance.[2][23] Key models included the Joshua-based variants at 500 MHz (5× multiplier) and 533 MHz (approximately 5.33× multiplier), both with 100 MHz FSB. The Samuel core extended the lineup with 650 MHz (6.5×100 MHz, though some configurations used 133 MHz FSB), 667 MHz (5×133 MHz), and 700 MHz (approximately 5.27×133 MHz) options. The Samuel 2 core, an enhanced iteration, featured higher speeds such as 750 MHz (approximately 5.64×133 MHz) and 800 MHz (6×133 MHz). Additional SKUs, including 550 MHz (5.5×100 MHz), 600 MHz (6×100 MHz or 4.5×133 MHz), and 733 MHz (5.5×133 MHz), were available across cores, often as OEM variants for system integrators. Embedded system variants were limited but included lower-speed Joshua derivatives like the 400 MHz and 450 MHz models, tailored for industrial or thin-client applications with reduced power envelopes.[16][3]| Core | Model Clock Speed (MHz) | FSB (MHz) | Multiplier | Notes |
|---|---|---|---|---|
| Joshua | 500 | 100 | 5× | Base desktop SKU |
| Joshua | 533 | 100 | ~5.33× | Common retail variant |
| Samuel | 650 | 100/133 | 6.5×/~4.88× | Flexible FSB support |
| Samuel | 667 | 133 | 5× | OEM-focused |
| Samuel | 700 | 133 | ~5.27× | High-volume production |
| Samuel 2 | 750 | 133 | ~5.64× | Added L2 cache |
| Samuel 2 | 800 | 133 | 6× | Top-end model |
| Various | 550, 600, 733 | 100/133 | Varies | OEM and embedded SKUs |