Intel 8237
The Intel 8237 is a programmable direct memory access (DMA) controller developed by Intel as a peripheral interface circuit for microprocessor systems, enabling high-speed data transfers between memory and I/O devices without requiring continuous CPU involvement.[1] Part of Intel's MCS-85 family, it includes four independent DMA channels, each with dedicated address registers and byte count capabilities supporting up to 64 KB per transfer, and it requires an external 8-bit address latch for operation.[1] The device supports multiple transfer modes—single, block, demand, and cascade (for expanding beyond four channels)—along with autoinitialization after each transfer and options for address increment or decrement.[1] It also features memory-to-memory transfer capabilities, end-of-process (EOP) signaling, and independent control over request/acknowledge signal polarities.[1] The 8237 gained prominence as a core component in early personal computers, including the original IBM PC (model 5150), where it managed 8-bit "fly-by" DMA operations for peripherals like floppy disk controllers and early sound hardware, limited to a 16 MB address space due to its 8-bit page registers.[2]History
Development Origins
The Intel 8237 DMA controller originated from a design developed by Advanced Micro Devices (AMD) as the Am9517, under a 1976 patent cross-licensing agreement between AMD and Intel that permitted mutual manufacturing and use of each other's processor and peripheral technologies.[3] This collaboration enabled AMD to leverage Intel's microprocessor architectures while providing Intel access to AMD's innovative peripheral designs, fostering compatibility across emerging computing ecosystems in the late 1970s. The Am9517, later adopted and rebranded by Intel as the 8237, was fabricated using N-channel silicon gate MOS technology, reflecting the era's emphasis on efficient, low-power integrated circuits for microprocessor-based systems.[4] Development of the Am9517/8237 was closely aligned with Intel's MCS-85 family (including the 8080 and 8085 microprocessors) and the nascent x86 architecture, such as the 8086 introduced in 1978, to address the growing demand for high-performance input/output operations in single-board computers and early personal systems.[4] At the time, microprocessors like the 8085 were increasingly paired with peripherals requiring rapid data movement, such as floppy disk drives and emerging hard disk storage, where CPU-mediated transfers bottlenecked system performance. The controller's design prioritized direct memory access (DMA) to offload the processor, enabling seamless integration into memory-mapped I/O environments typical of these 8-bit and early 16-bit platforms.[4] Central to the device's architecture were four independent DMA channels, each supporting up to 64 KB transfers via 16-bit address and byte count registers, optimized for 8-bit data paths to match the prevailing bus standards of the period.[4] These features allowed for versatile transfer modes, including demand, block, and single transfers, with expandability through cascading for multi-controller setups, ensuring scalability for high-speed peripherals while maintaining compatibility with NMOS-based systems operating at clock speeds up to 4 MHz.[4] This focus on programmable efficiency marked a significant advancement in peripheral support, directly responding to the limitations of earlier DMA solutions like the Intel 8257.Release and Early Adoption
The Intel 8237, a programmable direct memory access (DMA) controller fabricated using NMOS technology, was released by Intel in 1979 to support efficient data transfers in microprocessor-based systems, with an initial operating clock speed of up to 3 MHz.[5][6] Its design addressed limitations in earlier DMA controllers like the Intel 8257 by introducing features such as memory-to-memory transfer capabilities between channels 0 and 1, enabling up to 64 KB per operation compared to the 8257's 16 KB limit, and providing enhanced programmable control for dynamic reconfiguration during operation.[6][7] The official datasheet for the 8237 was published by Intel in 1980, highlighting these advancements and positioning the device as a high-performance peripheral for improving system throughput in data-intensive applications.[6] Early commercial availability targeted original equipment manufacturers (OEMs), with volume pricing around $25 per unit for the 3 MHz variant in quantities of 100, making it accessible for integration into custom designs.[8] Initial adoption occurred primarily in industrial and embedded systems leveraging the Intel 8086 microprocessor, including data acquisition setups and process control equipment where DMA offloaded the CPU for real-time I/O handling.[9] These applications benefited from the 8237's compatibility with the 8086's 16-bit architecture and its ability to manage four independent channels for peripherals like disk controllers and sensors. AMD released a parallel version, the Am9517, under cross-licensing arrangements around the same period.[4]Architecture
Block Diagram and Key Components
The Intel 8237 is housed in a 40-pin dual in-line package (DIP) fabricated using NMOS technology, designed to operate at a single 5 V supply with a typical power dissipation of up to 1.5 W.[1][5] At its core, the 8237 features four independent DMA channels, each equipped with 16-bit address counters and byte counters capable of handling up to 64 KB transfers, along with a bidirectional 8-bit data bus interface and integrated control logic that facilitates direct data transfers between I/O peripherals and system memory without CPU intervention.[1] The control logic encompasses major functional blocks including a timing control unit for generating internal clocks and external signals, a program command control section for decoding operational instructions, and a priority encoder to manage channel arbitration during concurrent requests.[1] The block diagram of the 8237 illustrates these elements interconnected via internal data paths, with input/output request lines (DREQ0–DREQ3) serving as asynchronous inputs from peripherals to initiate DMA cycles, and corresponding acknowledge signals (DACK0–DACK3) output to grant access and notify devices of active transfers.[1] Address generation is handled through 16-bit address bus drivers, where lower-order bits (A0–A7) are provided directly and higher-order bits are multiplexed over the data bus (DB0–DB7) using external latches for extension to 24-bit addressing in larger memory systems.[1] The chip supports byte and word transfers, as well as verify operations for data integrity checks, with an internal first/last flip-flop that tracks the initial and final cycles of multi-byte transfers to optimize bus usage and signaling.[1] Registers within the channels are briefly referenced for configuring transfer parameters, but their detailed programming is handled separately.[1]Pin Configuration and Interfaces
The Intel 8237 DMA controller is housed in a 40-pin dual in-line package (DIP) and features a pinout designed for integration with microprocessor systems, providing direct control over memory addressing and data transfer during DMA operations. The address interface includes eight pins for the lower address bits: A0–A3 are bidirectional tri-state outputs that serve as inputs during programming cycles and outputs during active DMA cycles, while A4–A7 are dedicated tri-state outputs enabled only during DMA service to provide the upper four bits of the 8-bit on-chip address. To support full 16-bit or 20-bit addressing (as required for systems like the 8086), external page registers latch the upper address bits (A8–A15 or A16–A19), effectively extending the addressing capability to 64 KB per channel without additional pins on the 8237 itself. The data bus consists of eight bidirectional tri-state pins (DB0–DB7) that handle both programming data from the CPU and actual DMA data transfers between memory and peripherals.[1][10] Key control signals facilitate bus arbitration and DMA cycle management. The CLK pin accepts a single-phase clock input, with a maximum frequency of 3 MHz for the standard 8237 and up to 5 MHz for the 8237-2 variant, synchronizing all internal operations. HRQ (hold request) is an output pin that signals the CPU to relinquish the bus, while HLDA (hold acknowledge) is an input pin where the CPU confirms bus release, enabling the 8237 to take control for DMA transfers. DMA channel requests are handled via four input pins (DREQ0–DREQ3), which are asynchronous and prioritized internally (DREQ0 highest), and corresponding output acknowledge pins (DACK0–DACK3), whose polarity is programmable but defaults to active low. Additional control pins include CS (chip select, active low for I/O addressing), RESET (active high to initialize the device), READY (input to extend cycles for slow peripherals), and EOP (bidirectional end-of-process signal for terminating transfers). Memory and I/O operations are controlled by outputs such as MEMR/MEMW (memory read/write, active low) and IOR/IOW (I/O read/write, bidirectional), along with AEN (address enable, active high) and ADSTB (address strobe, active high) for latching external addresses.[6][11][10] The 8237 is electrically compatible with TTL logic levels, with input high voltage (VIH) minimum of 2.0 V, input low voltage (VIL) maximum of 0.8 V, output high voltage (VOH) minimum of 2.4 V at -400 μA, and output low voltage (VOL) maximum of 0.45 V at 8 mA, ensuring seamless integration with TTL-based systems. Timing specifications include a DREQ setup time to CLK low of 0 ns (asynchronous), a READY setup time to CLK low of 100 ns minimum, and hold times of 0 ns for most inputs relative to CLK. Power requirements are +5 V DC (VCC) with ground (VSS), and the device operates over a temperature range of 0°C to 70°C for commercial versions.[1][10] Designed primarily for the 8080/8085 microprocessor bus, the 8237 interfaces with the 8086/8088 via external latches (such as the 8282 or 8283) to handle the multiplexed address/data bus, where address bits are latched during the first T cycle and data is transferred in subsequent cycles. For expansion, the device supports cascading multiple 8237s by connecting the HRQ and HLDA of a master to a slave's DREQ and DACK pins, allowing up to four controllers (16 channels total) while maintaining a single bus interface to the CPU; in this configuration, lower-priority channels on slaves are arbitrated only after master channels are serviced.[1][6][10]| Pin Group | Pins | Type | Function |
|---|---|---|---|
| Address | A0–A3 | I/O (tri-state) | Lower 4 address bits; inputs for register select, outputs during DMA |
| Address | A4–A7 | O (tri-state) | Upper 4 address bits; enabled during DMA service |
| Data | DB0–DB7 | I/O (tri-state) | 8-bit bidirectional data bus for programming and transfers |
| DMA Requests | DREQ0–DREQ3 | I | Asynchronous channel request inputs (prioritized) |
| DMA Acknowledges | DACK0–DACK3 | O | Channel acknowledge outputs (programmable polarity) |
| Bus Control | HRQ | O | Hold request to CPU |
| Bus Control | HLDA | I | Hold acknowledge from CPU |
| Clock/Timing | CLK | I | System clock input (max 3–5 MHz) |
| Other Controls | CS, RESET, READY, EOP, IOR/IOW, MEMR/MEMW, AEN, ADSTB | Mixed | Chip select, reset, ready wait, end-of-process, I/O and memory controls, address enable/strobe |
| Power | VCC, VSS | Supply | +5 V and ground |
Internal Structure
Registers and Programming
The Intel 8237 DMA controller incorporates a set of programmable registers that enable software configuration of transfer parameters, channel selection, and operational modes for its four independent channels. These registers are accessed via the chip's 8-bit bidirectional data bus using I/O read (IOR) and write (IOW) signals, with address lines A0–A3 decoding the specific register (ports 00h–0Fh). Each channel maintains eight 8-bit registers internally: two for the 16-bit current address (CAR), two for the 16-bit current word count (CWCR), two for the 16-bit base address (BAR), and two for the 16-bit base word count (BWCR). The current address and word count registers are directly programmable by the CPU, while the base registers are loaded automatically from the current registers upon the first transfer when auto-initialize is enabled, allowing repeated transfers without CPU intervention.[1][12] Programming the address and count registers requires a preliminary step to manage the first/last flip-flop, which determines whether the low or high byte is accessed. This flip-flop is cleared by writing 00h to the temporary register at port 0Ch, ensuring the subsequent write targets the low byte. For a given channel, the low byte of the current address is then written to the channel's address port (e.g., 00h for channel 0, 02h for channel 1), followed by the high byte to the same port; the process repeats for the count port (e.g., 01h for channel 0). The address value specifies the starting memory or I/O location for the transfer, incrementing or decrementing based on the mode register configuration, while the word count (decremented per transfer, with terminal count signaled at 0000h after FFFFh rollover) defines the number of bytes or words to move. Base registers, though not directly accessible, are software-initiated by loading the current registers prior to enabling auto-initialize.[13][12] The mode register, one per channel and write-only at port 0Bh, configures transfer specifics and is programmed by specifying the channel in bits 0–1 (00b for channel 0, 01b for channel 1, 10b for channel 2, 11b for channel 3). Its 6-bit format (bits 2–7) includes:| Bit | Name | Description |
|---|---|---|
| 7–6 | Transfer Mode | 00b: Demand; 01b: Single; 10b: Block; 11b: Cascade |
| 5 | Addressing | 1b: Decrement (address decreases); 0b: Increment (address increases) |
| 4 | Auto-Initialize | 1b: Enabled (reload from base on terminal count); 0b: Disabled |
| 3–2 | Transfer Type | 00b: Verify; 01b: Write (peripheral to memory); 10b: Read (memory to peripheral); 11b: Illegal |
| Bit | Name | Description |
|---|---|---|
| 0 | M/M | 1b: Enable memory-to-memory transfer (using channels 0 and 1 as source/destination) |
| 1 | CH0 | 1b: Address hold on channel 0 during transfers |
| 2 | D/C | 1b: Disable controller (halts all DMA) |
| 3 | C/T | 1b: Enable compressed timing |
| 4 | F/R | 0b: Fixed priority (channel 0 highest); 1b: Rotating priority |
| 5–7 | - | Reserved |