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Bus mastering

Bus mastering is a capability in computer bus architectures that enables a connected device, known as a bus master, to independently seize control of the system bus to initiate and manage direct memory access (DMA) transactions, allowing data transfers between peripherals and memory without ongoing intervention from the central processing unit (CPU).^[1] This mechanism contrasts with simpler bus systems where only the CPU acts as the master, requiring it to handle all communications and potentially creating bottlenecks.^[2] In operation, a bus master requests control of the bus through a dedicated signal, such as the REQ# line, to a central bus arbiter—often integrated into the host bridge or chipset—which evaluates competing requests and grants access via a GNT# signal, ensuring fair allocation and preventing conflicts among multiple devices.^[1] Once granted, the master can perform burst transfers of multiple data units at high speeds, supporting protocols like those in the PCI bus, where it maintains ownership for sequential operations to optimize throughput up to 133 MB/s in early implementations.^[1] This process includes address and command phases followed by data phases, with features like peer-to-peer communication enabling direct device-to-device interactions without routing through system memory.^[3] The concept traces its roots to early 1970s innovations, such as IBM's System/7, which introduced DMA for I/O devices to offload the CPU, evolving into more sophisticated arbitration in the 1980s with the IBM PC/AT's MASTER signal for single-channel DMA access.^[4] True bus mastering, with hardware-mediated arbitration, preemption, and fairness algorithms, was realized in 1987 with IBM's PS/2 Micro Channel Architecture (MCA), which supported multiple masters and subsystem control blocks for enhanced efficiency.^[4] By the 1990s, Intel's PCI standard popularized it across personal computers, replacing older buses like ISA and EISA by providing plug-and-play compatibility, high bandwidth, and full bus mastering for graphics cards, network adapters, and storage controllers.^[5] Earlier precursors appeared in 1970s minicomputer designs, such as Intel's Multibus and the S-100 bus used in the 1975 Altair 8800, where devices could assert bus control for basic DMA.^[5] Bus mastering remains fundamental to modern architectures like PCI Express (PCIe), where it facilitates high-speed, low-latency transfers in endpoints such as GPUs and SSDs, reducing CPU overhead and enabling scalable system performance in servers, desktops, and embedded devices.^[1] Its advantages include minimized interrupt latency, increased overall throughput, and support for concurrent operations, though it requires robust arbitration to avoid bus contention and ensure system stability.^[3]

Overview

Definition

Bus mastering is a hardware feature in computer bus architectures that enables a peripheral device to seize control of the bus and independently initiate and manage data transfers, thereby reducing the need for continuous oversight by the central processing unit (CPU).^[1] This capability allows the device, known as the bus master, to generate addresses and control signals on the bus, facilitating efficient communication between peripherals and system memory or other devices.^[6] The primary components involved in bus mastering include the bus master, which takes temporary control to drive the bus; bus slaves, which are responsive devices that react to the master's requests by providing or receiving data; and the bus protocol, which governs the handover of mastership through defined signaling mechanisms.^[7] Key terminology encompasses "bus master" for the initiating controller, "bus slave" for the targeted responder, and "master-slave arbitration" for the process that resolves competing access requests to ensure orderly bus usage.^[1] In contrast to traditional CPU-centric bus control, where the processor exclusively drives all addresses and control signals for every transaction, bus mastering empowers non-CPU devices to operate autonomously, offloading the CPU and improving overall system performance.^[6] This feature primarily enables applications such as direct memory access (DMA), where peripherals can transfer data directly to or from memory without CPU intervention.^[7]

Relation to DMA

Direct Memory Access (DMA) is a hardware mechanism that enables peripheral devices to transfer data directly to or from main memory without continuous CPU intervention, thereby improving system efficiency by offloading I/O operations.^[8] Bus mastering serves as the bus-level protocol that empowers these devices to initiate and control such transfers autonomously by temporarily taking over the system bus from the CPU.^[9] This integration allows DMA to function beyond simple controller-mediated transfers, enabling more flexible and performant I/O in modern architectures.^[10] Bus mastering facilitates two primary types of DMA: first-party DMA, where the peripheral device itself acts as the bus master and directly drives the transfer cycles using its onboard logic; and third-party DMA, where a separate system-level DMA controller mediates the process, allocating bus channels while the device provides data but does not control the bus.^[10] In first-party DMA, the device integrates its own DMA engine, allowing it to request and acquire bus control independently, which is common in high-speed peripherals like graphics cards or storage controllers.^[11] Third-party DMA, by contrast, relies on a centralized controller (e.g., on the motherboard), which handles arbitration and transfers on behalf of the device, often limiting performance due to shared resources.^[11] Through bus mastering, DMA extends its capabilities by permitting peripherals—such as hard disk drives or network interfaces—to generate memory addresses and perform reads/writes directly, minimizing CPU cycles compared to programmed I/O (where the CPU handles each byte) or interrupt-driven methods (where the CPU responds to each data event).^[8] This autonomy reduces CPU utilization by up to 30% in disk transfer scenarios, as the processor can execute other instructions while the device manages the bus.^[12] Bus mastering thus transforms DMA from a CPU-assisted process into a device-driven one, enhancing throughput for bandwidth-intensive tasks.^[9] Conceptually, the DMA process under bus mastering follows a sequential flow: the peripheral detects data to transfer and asserts a bus request to the arbiter; upon granting control via bus arbitration, the device becomes the master and addresses memory directly for read/write operations; once the transfer completes, it releases the bus and signals the CPU via interrupt if needed.^[9] This cycle—request, acquisition, access, and release—ensures efficient resource sharing without halting the CPU entirely.^[13]

History

Early Developments

The concept of bus mastering originated in the mainframe and minicomputer eras of the 1960s and 1970s, where specialized I/O controllers managed data transfers independently of the central processor to improve system efficiency. In IBM's System/360 family, introduced in 1964, I/O channels acted as dedicated processors for handling input/output operations, performing data transfers to/from main memory after CPU initiation, providing early direct memory access (DMA) capabilities without constant CPU involvement during the transfer. These channels, such as byte-multiplexer and selector types, allowed multiple devices to share access while the CPU focused on computation, marking a shift from CPU-bound I/O in prior systems.^[14] The introduction of direct memory access (DMA) controllers further advanced these ideas by enabling peripheral devices to seize bus control for transfers, a direct precursor to full bus mastering. The Intel 8257 DMA controller, released in 1976 as part of the 8085 microprocessor ecosystem, provided programmable channels for high-speed I/O-to-memory operations, allowing third-party devices to temporarily master the system bus and bypass CPU involvement. This innovation addressed bottlenecks in early microcomputer designs, where CPU-mediated transfers limited performance for tasks like disk or tape operations. Bus mastering thus built on DMA to extend control beyond dedicated controllers to general peripherals.^[15] Early bus architectures in the 1970s began incorporating explicit support for device-initiated transfers, enabling limited bus mastering in microcomputer systems. The S-100 bus, developed in 1974 for the Altair 8800, included master/slave arbitration signals that permitted DMA-capable cards to take control for data movement, fostering expandability in hobbyist and small-scale computing.^[16] Similarly, Intel's Multibus, introduced in 1976, standardized a parallel interface with bus arbitration logic, allowing multiple masters—including DMA controllers and coprocessors—to request and hold bus ownership for efficient inter-board communication in industrial and OEM applications.^[17] A key milestone occurred with the transition from CPU-dominated control in 8-bit microcomputer systems to shared bus management in emerging 16-bit designs, enabling more complex arbitration and higher throughput. While 8-bit buses like the original S-100 prioritized simple CPU-centric access, 16-bit extensions and architectures such as Multibus supported wider data paths and concurrent masters, laying groundwork for scalable I/O in professional computing.^[18] This evolution reflected growing demands for multitasking and peripheral autonomy in the late 1970s.^[1]

Adoption in Personal Computers

The adoption of bus mastering in personal computers began with the introduction of the Industry Standard Architecture (ISA) bus alongside the IBM PC in 1981, though initial implementations were limited to basic direct memory access (DMA) capabilities managed by the system's DMA controller.^[19] Enhanced support for bus mastering peripherals emerged with the IBM PC/AT in 1984, allowing compatible adapters to request and gain control of the bus for independent data transfers, thereby offloading the CPU during I/O operations.^[20] This feature proved essential for early high-performance peripherals, such as SCSI host adapters, which required efficient handling of large data volumes without constant CPU intervention.^[21] In 1987, IBM introduced the PS/2 line with Micro Channel Architecture (MCA), which provided true bus mastering through hardware-mediated arbitration, preemption, and fairness algorithms, supporting multiple masters and subsystem control blocks for enhanced efficiency. However, its proprietary design and licensing fees limited widespread adoption beyond IBM systems.^[4] The primary drivers for bus mastering's integration into PCs during the late 1980s were the growing demands for high-speed input/output in emerging applications like multimedia processing and local area networking. For instance, the Extended Industry Standard Architecture (EISA) bus, introduced in 1988 by a consortium of seven PC manufacturers, extended ISA to 32 bits and improved bus mastering to support up to 4 GB of memory addressing, facilitating faster peripherals such as SCSI controllers for hard drives and tape backups.^[22] Early Ethernet adapters, like National Semiconductor's SONIC-based EISA bus master cards, leveraged this capability to perform DMA transfers directly to system memory, enabling reliable network performance in multitasking environments without overburdening the processor.^[23] These advancements addressed bottlenecks in data-intensive tasks, such as file sharing over networks or audio/video buffering, which were becoming prevalent with the rise of graphical user interfaces. In the 1990s, the Peripheral Component Interconnect (PCI) bus, specified by Intel in June 1992, marked a pivotal shift by standardizing bus mastering across a plug-and-play architecture that supported multiple masters with centralized arbitration.^[24] This enabled widespread adoption in consumer PCs, particularly with the proliferation of Windows 95 and OS/2 Warp, which included native support for PCI bus-mastering drivers to manage device initialization and resource allocation.^[25] By the mid-1990s, operating systems like Windows provided optimized drivers for bus-mastering IDE controllers, such as the Triones drivers for Intel's PIIX chipsets released in 1995, significantly reducing CPU utilization during disk I/O in multitasking scenarios and improving overall system responsiveness.^[26]

Technical Operation

Bus Arbitration

Bus arbitration is the process by which multiple potential bus masters compete for control of a shared system bus, ensuring that only one device can initiate transfers at a time to avoid conflicts and maintain orderly operation in bus mastering environments.^[27] This mechanism is essential for enabling direct memory access (DMA) controllers or other peripherals to take over from the CPU without system crashes or data corruption. In bus mastering, the arbitration resolves requests from devices seeking to become the active master, determining which one gains temporary control based on predefined rules.^[28] There are two primary types of bus arbitration: centralized and distributed. In centralized arbitration, a single dedicated arbiter—such as the CPU or a separate controller—manages all requests and grants bus access, evaluating competing claims and assigning priority through a unified decision process.^[29] This approach simplifies hardware design but can introduce bottlenecks if the arbiter becomes overwhelmed. Examples include daisy-chaining, where devices are linked in a serial fashion to propagate grant signals, with fixed priority based on position in the chain. In contrast, distributed arbitration allows all connected devices to participate directly in the resolution, using schemes such as self-selection where each device places a unique ID on shared arbitration lines to determine priority without a central authority.^[30] Distributed methods promote scalability in multi-master systems but require more complex wiring and signaling to ensure synchronization.^[31] Key signals facilitate the arbitration handshake between requesters and the bus controller. Devices typically assert a Request signal (often denoted as REQ# in active-low protocols) to indicate their need for bus control, prompting the arbiter to evaluate and respond with a Grant signal (GNT#) to the selected master.^[32] In early microprocessor-based systems, such as those using the Intel 8086, the external master asserts the HOLD signal to request control, to which the processor responds with HLDA (Hold Acknowledge) at the end of its current bus cycle, tri-stating its outputs to relinquish control and allow the new master to drive the lines.^[33] These signals ensure a clean transition of bus ownership, with the granting process often including a brief idle period to stabilize the bus. Priority resolution schemes determine which requester wins during contention, balancing efficiency and equity. Fixed priority assigns static ranks to devices—e.g., the CPU or critical DMA controllers always outrank peripherals—to minimize latency for high-importance tasks, though this risks bus starvation for lower-priority devices if higher ones dominate.^[1] Rotating priority, also known as round-robin, cyclically shifts the order of precedence after each grant, ensuring fairer access and preventing indefinite delays for any single requester.^[32] Fair arbitration extends this by incorporating time-based or request-history mechanisms to explicitly avoid starvation, guaranteeing that every active device eventually gains access within a bounded timeframe.^[34] Latency in bus arbitration refers to the delay from a device's request assertion to receiving the grant, influenced by factors like the number of contenders and the scheme employed. This period typically includes evaluation time by the arbiter plus turnaround cycles—idle clock periods needed for address and control lines to settle after the previous master releases them, often 1-2 cycles in synchronous systems to prevent signal contention.^[34] High contention can extend this latency to several bus cycles, impacting overall system throughput, though efficient schemes like independent request-grant lines in centralized setups can reduce it to under one cycle in low-load scenarios. Once granted, the master proceeds to initiate data transfers, but arbitration overhead remains a key factor in bus mastering performance.

Data Transfer Process

Once bus control has been granted through the arbitration process, a bus master initiates a data transfer cycle by entering the address phase, during which it drives the target memory or I/O address onto the address bus and asserts control signals specifying the operation type, such as memory read, memory write, I/O read, or I/O write.^[24] The data phase immediately follows, enabling the actual transfer of information between the master and the target device. In a read operation, the bus master has already provided the address and now waits for the target to decode it and drive the requested data onto the data bus; the master samples this data upon receiving an acknowledgment from the target. For a write operation, the bus master supplies both the address (from the prior phase) and the write data onto the data bus, with the target latching the information once ready; some bus architectures incorporate parity bits or error detection mechanisms during this phase to verify data integrity.^[24]^[35] To enhance efficiency, especially for sequential accesses, bus masters support burst modes consisting of a single address phase followed by multiple consecutive data phases, transferring several words without reasserting the address each time. In cache-based systems, these burst transfers incorporate coherency handling, where the bus master or supporting hardware monitors or invalidates relevant cache lines to prevent stale data inconsistencies across multiple processors or devices.^[24]^[36] Each phase concludes with termination signals from the target, such as a ready indicator (e.g., RDY# in legacy buses or TRDY# in more advanced designs) to signal successful completion of the data transfer, or a stop signal for error conditions like invalid addresses, ensuring the operation remains atomic and the bus is released promptly by the master.^[24]^[37]

Implementations

In ISA and EISA

Bus mastering in the Industry Standard Architecture (ISA) bus was implemented optionally through direct memory access (DMA) channels managed by controllers like the Intel 8237, which provided four channels per controller (channels 0-3 for 8-bit transfers and 5-7 for 16-bit, with channel 4 used for cascading between controllers).^[38] These channels allowed peripherals to request bus control, but the process relied on third-party DMA mode, where the CPU had to actively relinquish the bus by responding to a HOLD request with HLDA (hold acknowledge), introducing significant involvement and potential delays from the processor.^[38] The ISA bus operated at a maximum clock speed of 8 MHz, limiting transfer rates to approximately 5 MB/s theoretically for 16-bit operations, though real-world performance was often lower due to overhead.^[38] ISA bus mastering suffered from compatibility issues, particularly in systems where the bus ran in half-speed mode—such as 4 MHz when the system clock was 8 MHz—to accommodate slower peripherals or 8-bit slots, creating bottlenecks that reduced overall throughput and made it unsuitable for high-performance data transfers.^[38] This mode was common to ensure reliability with legacy hardware, but it exacerbated latency during master operations, as the CPU's involvement in arbitration could lead to contention and inefficient resource sharing.^[38] The Extended Industry Standard Architecture (EISA) addressed many ISA limitations by introducing native 32-bit addressing, enabling access to up to 4 GB of memory through signals like A[31:0] and byte enables BE#[3:0].^[38] EISA supported dedicated master/slave modes with request (MREQx#) and grant (MAKx#) lines for arbitration, managed by a Central Arbitration Control block, allowing up to 15 concurrent bus masters including the CPU, DMA controllers, and peripherals.^[38] This setup used a rotational priority scheme, configurable via jumper settings on the motherboard or expansion cards to assign levels and ensure fair access, with preemption possible within 64 bus clock cycles (approximately 8 µs at standard speeds).^[38] In practice, EISA bus mastering enabled peripherals like tape drives to operate as intelligent masters, performing high-speed burst-mode transfers directly to memory without constant CPU intervention, improving efficiency for storage devices in 1980s personal computers.^[38] Slaves in EISA indicated their data path width via signals such as EX16# or EX32#, ensuring compatibility with ISA cards while leveraging the enhanced architecture for 32-bit operations.^[38]

In PCI and PCIe

Bus mastering in PCI, introduced by the PCI Special Interest Group in 1992, enables peripheral devices to take control of the bus to perform direct memory access (DMA) transfers, improving system efficiency by offloading the CPU. The PCI specification defines a parallel bus architecture operating at 33 MHz with 32-bit or optional 64-bit data widths, supporting burst transfers of up to 256 bytes to minimize latency during high-volume data movements. Arbitration is handled centrally by the host bridge using four dedicated request (REQ#) and grant (GNT#) signal pairs per bus segment, allowing up to four concurrent masters; this point-to-point signaling ensures fair access through priority or round-robin algorithms, with the bus master asserting FRAME# to initiate transactions after receiving a grant.^[24] PCIe, evolving from PCI since its initial specification in 2003, replaces the parallel shared bus with high-speed serial point-to-point links, scaling from x1 to x32 lanes and supporting data rates up to 64 GT/s per lane in PCIe 6.0 (specification finalized in 2022, with initial products launching as of 2025) for greater bandwidth.^[39] Bus mastering in PCIe occurs through the transaction layer, where devices generate transaction layer packets (TLPs) to request memory reads/writes, I/O operations, or configuration accesses, encapsulated with headers defining the transaction type, address, and length (up to 4 KB per TLP). Virtual channels enhance quality of service by providing multiple logical paths over the physical link, enabling prioritized traffic flow via credit-based flow control to prevent congestion during mastering operations.^[40] Key optimizations in PCIe include posted writes, where write TLPs are fire-and-forget without requiring acknowledgments, reducing overhead for bulk data transfers, and the ability to disable interrupts during active mastering to avoid CPU intervention. PCIe also integrates support for Input-Output Memory Management Units (IOMMUs), which translate device virtual addresses to physical ones, enhancing security by isolating DMA accesses from unauthorized memory regions. For instance, graphics cards employ PCIe bus mastering for GPU DMA to stream textures and frame buffers directly to system memory at rates exceeding 16 GB/s on x16 links, while NVMe SSD controllers use it for high-bandwidth command queuing and data transfers, achieving sequential read speeds over 7 GB/s in modern implementations.^[40]^[41]

In Other Architectures

Bus mastering extends beyond PC-centric architectures to various embedded, industrial, and specialized systems, where it enables efficient data movement in resource-constrained or multi-device environments. In the ARM Advanced Microcontroller Bus Architecture (AMBA), particularly the AXI protocol, bus mastering is implemented through master interfaces that allow system-on-chip (SoC) components, such as GPUs and DMA controllers, to initiate transactions independently of the central processor. The AXI4 specification supports multiple concurrent masters with features like out-of-order transaction completion and burst transfers, optimizing high-bandwidth interconnects in mobile and embedded processors. In storage and peripheral interfaces like USB and SATA, host controllers employ bus mastering to perform direct memory access (DMA) operations, offloading the CPU during data transfers. For SATA, the Advanced Host Controller Interface (AHCI) enables the controller to act as a bus master on the system bus while managing multiple devices; notably, AHCI supports port multipliers that extend connectivity to additional drives, allowing the controller to arbitrate and master transfers across the multiplier topology without CPU intervention. Similarly, USB host controllers in embedded systems use bus mastering for DMA to handle bulk data from devices like sensors or storage, ensuring low-latency communication in real-time applications. Industrial and embedded architectures from earlier decades also incorporated bus mastering for robust multi-device coordination. The VMEbus, introduced in the 1980s, features a multi-master design with centralized arbitration using daisy-chain signals to grant bus ownership, supporting real-time systems in aerospace and scientific instrumentation where predictable latency is critical.^[42] In Apple's Macintosh systems, the NuBus employed cooperative bus mastering, where masters request control via synchronous arbitration and can extend tenure through bus locks, allowing shared access to multiport memories without aggressive contention, which facilitated expansion cards in compact computing environments. Modern variants of bus mastering appear in Internet of Things (IoT) devices, where extensions to low-speed buses like I2C and SPI integrate DMA capabilities for efficient sensor data handling. In microcontrollers such as those from STM32 families, I2C and SPI peripherals can trigger DMA transfers, enabling peripherals to master the system bus for autonomous data movement from sensors to memory, reducing CPU overhead in battery-powered nodes. This approach supports multi-master arbitration in I2C for conflict resolution during concurrent sensor reads, enhancing scalability in distributed IoT networks.^[43]

Advantages and Challenges

Benefits

Bus mastering provides significant CPU offloading by allowing peripheral devices to initiate and manage data transfers directly to and from system memory, thereby freeing the central processing unit from repetitive I/O handling and enabling it to focus on computational tasks. This offloading leads to overall system throughput improvements in I/O-intensive workloads, such as disk transfers, compared to programmed I/O methods.^[12] Direct memory access enabled by bus mastering minimizes latency through reduced interrupt overhead and streamlined data paths, as devices bypass the CPU for transfers, resulting in smoother real-time applications like uninterrupted video streaming or audio processing without frame drops or buffering delays. For instance, in graphics or multimedia systems, bus mastering ensures timely data delivery to display buffers, preventing performance bottlenecks in high-resolution playback scenarios.^[9]^[12] In multi-device environments, bus mastering enhances scalability by supporting concurrent I/O operations across multiple peripherals, which is particularly valuable in server architectures handling diverse workloads like database queries and network servicing simultaneously. This concurrency allows systems to maintain efficiency as device counts increase, without proportionally burdening the CPU, thereby supporting robust multitasking in enterprise settings.^[12]^[4] Bus mastering optimizes bandwidth efficiency through features like burst modes, where devices can transfer large data blocks in rapid succession to saturate available bus capacity, which is essential for high-throughput networking applications such as 1 Gbps Ethernet adapters that stream packets directly into memory to achieve full link speeds. In these scenarios, the mechanism ensures maximal utilization of bus resources, doubling effective transfer rates on 64-bit buses compared to narrower architectures, without unnecessary CPU intervention.^[12]^[44]

Limitations and Issues

Bus mastering introduces significant design complexity due to the need for sophisticated hardware to manage arbitration among multiple masters, which can lead to increased costs and higher power consumption in system implementations. In multi-master environments, this complexity heightens the risk of deadlocks, where devices are unable to proceed because each is waiting for resources held by another, necessitating advanced avoidance mechanisms such as rearbitration protocols in bus architectures like CoreConnect.^[45] Compatibility challenges arise particularly in legacy systems, where bus mastering devices may conflict with interrupt request (IRQ) sharing limitations; for instance, ISA bus devices generally require unique IRQs and cannot share them if simultaneous use is possible, leading to resource contention and installation difficulties. Additionally, bus mastering enables direct memory access (DMA), which poses security risks by allowing peripherals to read or write arbitrary memory locations without CPU mediation, potentially enabling data theft or malware injection; these vulnerabilities are mitigated in modern systems through Input-Output Memory Management Units (IOMMUs) that enforce address translation and access controls.^[46]^[47] In low-load scenarios involving small data transfers, the overhead of bus mastering can outweigh its benefits, as the arbitration latency—often spanning several clock cycles to grant bus control—results in poorer performance compared to simpler CPU-polling methods, which avoid such delays for frequent, minor operations.^[48] Error handling in bus mastering systems presents further issues, including the management of bus errors like master or target aborts, which require software intervention to detect, log, and recover from faults such as invalid addresses or timeouts. Coherency problems also emerge in cached environments, where DMA transfers bypass caches, necessitating explicit software actions like cache invalidation or flushing to ensure data consistency across bus masters and processors, thereby adding to programming complexity and potential for errors if not properly implemented.^[49]

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[PDF] Interfacing bus, Protocols, ISA bus etc. - Cloudfront.net
It starts with a bus request to the CPU and after it is granted it takes over the address/data and control bus to initiate the data transfer. After the data ...Missing: termination | Show results with:termination
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[PDF] EISA System Architecture - ece.ufrgs
EISA Bus Master Handshake Lines ... The EISA specification defines a new set of bus cycle definition signal lines. The current EISA bus master uses them to ...
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[PDF] PCI Express® Basics & Background
Jun 23, 2015 · Request are translated to one of four transaction types by the Transaction Layer: 1. Memory Read or Memory Write. Used to transfer data from or ...
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[PDF] Using IOMMU for DMA Protection in UEFI Firmware - Intel
If PCI BME is used, bus mastering must be disabled at the root bridge for the entire duration critical early processing until the platform security ...
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VMEbus Arbitration - VITA
Sep 19, 1999 · The VMEbus is a shared resource, each master must be granted the bus so that no two masters can drive the bus at the same time. This is called bus arbitration.
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[PDF] I²C Master Mode - Microchip Technology
The I2C interface allows for a multi-master bus, meaning that there can be several master devices present on one bus. A master can select a slave device by ...
[46]
[PDF] Design and Evaluation of FPGA-based Gigabit Ethernet/PCI ...
bus. The bus is required to provide enough bandwidth at 1Gbps rate for receive and transmit transfers in DMA channels and Gigabit Ethernet interface.
[47]
[PDF] The CoreConnect™ Bus Architecture
Deadlock avoidance through slave forced PLB rearbitration. •. Master driven atomic operations through a bus arbitration locking mechanism. •. Byte-enable ...
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1.3.1.1. ISA interrupts versus PCI interrupts - PC Hardware in a ...
For ISA slots and devices, the rule is simple: two devices cannot share an IRQ if there is any possibility that those two devices may be used simultaneously. In ...
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[PDF] Thunderbolt: Exposure and Mitigation - cs.wisc.edu
In this study, we explored a number of vulnerabilities ex- posed by the presence of a Thunderbolt interface within a system, including well-known attacks such ...Missing: risks | Show results with:risks
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[PDF] Bus Arbitration & Mastery Network type busses I/O architectur
All communication between the bus and the device (send data, receive data, status and control) is performed by reading from, and writing to these registers. I/O ...Missing: concurrent | Show results with:concurrent
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[PDF] Using the i.MXRT L1 Cache - NXP Semiconductors
Then eDMA transfers the data to SAI FIFO is incorrect, and the data coherency problem occurs. To avoid such data coherency issue, here're some solutions: 1.<|control11|><|separator|>