Socket 370
Socket 370, also known as PGA370, is a 370-pin zero insertion force (ZIF) CPU socket developed by Intel for connecting processors to motherboards using a pin grid array (PGA) configuration.[1] Introduced in 1998 as a cost-effective alternative to the Slot 1 interface, it initially supported plastic pin grid array (PPGA) packaging for Intel Celeron processors (Mendocino core) before expanding to flip-chip pin grid array (FC-PGA) for Coppermine-core processors in 1999 and FC-PGA2 formats for Tualatin-core chips in 2001.[2] The socket facilitated Intel's transition to more affordable desktop and entry-level systems during the late 1990s and early 2000s, serving as the primary interface for consumer and value-oriented computing until the advent of Socket 478 in 2001.[1] It supports front-side bus (FSB) speeds ranging from 66 MHz to 133 MHz, with core voltages ranging from 1.45 V to 2.0 V depending on the processor model, and a maximum thermal design power of approximately 30 watts.[1][2] Compatible processors include the Intel Celeron (Mendocino, Coppermine, and Tualatin cores) and Pentium III (Coppermine and Tualatin cores), with clock speeds from 300 MHz up to 1.4 GHz; third-party options like VIA Cyrix III and VIA C3 were also supported on compatible motherboards.[2] Key features encompass the AGTL+ signaling protocol for efficient bus communication, integrated thermal monitoring via a diode on the processor, and compatibility with chipsets such as Intel 440BX, 815, and VIA Apollo Pro series, enabling dual-processor configurations in some workstation setups.[1] Despite its limitations—such as the absence of hyper-threading, multi-core support, or native overclocking—Socket 370 played a pivotal role in popularizing advanced features like Streaming SIMD Extensions (SSE) in mainstream PCs.[1]Introduction
Definition and Overview
Socket 370, also known as PGA370, is a 370-pin Pin Grid Array (PGA) CPU socket developed by Intel for mounting desktop processors directly onto motherboards.[1] It supports Pin Grid Array (PGA) package interfaces, including Flip-Chip PGA (FC-PGA) and Plastic PGA (PPGA), enabling electrical and mechanical connection through pins on the underside of the processor package.[1] The primary purpose of Socket 370 was to provide a cost-efficient alternative to the Slot 1 cartridge-based design, particularly for budget and mainstream systems by eliminating the need for additional packaging components.[3] This direct socket mounting simplified assembly and reduced manufacturing expenses while maintaining compatibility with Intel's processor architecture.[3][1] At its core, Socket 370 operates using a Zero Insertion Force (ZIF) lever mechanism, which allows processors to be installed and removed without applying force to the pins, minimizing damage risk.[1] It primarily supports single-processor configurations, though some motherboards enabled dual-processor setups, with a staggered pin layout that ensures proper orientation and prevents incorrect insertion.[1] The socket measures approximately 50 mm × 50 mm, accommodating the processor package dimensions of about 49.5 mm × 49.5 mm.[1] It was introduced for processors such as the Pentium III and Celeron families.[1]Historical Development
Socket 370 was introduced by Intel in 1998 as a cost-effective replacement for the Slot 1 interface used in Pentium II processors.[4] The socket's development was driven by the need to lower manufacturing expenses for budget-oriented systems, transitioning from the more complex cartridge-based Slot 1 design to a simpler Pin Grid Array (PGA) package that reduced material costs and streamlined motherboard production. This shift aligned with the surging demand for affordable personal computers during the late 1990s economic expansion, enabling broader market penetration for entry-level desktops.[5] The first implementations of Socket 370 appeared in early 1999, coinciding with the adoption of Mendocino-core Celeron processors, which marked Intel's initial deployment of on-die L2 cache in a low-end offering. By late 1999, the socket expanded to support Pentium III Coppermine processors operating at 100/133 MHz front-side bus speeds, solidifying its role as Intel's primary desktop interface for mainstream systems. In 2001, revisions to Socket 370 accommodated the Tualatin-core variants of both Celeron and Pentium III, extending compatibility through minor pinout adjustments without requiring entirely new sockets.[6] Socket 370's lifecycle concluded around 2001-2002, as Intel phased out production in favor of Socket 478 for the Pentium 4 architecture, reflecting the end of the P6 microprocessor era.[5] Emerging amid the PC industry's rapid growth in the late 1990s, the socket positioned Intel competitively against AMD's Socket A platform, which debuted in 2000 and targeted similar mid-range segments with enhanced performance features.Technical Specifications
Physical Characteristics
Socket 370 employs a 370-pin configuration arranged in a staggered grid layout, facilitating compatibility with pin grid array (PGA) processor packages. This includes approximately 200 signal pins for data transfer and control functions, 74-75 pins for VCC core power, 74-77 pins for VSS ground, 15-20 pins for VTT termination voltage, and a small number of reserved or no-connect pins to accommodate future expansions or manufacturing tolerances. To prevent incorrect installation, the socket incorporates alignment keys at positions A1 and AN1, which act as plugs that mate with corresponding notches on the processor package, ensuring proper orientation.[7] The socket's construction utilizes a durable plastic body to house the pin array, with gold-plated contacts providing low-resistance electrical connectivity and corrosion resistance. A zero insertion force (ZIF) lever-operated clamp secures the processor without bending pins, allowing for repeated installations during assembly or upgrades. This design supports high reliability in desktop motherboard environments.[1][8] Physically, the socket measures approximately 49.5 mm by 49.5 mm, matching the footprint of earlier sockets like Socket 7 while adding pins for advanced signaling. It integrates seamlessly into motherboard layouts via through-hole mounting, and is compatible with standard retention mechanisms, such as those used in Intel's boxed processor coolers, which employ mounting holes for secure attachment and heat sink support.[1] Early iterations of Socket 370 were optimized for plastic pin grid array (PPGA) packages, as seen in initial Celeron processors, emphasizing cost-effective manufacturing. Subsequent revisions adapted to flip-chip pin grid array (FC-PGA) packages, incorporating an integrated heat spreader on the processor side to enhance thermal dissipation while maintaining the same socket interface. These evolutions ensured backward compatibility across processor generations without altering the core physical structure.[1]Electrical and Interface Details
Socket 370 provides electrical support for a range of core voltages (VCC) tailored to compatible processors, typically spanning 1.1 V to 1.7 V, with specific implementations varying by generation: early Mendocino-core Celerons operate at up to 2.0 V, while Coppermine and Tualatin models use 1.20 V to 1.76 V as defined by the processor's VID pins.[1] The socket also requires a termination voltage (VTT) of 1.25 V ±9% for AGTL signaling in Tualatin processors or 1.50 V ±9% for AGTL+ in earlier models, ensuring proper signal integrity on the system bus.[9] This voltage flexibility allows the socket to accommodate Intel's evolving P6-based architectures without requiring hardware modifications to the interface. The bus architecture employs a 64-bit data path (D[63:0]#) synchronized to the Front Side Bus (FSB), which operates at official speeds of 66 MHz, 100 MHz, or 133 MHz, though many motherboards enable compatibility with 150 MHz via overclocking configurations.[1] Data integrity is maintained through parity checking mechanisms, including address parity (AP[1:0]#) and data error-checking pins (DEP[7:0]#) that support error-correcting code (ECC) for reliable transfers.[9] Signaling follows the AGTL+ (Advanced GTL+) standard for the majority of Socket 370 implementations, which uses open-drain drivers with external pull-up resistors to VTT, reducing power consumption and electromagnetic interference compared to earlier GTL protocols.[1] Power delivery is optimized through a distributed array of pins—approximately 74-75 for VCC core and 74-77 for VSS ground, interspersed across the 370-pin grid—to minimize voltage droop and inductive noise during high-frequency operations.[9] Maximum power dissipation reaches up to 37.5 W for high-end processors like the 1.13 GHz Pentium III, with dedicated low-pass filtering required for phase-locked loop (PLL) supplies to ensure stable clock generation.[1] Interface protocols inherit P6 architecture features, including the Advanced Programmable Interrupt Controller (APIC) via signals like LINT[1:0], PICCLK, and PICD[1:0] for multi-processor interrupt handling.[9] Thermal monitoring is facilitated by dedicated DI (THERMDN) and DTS (THERMDP) pins connected to an on-die thermal diode, enabling external sensors to measure junction temperature and trigger protective mechanisms like THERMTRIP#.[1]Processor Compatibility
Supported Processor Families
Socket 370 primarily supported Intel's entry-level Celeron processors and mainstream Pentium III processors, both derived from the P6 microarchitecture, providing binary compatibility with earlier Intel x86 processors such as the Pentium II.[1] These families evolved through multiple cores, enhancing performance via on-die L2 cache integration and support for advanced instruction sets.[10] The Celeron family, positioned as budget-oriented processors, began with the Mendocino core in 1998, featuring clock speeds from 300 MHz to 533 MHz, a 66 MHz front-side bus (FSB), and 128 KB of on-die L2 cache at full core speed, marking a shift from off-die cache designs in prior models.[11] Subsequent Coppermine-128 variants, introduced in 2000, utilized a 0.18-micron process and extended speeds up to 1.1 GHz, retaining the 128 KB L2 cache while supporting 66 MHz and 100 MHz FSB options for improved memory bandwidth in compatible systems.[12] The Tualatin-core Celeron processors, released in 2001 on a 0.13-micron process, offered clock speeds from 1.0 GHz to 1.4 GHz with 256 KB L2 cache and 100 MHz FSB support, providing further efficiency improvements for entry-level systems.[13] The Pentium III family served as the high-performance counterpart, starting with the Coppermine core in 1999, which offered clock speeds from 500 MHz to 1.13 GHz, 256 KB of on-die L2 cache, and FSB support at 100 MHz or 133 MHz to enable higher data throughput.[1] Later Tualatin-core models, released in 2001 and fabricated on a 0.13-micron process, pushed speeds up to 1.4 GHz with 512 KB L2 cache, maintaining 100 MHz and 133 MHz FSB compatibility while incorporating enhancements for better efficiency.[14] All Socket 370 processors were based on the P6 microarchitecture, which emphasized dynamic execution with out-of-order processing and a superscalar design for improved instruction-level parallelism, ensuring seamless execution of legacy x86 software.[1] Later iterations, particularly from the Coppermine core onward, integrated over 70 Streaming SIMD Extensions (SSE) instructions to accelerate vectorized floating-point and multimedia operations. The following table summarizes key compatibility details for clock speeds and FSB support across these families:| Processor Family | Core | Clock Speed Range | L2 Cache | FSB Support |
|---|---|---|---|---|
| Celeron | Mendocino | 300–533 MHz | 128 KB | 66 MHz |
| Celeron | Coppermine-128 | 533 MHz–1.1 GHz | 128 KB | 66/100 MHz |
| Celeron | Tualatin | 1.0–1.4 GHz | 256 KB | 100 MHz |
| Pentium III | Coppermine | 500 MHz–1.13 GHz | 256 KB | 100/133 MHz |
| Pentium III | Tualatin | 1.0–1.4 GHz | 512 KB | 100/133 MHz |