Altera
Altera Corporation is a global semiconductor company specializing in the design and manufacture of programmable logic devices (PLDs), with a primary focus on field-programmable gate arrays (FPGAs) and system-on-chip (SoC) FPGAs that enable customizable, high-performance computing solutions for applications including artificial intelligence, cloud infrastructure, networking, and edge devices.[1][2] Founded in 1983 by engineers including Rodney Smith, Jim Sansbury, and Paul Newhagen with initial seed funding of $500,000, the company was established in San Jose, California, to address the growing need for flexible digital logic in electronics.[3][2] Altera reincorporated in Delaware in 1997 and rapidly became a leader in the PLD market through innovations like its MAX and FLEX device families, expanding into high-density FPGAs such as the Stratix and Arria series.[2][3] In December 2015, Intel Corporation acquired Altera for approximately $16.7 billion in its largest acquisition to date, integrating it as the Intel Programmable Solutions Group (PSG) to bolster Intel's offerings in data center acceleration and embedded systems.[4] Under Intel, Altera advanced its portfolio with Agilex FPGAs optimized for AI and 5G, while maintaining a strong emphasis on software tools like Quartus Prime for design and deployment.[5] In February 2024, Intel relaunched Altera as a dedicated standalone business unit to prioritize FPGA innovation and customer focus in emerging technologies.[5] By April 2025, Intel announced a strategic divestiture, selling a 51% stake in Altera to Silver Lake Partners for a total valuation of $8.75 billion, granting Altera operational independence while retaining Intel as a minority shareholder and key technology partner.[6] The transaction closed in September 2025, positioning Altera as the world's largest pure-play FPGA solutions provider and enabling accelerated growth in AI-driven markets, with first-half 2025 revenue reaching $816 million—a 16% increase year-over-year.[7][8] Under new CEO Raghib Hussain, appointed effective May 2025, Altera continues to emphasize scalable, power-efficient devices and an open FPGA stack to support developers in cloud-to-edge deployments.[9][10]History
Founding and early development
Altera Corporation was founded in June 1983 in San Jose, California, by four semiconductor engineers: Robert "Bob" Hartmann, James "Jim" Sansbury, Paul Newhagen, and Michael Magranet.[11] These founders, with prior experience at companies including Fairchild Semiconductor, Signetics, and Hewlett-Packard, aimed to develop user-programmable gate arrays as flexible alternatives to fixed gate array designs in the semiconductor industry.[12] The company outsourced manufacturing to foundries like Ricoh while focusing on design and innovation in programmable logic.[11] The initial team secured $500,000 in seed funding to launch operations.[3] Rodney Smith, a British applications engineer from Fairchild, joined shortly after as the first CEO to lead commercialization efforts.[12] By late 1983, the team completed the design of their debut product, and in 1984, Altera released the EP300, a 20-pin CMOS programmable logic device (PLD) that was the world's first UV-erasable and field-reprogrammable chip, replacing less flexible bipolar PAL devices from competitors like AMD and Monolithic Memories Inc.[11] Building on this success, Altera expanded its portfolio in the mid-1980s with larger complex PLDs (CPLDs) such as the EP1200 and EP600 families, targeting applications in telecommunications, data communications, and industrial controls.[11] In 1988, the company introduced the MAX architecture, enabling devices with up to 5,000 gates operating at 40 MHz, and went public through an initial public offering priced at $5.50 per share, raising capital amid a recovering market after a 1987 downturn.[11][13] That year, sales reached $38 million, reflecting rapid adoption of Altera's reprogrammable logic solutions in high-performance computing and embedded systems.[14] By 1990, the company had invested in fabrication capacity by acquiring a minority stake in Cypress Semiconductor's facility and expanded internationally, with Japan accounting for 15% of its business.[14]Product innovation and growth
Following its founding in 1983, Altera rapidly advanced programmable logic technology, introducing the EP300 in 1984 as the industry's first ultraviolet-erasable programmable logic device (PLD), which served as a direct replacement for bipolar PALs and enabled faster design iterations in applications like telecommunications and computing peripherals.[11] This innovation was followed by the EP1200 and EP600 families, expanding device complexity and density, which helped Altera establish itself as a fabless semiconductor leader by partnering with Ricoh as its initial foundry.[11] By 1988, the company launched the MAX architecture, featuring erasable programmable logic devices (EPLDs) with up to 5,000 gates and 40 MHz operating speeds, targeting high-volume markets such as office automation and industrial controls; this series drove sales to $38 million that year.[3] In the early 1990s, Altera shifted toward field-programmable gate arrays (FPGAs) with the FLEX 8000 family introduced in 1992, incorporating logic elements (LEs) based on four-input look-up tables (LUTs) organized into logic array blocks for enhanced routability and performance in data processing tasks.[15] The MAX 7000 series, launched in 1991, further scaled to 4,000–40,000 gates, contributing to revenue growth from $106.9 million in 1991 to $140.3 million in 1993, while the 1994 acquisition of Intel's PLD business for $50 million bolstered Altera's portfolio with the MAX 9000 (up to 80 MHz) and propelled sales toward $200 million.[3] By 1995, the FLEX 10000 family exceeded 100,000 gates, supporting complex system-on-chip designs and fueling a revenue surge to $401.6 million, as Altera captured significant market share in telecommunications and military applications.[3] The late 1990s and 2000s marked Altera's maturation into a high-performance FPGA provider, with the 2000 Excalibur series integrating ARM processors with programmable logic via AMBA-AXI interconnects for embedded systems innovation.[15] The Stratix family debuted in 2002, expanding logic array blocks to 10 LEs with improved memory and routing for data center uses, followed by Stratix II in 2004 introducing adaptive logic modules (ALMs) that doubled LUT and flip-flop density per block.[15] Subsequent releases like Stratix IV (2008) and Stratix V (2011) enhanced arithmetic modes and interconnects, enabling applications in high-speed networking and video processing; these advancements, alongside mid-range Cyclone and Arria families for cost-sensitive sectors, supported quarterly revenue growth, such as a 31% year-over-year increase to $215.1 million in Q3 1999 and 16.5% to $491.5 million in Q2 2014.[16][17] By the mid-2010s, Altera's focus on power-efficient, scalable FPGAs positioned it as a leader in emerging fields like 5G and AI inference, with annual revenues approaching $2 billion prior to its 2015 acquisition by Intel.[18]| Product Family | Launch Year | Key Innovation | Market Impact |
|---|---|---|---|
| MAX Series | 1988 | EPLDs with 5,000 gates, 40 MHz speeds | Enabled high-volume adoption in industrial and telecom; sales to $38M in 1988[3] |
| FLEX Series | 1992 | LUT-based LEs in logic array blocks | Shift to FPGA density >100,000 gates by 1995; revenue to $401.6M[15][3] |
| Stratix Series | 2002 | ALMs with expanded routing and memory | High-performance for data centers; contributed to revenue growth in networking and video processing applications[15][16] |
Financial restatement
In June 2006, Altera Corporation announced that it would restate its financial statements for fiscal years 1996 through 2005, covering 40 consecutive quarters, due to errors in the accounting for stock-based compensation expenses.[19] The discrepancies primarily involved incorrect measurement dates for stock option grants issued between December 1996 and March 2001, stemming from an internal review prompted by broader scrutiny of stock option practices in the semiconductor industry.[20] This issue rendered the company's previously issued financial statements for those periods unreliable, leading to the formation of a special committee, supported by independent legal and accounting experts, to investigate the matter.[19] The restatement was expected to result in additional non-cash charges totaling $38 million to $48 million on a pre-tax basis, with approximately $18 million related to the stock option grants themselves and $20 million to $30 million attributed to modifications in employees' stock option agreements.[21] No material impact was anticipated for the fiscal year ended December 30, 2005, and historical revenue figures remained unaffected.[21] Altera also identified a material weakness in its internal controls over financial reporting as of December 30, 2005, which contributed to the delays in filing its annual and quarterly reports.[19] By October 2006, the special committee completed its investigation, confirming the need for the restatement and quantifying the cumulative pre-tax charge at $47.6 million.[22] The company filed the restated financials with the U.S. Securities and Exchange Commission shortly thereafter, resolving the immediate compliance issues and allowing Altera to regain full Nasdaq listing status.[23] This event occurred amid a wave of similar stock option investigations across corporate America, but it did not lead to charges against current executives and had no lasting effect on Altera's ongoing operations or market position.[24]Products and technologies
Field-programmable gate arrays (FPGAs)
Altera's field-programmable gate arrays (FPGAs) represent a cornerstone of its product portfolio, offering reconfigurable semiconductor devices that allow users to implement custom hardware acceleration for applications ranging from telecommunications to data centers. Founded on SRAM-based programmable logic, Altera's FPGAs evolved from early programmable logic devices (PLDs) to sophisticated architectures integrating embedded processors, high-speed interfaces, and AI accelerators. The company's first FPGA, the FLEX 8000 family introduced in 1992, featured a fine-grained architecture with logic array blocks (LABs) comprising 16 logic elements (LEs) each, enabling flexible implementation of combinational and sequential logic while supporting up to 16,000 gates in larger devices.[11][25] Subsequent generations built on this foundation by incorporating embedded resources to reduce external components and enhance performance. The FLEX 10K family, launched in 1995, introduced embedded array blocks (EABs) for on-chip memory, allowing up to 6,700 logic elements and supporting synchronous designs with deterministic timing. This was followed by the APEX II family in 2001, which added embedded multipliers for digital signal processing (DSP) tasks, achieving up to 89,000 logic elements and clock speeds exceeding 300 MHz. By the mid-2000s, Altera segmented its offerings into tiered families: the high-performance Stratix series (debuting in 2002 with up to 79,000 logic elements and 500 MHz performance), the mid-range Arria series (introduced in 2007 for cost-effective high-bandwidth applications), and the low-cost Cyclone series (launched in 2004, optimized for power efficiency with up to 114,000 elements in Cyclone IV).[3] These families adopted a hierarchical structure with LABs, interconnects, and dedicated I/O blocks, emphasizing scalability and integration of transceivers for serial protocols like PCI Express.[26] In the 2010s, Altera advanced to finer process nodes and hybrid architectures, culminating in the Stratix 10 family in 2016, the industry's first 14 nm FPGA with HyperFlex architecture using adaptive logic modules (ALMs) that combine multiple LEs for up to 2.8 times higher density than prior generations, alongside 58 Gbps transceivers and integrated HBM memory support. The Arria 10 (2015) and Cyclone 10 (2016) followed, incorporating hard IP for floating-point DSP and low-power features, with Cyclone 10 LP variants achieving up to 63% lower power than predecessors for embedded applications. Post-acquisition by Intel in 2015 and subsequent spin-off in 2025, Altera introduced the Agilex series starting in 2019, featuring 10 nm and 7 nm processes with in-package HBM2e integration and PCIe 5.0 support; the Agilex 7, for instance, delivers up to 116 Gbps transceiver speeds and 4 million LEs for AI and networking workloads.[7][27] The MAX 10 family (2014), a non-volatile FPGA with flash-based configuration, provides instant-on capability and analog features like ADCs for compact industrial designs. Altera's FPGA innovations prioritize modularity and efficiency, with common architectural elements including configurable logic blocks, distributed RAM, and DSP slices for compute-intensive tasks. For example, modern devices like Agilex 5 (2023) integrate AI tensor blocks for machine learning acceleration, achieving up to 42% lower power than prior mid-range offerings while supporting DDR5 memory.[28] These advancements have enabled applications in 5G infrastructure, autonomous vehicles, and cloud computing, where FPGAs provide low-latency reconfiguration superior to fixed ASICs.[29]| Family | Introduction Year | Target Segment | Key Features |
|---|---|---|---|
| FLEX 8000 | 1992 | Entry-level | Up to 16K gates, LAB-based architecture with LEs[25] |
| Stratix 10 | 2016 | High-end | 14 nm, HyperFlex ALMs, 58 Gbps transceivers, HBM support |
| Arria 10 | 2015 | Mid-range | Hard DSP with floating-point, 28 Gbps transceivers |
| Cyclone 10 | 2016 | Low-cost | Low power (up to 63% reduction), integrated PCI Express |
| Agilex 7 | 2023 | High-performance | 7 nm, 116 Gbps PAM4, PCIe 5.0, up to 4M LEs[27] |
| MAX 10 | 2014 | Non-volatile | Flash configuration, ADCs, up to 50K LEs |
System-on-chip FPGAs
Altera's System-on-Chip (SoC) FPGAs integrate programmable logic fabric with hard-embedded processor subsystems on a single die, enabling seamless hardware-software co-design for embedded applications. This architecture combines the reconfigurability of FPGAs with the computational efficiency of processors, reducing system complexity, power consumption, and board space compared to discrete components. The processor subsystems typically feature ARM-based cores, peripherals, and memory controllers, interconnected with the FPGA fabric via high-speed interfaces like the Advanced eXtensible Interface (AXI).[30][31] Altera introduced its first SoC FPGA with the Cyclone V family in December 2012, marking a pivotal evolution in programmable logic by embedding a dual-core ARM Cortex-A9 MPCore processor system alongside 28 nm FPGA fabric optimized for low power and cost. This device supported transceiver speeds up to 6.144 Gbps and targeted edge applications requiring efficient logic, DSP, and connectivity. Subsequent generations advanced process nodes and core counts: the Arria 10 SoC, launched in 2015 on 20 nm technology, featured a dual-core ARM Cortex-A9 hard processor subsystem (HPS) with up to 48 full-duplex transceivers at 17.4 Gbps, delivering over a speed grade's improvement in core performance for mid-range bandwidth-intensive tasks. The Stratix 10 SoC, introduced in 2017 at 14 nm, upgraded to a quad-core ARM Cortex-A53 processor, HyperFlex architecture, and variants supporting PCIe 4.0 x16 and up to 28.3 Gbps transceivers, emphasizing high-density integration for demanding systems.[32][33][34] The Agilex family represents Altera's latest SoC advancements, built on Intel's 10 nm and 7 nm processes for superior performance-per-watt. Agilex 7 SoC devices, available since 2023, incorporate a quad-core ARM Cortex-A53 across F-, I-, and M-series variants, with logic elements ranging from 573k to 3.8M and transceivers up to 116 Gbps; the M-series further supports HBM2e memory up to 32 GB and Compute Express Link (CXL) for processor offload. Agilex 5 and 3 SoCs extend this to mid- and cost-optimized segments, offering up to 2x fabric performance per watt versus prior 7 nm competitors and features like 12.5 Gbps transceivers for compact designs. These evolutions prioritize heterogeneous computing, with integrated DSP blocks and AI accelerators enhancing scalability. Following the 2025 spin-off, Altera expanded the Agilex portfolio in September 2025 with production availability of all families, including enhanced SoC variants for AI and edge applications.[35][36][37] Altera SoC FPGAs excel in applications demanding real-time processing and adaptability, such as industrial automation, wireless infrastructure, automotive systems, and data center acceleration. In networking and edge computing, they enable low-latency packet processing and protocol handling; defense and broadcast leverage high-bandwidth I/O for secure, reliable operations. Advantages include up to 20% higher fMAX performance in core logic, reduced latency through direct fabric-processor communication, and lower total power via monolithic integration, making them ideal for AI inference at the edge and hardware-accelerated filtering in embedded vision systems.[38][39][40]Intellectual property cores
Altera provides a broad portfolio of intellectual property (IP) cores tailored for integration into its field-programmable gate arrays (FPGAs) and system-on-chip (SoC) devices, encompassing both soft IP—synthesizable register-transfer level (RTL) designs that allow customization across device families—and hard IP, which are fixed, silicon-optimized blocks for superior performance and power efficiency.[41][42] These cores are developed internally by Altera and in collaboration with strategic partners to ensure compatibility and optimization with Altera architectures, enabling designers to accelerate development of complex systems such as telecommunications equipment, data centers, and automotive applications.[43] The IP cores are integrated into the design flow through the Quartus Prime software's IP Catalog, where users can parameterize variations for specific throughput, latency, and resource requirements before generating HDL files for synthesis.[43] Licensing models vary, with many foundational cores available at no cost for evaluation and production, while advanced or partner-provided options require paid licenses to support commercial deployment.[42] This approach has historically included the MegaCore program, launched in the early 2000s, which standardized parameterized IP delivery for communications and networking markets.[44] Altera's IP portfolio is organized into several key categories, prioritizing high-impact functions for modern FPGA applications. Interface protocol IP supports high-speed connectivity standards, with examples including the PCI Express (PCIe) core for endpoint and root complex configurations up to Gen5 speeds, enabling seamless integration with host processors in computing and storage systems; the Ethernet IP suite for 1G to 400G rates, optimized for low-latency packet processing in routers and switches; and the RapidIO IP for serial interconnects in embedded multiprocessing environments.[41][45][46][47] Memory controller IP facilitates access to external DRAM and SRAM, such as DDR4/LPDDR4 controllers supporting data rates over 3.2 Gbps per pin and QDR IV SRAM interfaces for ultra-low latency caching in high-throughput designs.[41][48] In the digital signal processing (DSP) category, Altera offers parameterizable blocks like the Fast Fourier Transform (FFT) core, which implements radix-2 or mixed-radix algorithms for up to 65,536 points with throughput exceeding 1 GSPS in advanced devices, and multiplier-accumulator (MAC) functions leveraging embedded DSP slices for efficient filtering in wireless base stations.[49][50] Video and image processing IP includes the Serial Digital Interface (SDI) core compliant with SMPTE standards for 3G/12G broadcast video transport, and DisplayPort cores supporting multi-stream transport up to 8K resolutions for AV interfaces.[51][52][48] Security IP provides hardened cryptographic accelerators, such as AES-GCM engines and random number generators, to meet compliance requirements like FIPS 140-2 in secure boot and data protection scenarios.[41] These IP cores emphasize configurability to balance area, speed, and power, with simulation models and reference designs available to verify functionality early in the design cycle.[42] By focusing on widely adopted standards and high-performance implementations, Altera's IP reduces engineering effort, allowing developers to concentrate on application-specific logic rather than foundational blocks.[43]Soft processor cores
Altera's soft processor cores enable the implementation of embedded processing capabilities directly within the programmable logic fabric of their field-programmable gate arrays (FPGAs), facilitating the creation of customizable system-on-chip (SoC) designs. These cores are synthesized from hardware description languages like Verilog or VHDL, allowing designers to tailor processor features to specific application needs without dedicated hard processor silicon. The primary offering in this category is the Nios II family, a configurable 32-bit reduced instruction set computing (RISC) processor architecture optimized for Altera FPGAs.[53][54] The Nios II architecture employs a Harvard memory model with separate instruction and data paths, supporting up to 32 general-purpose registers and a variable instruction set that can include extensions for multiplication, division, bit manipulation, and custom instructions to accelerate domain-specific tasks. Key features include optional tightly coupled memory for low-latency access, dynamic branch prediction in higher-end variants, and support for memory protection units (MPU) or full memory management units (MMU) to enable operating systems like Linux. Integration occurs via Altera's Platform Designer tool (formerly SOPC Builder), which allows the processor to connect with peripherals, on-chip memory, and external interfaces in a single FPGA design. The Nios II family includes three core variants—economy (/e), standard (/s), and fast (/f)—each balancing trade-offs in performance, resource consumption, and configurability for diverse embedded applications. The Nios II/e core prioritizes minimal logic element (LE) usage with a single-cycle arithmetic logic unit (ALU) and no pipeline, making it ideal for simple control tasks; it consumes around 500–600 LEs in typical implementations and delivers 0.107 Dhrystone MIPS per MHz (DMIPS/MHz). The Nios II/s core introduces a five-stage pipeline, optional instruction and data caches, and more addressing modes for moderate-performance needs, using approximately 1,200–1,800 LEs while achieving higher throughput than the /e variant, though specific DMIPS/MHz figures vary by configuration. The Nios II/f core maximizes speed with a six-stage pipeline, advanced branch prediction, and the fullest set of optional features like a hardware multiplier and divider, targeting compute-intensive applications; it utilizes 2,000–3,000 LEs and reaches up to 0.753 DMIPS/MHz, with absolute performance scaling to over 200 DMIPS at clock speeds exceeding 250 MHz on modern Altera devices.[55][56][57] These cores support bare-metal programming, real-time operating systems (RTOS) such as FreeRTOS, and full Linux distributions, with debugging facilitated by the Nios II Software Build Tools for Eclipse (SBT). Performance benchmarks, such as CoreMark scores of 229/MHz for the /f core versus 19/MHz for the /e, underscore their scalability across Altera FPGA families like Cyclone and Stratix. By 2021, Intel announced the transition to the Nios V RISC-V-based soft core as a successor, but Nios II remains supported for legacy designs on Altera-era devices.[55][58]Design software
Quartus Prime is Altera's flagship design software suite, providing a multiplatform development environment for implementing digital logic designs on FPGAs, SoC FPGAs, and CPLDs. It encompasses tools for HDL synthesis, placement and routing, static timing analysis, power and thermal estimation, and in-system debugging, enabling engineers to compile, simulate, and program devices throughout the design lifecycle. The software supports hardware description languages such as Verilog, SystemVerilog, and VHDL, and integrates with third-party simulators like Questa from Siemens EDA.[59][60] Available in Lite, Standard, and Pro editions, Quartus Prime caters to varying project scales and device complexities, with the Lite edition being free for entry-level use, Standard for broader legacy support, and Pro for advanced high-performance applications. The editions differ in device support, advanced features, and integration capabilities, as summarized below:| Feature/Aspect | Lite Edition | Standard Edition | Pro Edition |
|---|---|---|---|
| Key Tools | Design entry, synthesis, place-and-route, timing/power analysis, basic simulation (Questa Starter Edition), Signal Tap Logic Analyzer | All Lite tools plus partial reconfiguration, design partitioning, Logic Lock regions, transceiver toolkit, multiprocessor support | All Standard tools plus block-based design, interface planner, register retiming, advanced partial reconfiguration |
| Supported Devices | Cyclone 10 LP, Cyclone V/IV, Arria II (limited), MAX 10/V/II CPLDs | Arria 10/V/II, Cyclone 10 LP/V/IV/GX, Stratix V/IV, MAX 10/V/II CPLDs | Agilex portfolio, Stratix 10, Arria 10, Cyclone 10 GX (plus legacy) |
| IP Support | Base IP suite (basic cores for interfaces, processors) | Base IP suite | Base IP suite plus advanced IP for high-speed transceivers and SoCs |
| Simulation | Questa Intel FPGA Starter Edition | Questa Intel FPGA Edition (free with license) | Questa Intel FPGA Edition |
| Limitations | No partial reconfiguration or advanced debugging; limited device density | No block-based flows or high-end optimization for newest devices | Full feature set; requires subscription for production use |
| Licensing | Free, no time limit | Subscription-based, includes legacy device support | Subscription-based, optimized for latest Agilex and Stratix devices |