Dram
A dram is a unit of mass equal to one-sixteenth of an avoirdupois ounce, or 27.34375 grains (approximately 1.772 grams). In the apothecaries' system, it traditionally represents both a mass of 60 grains (3.888 grams) and a volume known as the fluid dram, equivalent to one-eighth of a U.S. fluid ounce (approximately 3.697 milliliters). Originating from the ancient Greek drachmē (meaning "handful"), the term evolved through Latin and Old French to denote small quantities in medieval trade, pharmacy, and coinage before standardization in English-speaking systems. Though largely obsolete for scientific use in favor of metric units, the dram persists informally for measuring minute amounts, particularly a "wee dram" of whisky or spirits in Scottish and literary contexts.[1][1]Dynamic random-access memory
History and invention
Robert Heath Dennard, an engineer at IBM, invented the single-transistor dynamic random-access memory (DRAM) cell in 1967, patenting a design that stored each bit using one transistor and one capacitor to achieve higher density and lower cost compared to prevailing magnetic core memory systems.[2][3] The innovation stemmed from the need to scale memory economically using metal-oxide-semiconductor (MOS) technology, addressing limitations in static RAM and core memory's manual assembly and power demands.[4] IBM filed the patent application in 1967, with issuance in 1968, but delayed commercialization due to immature MOS fabrication processes at the time.[5] Intel released the first commercially successful DRAM chip, the 1103, in October 1970—a 1-kilobit device fabricated in PMOS technology that undercut magnetic core memory in price and size, selling initially at about 21 cents per bit.[6][7] This marked the transition to semiconductor dominance in mainframe and minicomputer memory, enabling denser integration without the labor-intensive wiring of cores.[8] Subsequent generations followed rapid density doublings aligned with shrinking process nodes, from 10-micrometer features in early chips to sub-micrometer scales by the mid-1980s, embodying Moore's Law in memory scaling. Texas Instruments led with the 4-kilobit DRAM in 1973, followed by Mostek's 16-kilobit in 1976, while Japanese firms like NEC and Hitachi accelerated progress with 64-kilobit devices around 1979 and 256-kilobit by 1983.[9][10] Competition intensified as Intel, Texas Instruments, and emerging Japanese manufacturers invested heavily in fabrication capacity, driving 1-megabit DRAM commercialization by 1984–1985 and reducing costs through yield improvements and volume production.[11][12] This rivalry, particularly Japan's focus on process refinement, propelled DRAM from niche to ubiquitous, supplanting alternatives by the early 1980s.[13]Fundamental operation and engineering
The basic memory cell in dynamic random-access memory (DRAM) consists of a single access transistor connected to a storage capacitor, forming a one-transistor, one-capacitor (1T1C) structure. A binary '1' is represented by storing a charge on the capacitor, while a '0' corresponds to an uncharged state; the transistor acts as a switch to isolate the capacitor from the bit line during standby.[14] Due to inherent leakage currents across the capacitor's dielectric and through semiconductor junctions, the stored charge decays exponentially, requiring periodic refresh operations to read and rewrite the data before loss, typically every 64 milliseconds as specified by JEDEC standards for retention at operating temperatures.[15] This volatility contrasts with static RAM (SRAM), which employs multi-transistor flip-flop circuits to maintain state without refresh or capacitors, but at the expense of larger cell size—typically six transistors per bit—resulting in DRAM's superior density for bulk storage.[16] Reading a bit involves activating the corresponding word line to turn on the access transistor, allowing charge sharing between the capacitor and the precharged bit line, which produces a small voltage differential of tens of millivolts across a pair of complementary bit lines.[17] A sense amplifier then detects and amplifies this differential—often around 100 mV in practice—to full logic levels (e.g., near supply voltage versus ground), enabling data output while restoring the cell charge destructively, as the read operation partially discharges the capacitor. Writing mirrors this process in reverse: the sense amplifier drives the bit line to the desired voltage, which transfers charge to or from the capacitor via the activated transistor. Random access is achieved through row decoders selecting word lines for entire rows (thousands of cells) and column multiplexers routing specific bit lines to sense amplifiers, allowing efficient addressing in a two-dimensional array without sequential scanning.[14] Key engineering challenges arise from scaling the cell footprint below 10-20 F² equivalents (where F is the minimum feature size), as shrinking the capacitor reduces stored charge (typically 10-50 fC), exacerbating signal-to-noise ratios during sensing and accelerating leakage-limited retention times. Early designs used trench capacitors etched into the silicon substrate for subsurface volume, but modern implementations favor stacked (or cylinder) capacitors built atop the transistor array to maximize height and surface area within planar constraints, often exceeding aspect ratios of 50:1.[18] Leakage is mitigated by adopting high-k dielectrics such as zirconium dioxide (ZrO₂) or hafnium oxide (HfO₂) in metal-insulator-metal stacks, which permit thinner effective oxide thicknesses for equivalent capacitance while suppressing tunneling currents compared to traditional silicon dioxide.[18] These materials enable capacitance densities over 50 fF/μm² but introduce trade-offs in thermal stability and interface defects, contributing to refresh overhead that consumes 1-10% of system power and generates localized heating.[17] DRAM's design yields densities 4-6 times higher than SRAM per bit, translating to costs roughly one-fourth to one-tenth that of SRAM equivalents, which underpins its dominance in main memory by facilitating terabit-scale modules despite slower access latencies (tens of nanoseconds versus SRAM's single-digit) and refresh-induced stalls.[16] This cost-density advantage stems from the minimal 1T1C footprint versus SRAM's 6T, but causal limits include amplified read/write energies from charge pumping and vulnerability to soft errors from alpha particles or cosmic rays, necessitating error-correcting codes for reliability.[14]Generations and variants
Asynchronous DRAM variants, including Fast Page Mode (FPM) and Extended Data Out (EDO), prevailed from the 1980s through the early 1990s, relying on independent control signals untethered to the system clock, which constrained access speeds to around 60-70 ns and introduced latency bottlenecks in pipelined operations.[19] These addressed early density needs in personal computers but faltered against rising processor frequencies, prompting a shift to clock-synchronized designs.[20] Synchronous DRAM (SDRAM), standardized in 1996 under JEDEC with initial speeds up to 133 MHz, synchronized row and column accesses to the system clock, enabling burst modes that transferred multiple words per access cycle and boosted effective throughput by up to 2-3 times over asynchronous types without altering core cell physics.[21] Double Data Rate SDRAM (DDR SDRAM), released in 2000, further enhanced this by capturing data on both clock edges, achieving data rates up to 400 MT/s in DDR1 while halving the required clock frequency for equivalent bandwidth, thus mitigating power and signal integrity issues in denser modules.[22] Successive DDR generations refined these principles: DDR2 (2003) introduced prefetch buffers for 4-bit bursts and on-die termination to reduce reflections, reaching 800 MT/s; DDR3 (2007) lowered voltage to 1.5 V and added fly-by topology for better signal skew, scaling to 1866 MT/s; DDR4 (2014) dropped to 1.2 V with bank groups for parallel access, supporting densities up to 16 Gb per die and speeds to 3200 MT/s.[23] DDR5, launched in 2020, incorporates dual 32-bit channels per module, on-die error-correcting code (ECC) for reliability in high-density setups (up to 64 Gb per die), and decision feedback equalization for signals exceeding 4800 MT/s initially, targeting bandwidth bottlenecks in data-intensive tasks.[24][25] Low-Power DDR (LPDDR) variants, evolving from LPDDR2 (2009) to LPDDR5X (2021), prioritize energy efficiency with voltages as low as 0.5-1.1 V and dynamic voltage scaling, achieving 6400-8533 MT/s for mobile processors while curbing leakage in always-on devices, though at marginally lower densities than standard DDR.[23] Graphics-oriented GDDR, such as GDDR6 (2018), delivers peak speeds of 14-18 GT/s via wider buses and error correction tailored for frame buffers, trading higher power draw (1.35-1.5 V) for sustained bandwidth in rendering pipelines exceeding 500 GB/s per module.[26] High Bandwidth Memory (HBM), first commercialized in 2013 with HBM1 at 1 Tb/s per stack, stacks multiple DRAM dies vertically using through-silicon vias (TSVs) for inter-die links, yielding 2-4x the bandwidth density of GDDR at lower voltages (1.2 V) and addressing thermal and pin-count limits in accelerators via logic-base integration.[27] DRAM densities have progressed from 1 Gb chips dominant in the early 2000s to 64 Gb+ by 2025, propelled by extreme ultraviolet (EUV) lithography for sub-10 nm nodes that enable tighter capacitor spacing and reduced variability without proportional power hikes.[28][29]Manufacturing processes and challenges
DRAM manufacturing begins with silicon wafer preparation, followed by repeated cycles of thin-film deposition, photolithography for patterning, etching to remove unwanted material, and ion implantation for doping to form n-type and p-type regions in access transistors and capacitors.[30] These steps construct the core 1T-1C cell structure, where trenches or stacked capacitors store charge and FinFET or gate-all-around (GAA) transistors control access, with processes iterated over 1000 times per wafer to achieve densities exceeding 20 Gb/mm² at sub-10nm-class nodes by 2025.[31][32] Samsung has introduced vertical channel transistors (VCT) in its first-generation sub-10nm DRAM processes to enable further scaling beyond planar limits.[33] The industry is dominated by three firms—SK Hynix (38% market share in Q2 2025), Samsung (33%), and Micron (22%)—with production concentrated in South Korea and the United States, heightening vulnerability to regional disruptions such as natural disasters or geopolitical tensions that affect equipment, chemicals, or wafer supplies from Japan and Taiwan.[34] The 2011 Tōhoku earthquake exemplified this, causing global supply chain shocks through halted production of intermediates like photoresists and silicon ingots, leading to DRAM price surges of over 200% within months as inventories depleted.[35] Key challenges include escalating defect densities at advanced nodes, where particle contamination or lithography misalignment can render entire dies unusable, necessitating yields below 80% and extensive error-correcting code (ECC) integration to mitigate rising bit error rates from charge leakage or alpha particle strikes.[36] On-die ECC in DDR5 modules corrects single-bit errors internally, but uncorrectable multi-bit failures still occur in 1-2% of high-density chips under field stress, driving additional system-level redundancy.[37] Fabrication facilities cost $10-20 billion to build and equip, with R&D expenditures amplifying unit economics amid cyclical overcapacity, where excess supply during demand lulls triggers price collapses of 50-70% every 2-3 years, eroding margins despite AI-driven booms.[38][39] Periodic refresh operations to retain data further contribute 10-20% of DRAM's total power draw in data centers, exacerbating energy demands as capacities scale.[40]Applications, market dominance, and economic impact
DRAM constitutes the core volatile memory component in personal computers, servers, and smartphones, enabling high-speed data access critical for operating system execution, application multitasking, and processing intensive workloads such as artificial intelligence inference and training. In 2025, typical configurations feature 16-64 GB DDR5 modules in consumer PCs and high-end smartphones to handle multitasking and emerging augmented reality applications, while enterprise servers deploy capacities exceeding 128 GB per system to support cloud-scale data analytics and machine learning models.[41][42][43] The global DRAM market reached $115.89 billion in revenue in 2024, with projections for $121.83 billion in 2025, driven primarily by surging demand from AI data centers and consumer electronics. Market dominance is concentrated among three firms: SK Hynix captured 36% share in the first half of 2025, surpassing Samsung's 34% for the first time since 1992, while Micron holds the remainder in a highly oligopolistic structure favoring scale and capital-intensive fabrication.[44][45][46] Pricing cycles reflect supply-demand imbalances, with shortages inflating contract prices by up to 100% or more during peaks—such as the 2018 memory boom—and oversupply in early 2023 leading to sales below production costs amid inventory buildup of 31 weeks. By mid-2025, AI-fueled demand has reversed this, tightening inventories to eight weeks and driving quarterly price hikes of 13-18% for PC DRAM, underscoring DRAM's role as a bottleneck in compute scaling.[47][48][49] Economically, DRAM has been a foundational enabler of the personal computing era and Moore's Law extensions by allowing exponential growth in accessible data volumes, powering innovations from desktop productivity to hyperscale AI infrastructure projected to require trillions in data center investments. However, its inherent volatility—data loss upon power interruption—exposes systems to reliability risks in edge and persistent workloads, spurring alternatives like Intel's 3D XPoint-based Optane, which promised non-volatility but was discontinued in 2022 after failing to achieve viable economics or ecosystem adoption.[41][50][51] Geopolitical tensions, particularly U.S. export controls on Huawei since 2019, have disrupted DRAM supply chains by restricting advanced chip flows to China, exacerbating shortages and highlighting vulnerabilities in Asia-dominated production where state subsidies enable overcapacity but crowd out unsubsidized Western innovation. These dynamics have prompted U.S. firms like Micron to capitalize on restricted markets, yet risk retaliatory measures that could fragment global supply.[52][53][54]Dram as a unit of measurement
Avoirdupois dram for mass
The avoirdupois dram (dr avdp) is a unit of mass defined as one-sixteenth of an avoirdupois ounce, equivalent to exactly 27 11/32 grains (27.34375 grains).[55] This corresponds to approximately 1.772 grams, with the precise value derived from the international avoirdupois pound of 453.59237 grams divided by 256.[55][56] The unit forms part of the avoirdupois weight system, which employs 16 drams per ounce and 16 ounces (256 drams total) per pound of 7,000 grains, distinguishing it from finer systems like troy weights used for precious metals, where a troy dram equals 1/8 troy ounce or 60 grains.[55][57] Originating from the medieval English adaptation of earlier European weighing practices around the 13th century, the avoirdupois dram supported commerce in commodities such as spices, fabrics, and non-precious metals, reflecting a practical standardization for bulk goods under the term "avoir de pois" (goods by weight).[57][58] The name "dram" traces to the Latin dragma and Greek drachmē, denoting a handful's approximate weight, which evolved into a standardized coin and measure in ancient trade before integration into imperial systems.[56] Unlike the apothecaries' dram (60 grains, tied to medicinal preparations), the avoirdupois variant emphasized coarser, everyday mass quantification without overlap into volume or pharmaceutical contexts.[55] In the United States and United Kingdom, the avoirdupois dram saw routine application in 18th- and 19th-century trade, agriculture, and manufacturing until the mid-20th century, when metric adoption accelerated its obsolescence.[57] The UK's Weights and Measures Act of 1824 formalized imperial standards including the dram, but post-1965 metrication policies—driven by international trade alignment—rendered smaller avoirdupois units like the dram effectively legacy by the 1970s, though legally retained in customary definitions.[57] In the US, where customary units persist under federal law, the dram remains defined via NIST standards but is seldom used outside historical references, numismatic contexts for base alloys, or archaic recipes, supplanted by grams or ounces for precision.[55]| Unit | Grains | Grams (approx.) |
|---|---|---|
| Avoirdupois dram | 27.34375 | 1.772 |
| Avoirdupois ounce | 437.5 | 28.35 |
| Avoirdupois pound | 7,000 | 453.592 |
Apothecaries' dram for mass and volume
The apothecaries' dram functioned as a dual unit of mass and volume within the apothecaries' system, tailored for pharmaceutical applications requiring exact dosing of solids and liquids before metric standardization. This system emphasized subdivisions amenable to manual measurement, such as dividing an ounce into eight drams rather than the avoirdupois system's sixteen, to reduce risks in compounding potent remedies.[59] In mass terms, the apothecaries' dram equaled 60 grains or one-eighth of the apothecaries' ounce (480 grains total), yielding approximately 3.888 grams—deliberately heavier than the avoirdupois dram (1.772 grams) to enhance accuracy in weighing minute medicinal quantities and avert underdosing.[60] The symbol ʒ denoted this unit, with prescriptions often using Roman numerals for quantities to minimize transcription errors. For volume, the fluid dram measured one-eighth of the apothecaries' fluid ounce, equivalent to 60 minims or precisely 3.696691 milliliters in the U.S. system, used for liquid preparations like tinctures and elixirs; it was marked as fʒ or fl dr.[61] This capacity aligned with the mass dram under the assumption of water's density, facilitating conversions in syrups or solutions where volume determined dose strength. Deriving from the ancient Greek drachma—a coin and weight approximating a handful—the dram entered apothecaries' practice via Roman and medieval traditions, with formalization in pharmacopeias like the London Pharmacopoeia of 1746 and U.S. standards by the 1820 Pharmacopeia of the United States to ensure reproducibility across practitioners.[62] Yet, symbol overlaps (e.g., ʒ resembling handwritten "3") and non-decimal relations contributed to errors, such as a 1970s case where one dram was misread as three tablespoons, causing theophylline overdose; such incidents, compounded by dual imperial systems, drove obsolescence in favor of metric grams and milliliters by the mid-20th century for unambiguous precision.[63][64]Armenian dram currency
Historical introduction and evolution
The Armenian dram (AMD) was introduced on November 22, 1993, as the national currency of the newly independent Republic of Armenia, replacing the Soviet ruble at an initial exchange rate of 1 dram to 200 rubles.[65][66] This transition occurred amid the dissolution of the Soviet Union, with Armenia facing severe economic disruptions from the loss of centralized planning, trade blockades, and the ongoing Nagorno-Karabakh war, which exacerbated supply shortages and fiscal imbalances.[67] The term "dram" derives from the ancient Greek "drachma," historically denoting a unit of weight and currency, reflecting linguistic continuity in the region.[68] Following its launch, the dram experienced extreme volatility, with hyperinflation exceeding 5,000% in 1994 driven by an influx of rubles from other former Soviet states, monetary overhang, and war-related production collapses that reduced output by over 50% from 1990 levels.[67][69] The currency is subdivided into 100 luma, though luma coins have seen negligible circulation due to persistent high inflation in early years eroding small denominations' utility.[65] The official symbol ֏, stylized from the Armenian letter Դ (D) for "dram," was adopted in 1995 following a national design competition to standardize representation in financial contexts.[70] Stabilization efforts intensified in the late 1990s through Central Bank of Armenia (CBA) reforms, including tightened monetary controls and fiscal consolidation, reducing inflation to single digits by 1997.[65] In the 2010s, the CBA shifted toward an inflation-targeting framework with a 4% goal (plus/minus 1.5% band), fostering relative exchange rate stability against the US dollar, often resembling a managed float supported by foreign reserves and remittance inflows exceeding 10% of GDP annually.[71] However, the 2020 Nagorno-Karabakh war and 2023 Azerbaijani offensive, displacing over 100,000 ethnic Armenians, triggered capital outflows and heightened risk premiums, depreciating the dram by approximately 20% against the dollar from 2020 to 2023 before partial recovery amid diversified remittances and export growth.[72] By October 2025, the USD/AMD rate hovered around 382, reflecting CBA interventions to mitigate volatility from geopolitical tensions and declining Russian remittances post-Ukraine invasion.[72][73]Denominations, issuance, and physical features
The Central Bank of Armenia (CBA) issues circulating coins in denominations of 10, 20, 50, 100, 200, and 500 dram, primarily composed of brass-plated steel or bimetallic materials for higher values.[74] These coins feature the Armenian coat of arms on the obverse and national symbols or landmarks on the reverse, with milled edges on larger denominations for anti-counterfeiting.[75]| Denomination (dram) | Composition | Diameter (mm) | Weight (g) |
|---|---|---|---|
| 10 | Steel | 18.5 | 3.7 |
| 20 | Steel | 21.5 | 4.6 |
| 50 | Steel | 23.0 | 5.1 |
| 100 | Brass-plated steel | 24.0 | 5.7 |
| 200 | Bimetallic | 25.0 | 7.5 |
| 500 | Bimetallic | 27.0 | 8.9 |
Economic stability, exchange rates, and policy influences
The Armenian dram has maintained relative economic stability since the hyperinflationary period of the 1990s, with annual consumer price inflation averaging approximately 4% from 2000 to 2024, a marked improvement from peaks exceeding 10,000% in the mid-1990s.[81][82] In September 2025, inflation stood at 3.7%, within the Central Bank of Armenia's (CBA) target range of 4% ±1.5%, bolstered by foreign exchange reserves exceeding $4.2 billion as of that month and personal remittances equivalent to about 6% of GDP in recent years.[83][84][85] These reserves, covering over six months of imports, have provided a buffer against external shocks, while remittances—primarily from the diaspora in Russia and the West—have supported consumption and reduced current account deficits.[86][87] The dram has operated under a managed floating exchange rate regime since 1995, transitioning from earlier fixed pegs amid post-Soviet reforms, with the CBA intervening to curb volatility rather than targeting a specific band.[65] Between 2020 and 2025, the USD/AMD rate fluctuated narrowly between roughly 380 and 485, appreciating overall due to strong remittance inflows, mining export growth (notably copper and molybdenum), and post-pandemic recovery, though it hovered around 382 in late 2025.[72][88] Key influences include Armenia's economic ties to Russia, which absorb about 40% of exports including re-exported goods, alongside aspirations for EU integration via the Comprehensive and Enhanced Partnership Agreement, which has boosted non-Russian trade but heightened exposure to commodity price swings.[89][90] Geopolitical events have tested this stability, as seen in the 2020 Nagorno-Karabakh war, which triggered a 6-9% dram depreciation against the USD in late 2020 due to capital outflows, disrupted trade, and heightened risk premiums, prompting CBA reserve drawdowns to stabilize markets.[91][92] Despite such vulnerabilities in this small, open economy—exacerbated by reliance on Russian energy imports and regional conflicts—the CBA's independent monetary policy, including inflation targeting adopted in the mid-2000s, has averted widespread dollarization, keeping foreign currency deposits below 30% of total banking assets through macroprudential tools and credibility-building measures.[71][93] Critics note, however, that state interventions, such as subsidies and fiscal expansions tied to Russian inflows post-2022, risk inflating asset bubbles over market-driven adjustments, though empirical data shows no return to 1990s-era instability.[65][94]DRAM in music and arts
DRAM (musician): Career and discography
Shelley Massenburg-Smith, performing under the stage name DRAM, began his career with the release of the single "Cha Cha" on April 14, 2015, which gained viral attention through a self-directed lo-fi video featuring him dancing in a colorful tracksuit.[95] The track peaked at number 3 on the Billboard Bubbling Under Hot 100 chart and marked his entry into mainstream hip-hop and R&B circles.[96] His breakthrough came with "Broccoli" featuring Lil Yachty, released on April 5, 2016, which debuted at number 76 on the Billboard Hot 100 and eventually peaked at number 5, certified 5× platinum by the RIAA for over 5 million units sold in the United States.[97] The song earned a Grammy nomination for Best Rap/Sung Performance at the 59th Annual Grammy Awards in 2017, which DRAM described as a profound validation early in his career.[98] This success led to his signing with Atlantic Records and Empire Distribution, culminating in the release of his debut studio album, Big Baby DRAM, on October 21, 2016, featuring collaborations with artists such as Erykah Badu, Young Thug, and Anderson .Paak, and blending hip-hop, soul, and funk elements in a playful, nostalgic style. Following the album's release, DRAM's output slowed amid reported creative differences with his label, leading to delays on subsequent projects like the initially planned Scrabble Creek.[99] He reemerged independently in 2021 under the moniker Shelley FKA DRAM—reflecting a temporary shift from his original acronym for "Do Really Amazing Music"—with the self-released album Shelley FKA DRAM. This was followed by What Had Happened Was... in 2022, a deluxe edition of Big Baby DRAM in 2017, DRAM&B in 2024, and LEORPIO in 2025, signaling a return to consistent independent releases focused on live performances and genre experimentation.[100] Critics noted his post-2016 work as artistically varied but commercially less dominant, with emphasis on personal expression over chart pursuits.Studio albums
| Title | Release date | Label | Peak chart position (Billboard 200) |
|---|---|---|---|
| Big Baby DRAM | October 21, 2016 | Empire/Atlantic | 117[96] |
| Shelley FKA DRAM | July 26, 2021 | Independent | — |
| What Had Happened Was... | November 11, 2022 | Independent | — |
| DRAM&B | 2024 | Independent | — |
| LEORPIO | 2025 | Independent | —[100] |