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Encoder

An encoder is a device, circuit, or algorithm that converts information from one format or code to another, for purposes such as data compression, error correction, or motion feedback. In electromechanical systems, encoders provide feedback on position, velocity, or direction by converting mechanical motion into electrical signals, typically digital pulses, for use in control systems, robotics, and automation. These devices are essential in applications requiring precise motion detection, such as motor control and industrial machinery, where they translate rotary or linear displacement into countable signals readable by microcontrollers or computers. Encoders are broadly classified into two main types: incremental and absolute. Incremental encoders generate pulses relative to a starting position, allowing calculation of change in position or speed but requiring a reference point to determine absolute location; they often use quadrature encoding with two channels (A and B) phased 90 degrees apart to detect direction. Absolute encoders, in contrast, output a unique code for each position without needing a reference, making them suitable for applications where power loss or system restarts cannot afford repositioning, such as elevators or CNC machines. Technologies underlying encoders include optical, magnetic, and methods. Optical encoders employ a light , , and patterned disk to produce signals, offering high resolution (up to thousands of pulses per revolution) and reliability in clean environments. Magnetic encoders use hall-effect sensors and magnetic fields for robust performance in harsh conditions like or , while encoders rely on switches for cost-effective but less durable solutions. In electronics, encoders refer to circuits that map multiple active inputs to a output, serving as the inverse of decoders and facilitating efficient data representation in systems like keyboards or analog-to-digital converters. encoders, a key subtype, resolve conflicts from multiple simultaneous inputs by assigning precedence, commonly used in handling and fault detection. In , encoders implement algorithms to add structured redundancy to data for , such as in and convolutional codes. Beyond these, the term "encoder" extends to software and algorithms in fields like data compression and , where it transforms input data into a compact or feature-rich representation. For example, in , autoencoders compress data for and feature extraction.

Digital Logic Encoders

Binary Encoders

A encoder is a circuit in electronics that converts 2^n input lines into n output lines, where only one input is active at a time, producing an output code corresponding to the position of the active input. These circuits perform the inverse function of decoders, a single active input signal to its representation on the outputs. A standard example is the 8-to-3 line binary encoder, which has eight input lines labeled D0 through D7 and three output lines Y2, Y1, and Y0. The circuit activates the output for the index of the single active input (e.g., if D5 is high and all others low, the output is 101). The full is as follows:
InputsOutputs
D7D6D5D4D3D2D1D0Y2Y1Y0
00000001000
00000010001
00000100010
00001000011
00010000100
00100000101
01000000110
10000000111
All other combinations (multiple 1s or all 0s) are invalid
The Boolean equations for the outputs, derived from the truth table using sum-of-products form, are: Y_0 = D_1 + D_3 + D_5 + D_7 Y_1 = D_2 + D_3 + D_6 + D_7 Y_2 = D_4 + D_5 + D_6 + D_7 Implementation typically involves s for each output bit, where each OR gate connects the input lines that contribute a 1 to that bit position in their (e.g., Y0 ORs all odd-indexed inputs). AND gates are not required in the basic form since inputs are assumed mutually exclusive, but the circuit relies solely on without memory elements. A key limitation arises if multiple inputs are active simultaneously, resulting in an erroneous output due to the OR , which may not represent a valid single ; this issue is mitigated in priority encoders that resolve conflicts by prioritizing higher inputs. Binary encoders find applications in , where they compress multiple data lines into a fewer-bit for , and in scanning to encode the position of a pressed into a signal. They are also used in address decoding within systems to map active select lines to addresses and in simple data selectors for routing input signals based on encoded positions.

Priority Encoders

A is a combinational logic designed to convert multiple inputs into a single output representing the highest-priority active input, thereby resolving conflicts when more than one input is asserted simultaneously. The purpose of this circuit is to ensure reliable encoding in systems where multiple inputs may activate at once, prioritizing the input with the highest designated index (typically the most significant bit) while ignoring lower-priority ones. This contrasts with basic binary encoders, which assume only a single input is active and produce invalid outputs otherwise. A common example is the 8-to-3 , which accepts eight inputs labeled I_0 through I_7 (with I_7 having the highest priority) and produces a 3-bit output A_2 A_1 A_0 corresponding to the index of the highest active input, along with a valid V that asserts high if any input is active. For instance, if I_2 and I_5 are both active, the selects I_5 (index 101 in ), outputting A_2 = 1, A_1 = 0, A_0 = 1, and V = 1. The behavior of an 8-to-3 encoder can be illustrated through key cases in its , focusing on scenarios that demonstrate resolution and the valid output:
Active InputsA_2 A_1 A_0VDescription
None0000No input active; outputs invalid
I_0 only0001Lowest selected
I_0, I_10011I_1 prioritized over I_0
I_2, I_51011I_5 prioritized over I_2
I_3, I_71111I_7 prioritized over I_3
All inputs1111Highest I_7 selected
These cases highlight how the encoder ignores lower-priority inputs when higher ones are active. The logic for the outputs requires ensuring only the highest active input contributes. This is typically implemented using intermediate signals H_i, where H_i = I_i \land \lnot (I_{i+1} \lor I_{i+2} \lor \cdots \lor I_7) indicates that I_i is the highest-priority active input. The output equations are then: A_0 = H_1 + H_3 + H_5 + H_7 A_1 = H_2 + H_3 + H_6 + H_7 A_2 = H_4 + H_5 + H_6 + H_7 V = I_0 + I_1 + I_2 + I_3 + I_4 + I_5 + I_6 + I_7 These expressions ensure that the output reflects the binary representation of the highest active input index. Many priority encoders include an enable input (EI) to control operation and an enable output (EO) for cascading multiple encoders, with the relation EO = EI \cdot V allowing expansion to handle more inputs without external logic. This feature is evident in integrated circuits like the 74LS148, where active-low signals facilitate hierarchical priority encoding. Priority encoders find essential applications in interrupt controllers within microprocessors, such as the 8259 , which prioritizes multiple requests based on assigned levels to ensure timely handling of critical events. They are also used in interfaces to key positions, where simultaneous presses are resolved by selecting the highest-priority (e.g., row-column) input for accurate detection.

Position and Motion Sensors

Rotary Encoders

Rotary encoders are electromechanical devices that convert angular mechanical motion into digital or analog electrical signals, providing precise feedback on position, speed, or direction of rotation. The core principle involves a rotating or attached to the , featuring slots, marks, or patterns that are detected by sensors such as optical, magnetic, or capacitive types to generate pulses or codes corresponding to the angular position. Optical variants typically use a light source like an LED and a to interrupt or modulate light beams as the rotates, while magnetic encoders employ sensors to detect changes in magnetic fields from embedded magnets or poles on the . There are two primary types: incremental and absolute rotary encoders. Incremental encoders provide relative position information by generating quadrature signals, consisting of two output channels (A and B) with a 90-degree phase shift, which enables detection of both rotation direction and speed through the sequence of rising and falling edges. Resolution in incremental encoders is determined by the number of lines per revolution (LPR) on the disc; for example, 1024 LPR provides 10-bit base precision (1024 pulses per revolution per channel), but with quadrature decoding, it yields 4096 counts per revolution (12-bit precision) by counting four edges per line. In contrast, absolute encoders deliver direct absolute position data without requiring a reference point, using a multi-track disc where each track represents a bit in a unique code pattern, such as or binary, assigned to every angular position. is preferred in absolute designs because it ensures only one bit changes between adjacent positions, minimizing errors during transitions. The angular position \theta can be calculated as: \theta = \frac{\text{code value} \times 360^\circ}{2^n} where n is the number of bits determining the resolution. Construction of rotary encoders varies by sensing technology but generally includes a shaft-coupled code disc housed in a protective enclosure, with sensor arrays fixed to the stator. Optical encoders commonly pair an infrared LED emitter with photodiodes or phototransistors to detect light modulation through transparent slots on the disc, achieving high resolution up to thousands of LPR. Magnetic encoders utilize Hall effect sensors to sense alternating north-south magnetic poles on a diametrically magnetized ring, offering robustness in dusty or oily environments where optical systems might fail. Output interfaces include parallel TTL (transistor-transistor logic) for incremental signals or serial protocols like SSI (Synchronous Serial Interface) for absolute data transmission, facilitating integration with microcontrollers or PLCs. Rotary encoders find widespread applications in motor control systems for robotics, where they enable precise servo feedback for joint positioning; in CNC machines for accurate spindle and axis monitoring; and in consumer audio equipment, such as volume knobs that provide tactile, infinite-turn adjustment with detents. As of 2025, advancements include seamless integration with IoT platforms, enabling wireless data transmission via Bluetooth or Wi-Fi modules embedded in encoder housings, which surpasses the limitations of 1990s-era wired connections by allowing remote monitoring and predictive maintenance in smart factories. This wireless evolution enhances connectivity in Industry 4.0 applications while maintaining the core mechanical reliability of traditional designs.

Linear Encoders

Linear encoders are sensors that convert linear into electrical signals, enabling precise of straight-line motion. They typically consist of a featuring periodic marks, such as gratings, and a readhead that detects these marks through optical, inductive, or interferometric methods to generate data. In optical systems, the readhead uses to illuminate the and photodetectors to capture interference patterns or modulated signals from the gratings. Inductive encoders employ electromagnetic fields to sense changes in the 's conductive patterns without physical contact. Interferometric approaches, often involving , produce high-resolution signals by exploiting phase shifts in waves diffracted from fine gratings. Incremental linear encoders operate on a straight scale analogous to their rotary counterparts but measure along a linear , producing pulses proportional to . Each mark on the scale generates signals (A and B channels) that indicate position, direction, and speed, with a reference mark for homing. Resolutions reach sub-micron levels, such as 1 μm, equivalent to 1 million counts per meter, enabling fine control in dynamic systems. Absolute linear encoders deliver a unique digital code corresponding to the exact position without requiring a homing sequence upon startup. They utilize scales with pseudo-random binary sequences or absolute grating patterns, where the position x is calculated as x = (\text{code}) \times \text{scale pitch}. This design supports immediate position readout via serial protocols, with lengths up to 21 meters in advanced models. Common error sources in linear encoders include thermal expansion of the scale material and contamination from dirt or debris, which can degrade signal quality. Mitigation strategies involve using materials with low thermal coefficients, such as glass scales with expansion rates of $8 \times 10^{-6} \, \text{K}^{-1}, and sealed enclosures rated IP64 or higher to protect against environmental factors. Accuracy specifications often achieve ±5 μm over 1 meter, with wide mounting tolerances up to ±0.3 mm to minimize alignment errors. Interfaces for linear encoders include analog sine/cosine outputs for incremental types, allowing external for higher , and protocols like EnDat 2.2 for encoders, which transmit position data bidirectionally over serial lines. Other standards include 1 Vpp signals, for incremental, and specialized interfaces like DRIVE-CLiQ for integration with servo systems. Applications of linear encoders span machine tools like milling and grinding machines for closed-loop feedback, coordinate measuring machines (CMMs) for , and Z-axis positioning, and systems for precise floor-level detection. They ensure high dynamic performance and accuracy in environments. By , advancements in laser-based interferometric linear encoders have enabled nanoscale precision, with resolutions down to 0.013 nm using nanostructured gratings and demodulation, building on inductive designs from the . These developments incorporate pseudo-random codes and AI-enhanced processing for absolute positioning in and .

Media Compression Encoders

Video Encoders

Video encoders are hardware or software systems that compress raw video data, typically in RGB or color formats, into efficient bitstreams suitable for storage, transmission, or playback. In the pipeline, they convert sequences of frames by applying to exploit temporal redundancies between frames and to reduce spatial redundancies within each frame, enabling significant data reduction while preserving perceptual quality. The evolution of video encoders traces back to the standard, developed in the 1990s and widely adopted for DVD storage and broadcasting, which supported standard-definition video at bitrates around 4-6 Mbps. Subsequent advancements led to H.264/AVC in 2003, introduced by the Video Coding Experts Group (VCEG) and ISO/IEC (MPEG), incorporating intra-frame and inter-frame prediction to achieve about twice the compression efficiency of for the same quality. Building on this, H.265/HEVC emerged in 2013, designed for high-efficiency encoding of and beyond, with larger coding tree units (up to 64x64 pixels) that reduce bitrate requirements by approximately 50% compared to H.264/AVC through improved prediction and partitioning flexibility. More recently, the codec, finalized in 2018 by the , offers royalty-free encoding with 30-40% better compression than H.265/HEVC, targeting internet video distribution. Subsequently, (VVC, also known as H.266), jointly developed by and MPEG and finalized in 2020, further advances compression efficiency with about 30-50% lower bitrates than H.265/HEVC at the same quality level, enabling support for resolutions up to 16K, though its widespread adoption as of 2025 remains limited by complex royalty licensing. Ongoing developments include AV2, the next iteration of , in progress as of 2025 for even greater efficiency. At the core of these encoders are algorithmic processes that begin with block-based partitioning of frames, followed by to identify and compensate for movement across frames. Residual data—differences after prediction—is then transformed using the (DCT), typically applied to blocks in standards like H.264/AVC, which concentrates energy into fewer coefficients for easier compression. These coefficients undergo quantization, where each is scaled and rounded via Q = \round\left(\frac{\coeff}{\scale}\right) to discard less perceptible details based on a quantization , controlling the bitrate-quality tradeoff. Finally, , such as Context-Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC and later standards, adaptively compresses the quantized data by modeling symbol probabilities, achieving up to 10-20% additional bitrate savings over simpler methods. Hardware implementations accelerate these processes using dedicated chips, exemplified by NVIDIA's NVENC, introduced in 2012 with Kepler GPUs and evolving through generations to support real-time encoding. By 2025, NVENC in and later architectures enables 8K video encoding at 60 fps via multiple parallel engines and split-frame techniques, offloading computation from the CPU for low-latency applications. Performance is evaluated using metrics like compression ratios, which can reach 100:1 for high-definition () video under typical conditions, balancing file size against visible artifacts. Quality is often quantified via (PSNR), where values above 30 dB indicate good fidelity for 8-bit video, serving as a for encoder in objective tests. Video encoders find widespread use in streaming platforms like for on-demand delivery, broadcasting for distribution over satellite or IP networks, and systems for recording and remote monitoring of high-resolution feeds.

Audio Encoders

Audio encoders compress digital audio signals by exploiting properties of human hearing to reduce data rates while preserving perceptual quality. Uncompressed (PCM) audio, such as the 1.411 Mbps stereo format at 44.1 kHz sampling used for compact discs, can be reduced to around 128 kbps through perceptual techniques that model psychoacoustic phenomena. These methods identify and eliminate inaudible signal components, allowing efficient and without significant loss in perceived sound fidelity. Perceptual coding relies on masking thresholds to discard redundant data: simultaneous masking occurs when a louder sound obscures nearby frequencies, while temporal masking affects sounds preceding or following a strong tone. Audio is analyzed in the frequency domain using the (MDCT), a lapped transform that efficiently represents overlapping signal blocks with near-optimal energy compaction for . The encoding process divides the signal into a of 32 subbands, applies quantization based on auditory models, and uses like Huffman to further minimize bits. Quantization precision is determined by the signal-to-mask ratio (SMR), calculated as \text{SMR} = \frac{\text{signal energy in subband}}{\text{masking threshold}} where higher SMR values indicate subbands requiring more bits to avoid audible distortion. Prominent standards include MP3 (MPEG-1 Audio Layer III), developed in the early 1990s with Huffman coding for bitstream efficiency, achieving transparent quality at 128-192 kbps; AAC (MPEG-2 Part 7), standardized in 1997, which improves compression by 30-50% over MP3 through enhanced perceptual modeling and MDCT windows; and Opus (RFC 6716), released in 2012, a hybrid codec combining linear prediction for speech and MDCT for music, optimized for low-latency applications like VoIP at bitrates from 6-510 kbps. Encoders often operate in variable bitrate (VBR) mode for content-adaptive allocation or constant bitrate (CBR) for predictable streams; the open-source LAME encoder exemplifies high-fidelity MP3 implementation, particularly in VBR for mid-to-high bitrates. These technologies enable applications in music streaming platforms like Spotify, where AAC delivers high-quality playback at low bandwidths; telephony for efficient voice transmission; and file formats such as MP4 containers. By 2025, the LC3 codec, specified for Bluetooth LE Audio, has emerged as a successor to SBC, offering up to 50% bandwidth reduction at equivalent quality levels through advanced bandwidth extension and noise shaping.

Coding Theory Encoders

Block Code Encoders

Block code encoders in are systematic methods that map a block of k information bits to a longer codeword of n > k bits, introducing to enable in communication or storage systems. This encoding process relies on algebraic structures, typically over finite fields like GF(2) for codes, where the codewords form a of the of length n. The G, an n \times k matrix, defines the code by producing codewords as linear combinations of its rows when multiplied by the message vector. Linear block codes, a prominent class, ensure that the set of codewords is closed under addition and scalar multiplication, forming a linear subspace. In systematic form, the generator matrix takes the structure G = [I_k \mid P], where I_k is the k \times k identity matrix and P is a k \times (n-k) parity matrix; the resulting codeword is c = [u \mid p], with u as the k-bit message and p = u P as the parity bits. Validity is verified via the parity-check matrix H, an (n-k) \times n matrix orthogonal to G, satisfying H c^T = 0 for all codewords. The minimum Hamming distance d of the code determines its error-correcting capability, allowing correction of up to \lfloor (d-1)/2 \rfloor errors. A example is the code, which encodes 4 information bits into 7-bit codewords using a whose first four columns form the and the remaining three incorporate parity checks based on powers of 2. This code achieves d=3, enabling single-error correction by locating and flipping the erroneous bit via syndrome decoding. The encoding computes c = u G, where u is the message row vector. An extension, the (8,4) code, appends an overall to the (7,4) codeword, increasing d to 4 for single-error correction and double-error detection (SECDED). Cyclic block codes form a subclass where any cyclic shift of a codeword remains a codeword, facilitating efficient implementation via polynomial algebra. These codes are generated by a monic generator polynomial g(x) of degree n-k that divides x^n + 1 (over GF(2)), with codewords corresponding to multiples of g(x) modulo x^n + 1. Encoding multiplies the message polynomial u(x) (of degree less than k) by x^{n-k} and divides by g(x), using the remainder to form the parity polynomial. Reed-Solomon codes, a non-binary cyclic variant over GF(q), exemplify this with d = n - k + 1. Block code encoders find widespread use in error-correcting applications, such as single-error correction double-error detection (SECDED) in modules via extended Hamming codes to protect against cosmic ray-induced bit flips. In , cyclic like Reed-Solomon underpin error correction in QR codes, allowing recovery from up to 30% data loss depending on the error-correction level by reconstructing damaged symbols. The theoretical foundation for traces to Claude Shannon's 1948 paper, which established the channel coding theorem proving reliable communication rates below using randomized codes, inspiring structured deterministic constructions. invented the (7,4) code in 1950 while at , motivated by unreliable computing hardware, publishing the first practical linear for single-error correction.

Convolutional Code Encoders

Convolutional code encoders produce a class of error-correcting codes known as , which add to streams by linearly combining current and previous input bits using a finite mechanism. These encoders differ from encoders by processing input continuously rather than in fixed-length blocks, enabling real-time encoding suitable for streaming applications. The concept was introduced by Peter Elias in 1955 as part of schemes for achieving error-free communication over noisy channels, where convolutional structures allow arbitrary error rates to be approached with sufficient . The algebraic foundation of convolutional encoders was formalized by G. David Forney Jr. in , describing them as time-invariant linear sequential circuits that map input sequences into output sequences via with generator sequences. A convolutional encoder is characterized by the (n, k, m), where k is the number of input bits processed per time step, n is the number of output bits generated (n > k), and m is the encoder memory order, determining the number of previous input bits influencing each output. The code rate is R = k/n, typically less than 1 to introduce ; the constraint length is often K = m + 1 for rate-1 codes. Andrew Viterbi's 1967 analysis provided error probability bounds for these codes, demonstrating their asymptotic optimality when paired with maximum-likelihood decoding, which propelled their practical use. In implementation, a convolutional encoder employs k shift registers, each of length m, to store input history, with n modulo-2 adders computing outputs based on generator polynomials or connection vectors that specify which register taps contribute to each output stream. The j-th output sequence v^{(j)} at time t is computed as v^{(j)}(t) = \bigoplus_{i=0}^{m} g_{j,i} \, u(t - i) \pmod{2}, where \bigoplus denotes modulo-2 addition (XOR), u(t) is the input bit stream, and g_{j,i} \in \{0,1\} are the coefficients of the j-th polynomial of degree at most m. This convolution operation ensures the output depends on the current input and up to m prior bits, creating inter-symbol dependencies that aid error correction. A representative example is the rate-1/2 convolutional encoder with constraint length 7, standardized by and the Consultative Committee for Space Data Systems (CCSDS) for deep-space communications. It uses two generator polynomials represented in as 171 ($1 + D^2 + D^3 + D^5 + D^6) and 133 ($1 + D^2 + D^3 + D^4 + D^6), where D is the delay operator. For an input bit u(t) = 1 followed by zeros to flush the registers, the encoder produces a specific output sequence that propagates through the 64 possible states ( $2^{6} for m=6 ), illustrating the trellis structure inherent to the encoding process. This configuration achieves a free distance of 10, providing robust error correction at rates up to several megabits per second in high-noise environments like satellite links.

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