Fact-checked by Grok 2 weeks ago

GDSII

GDSII, short for Graphic Design System II^[1], is a binary database file format that serves as the de facto industry standard for exchanging two-dimensional layout artwork in integrated circuit (IC) design and semiconductor manufacturing.^[2] It represents planar geometric shapes, text labels, and hierarchical structures essential for defining photomask patterns used in chip fabrication.^[3] Developed in the late 1970s, GDSII enables the transfer of complex IC designs from electronic design automation (EDA) tools to foundries, ensuring compatibility across diverse software and hardware ecosystems.^[4] Originally created by Calma Corporation in 1978 as an evolution of its earlier GDS format, GDSII was designed to address the fragmentation caused by proprietary file formats in the emerging IC industry.^[3] Calma, a pioneer in computer-aided design for electronics, introduced the format to facilitate precise control of photomask plotting equipment, which was critical for photolithography processes.^[2] Following Calma's acquisition, ownership passed through General Electric and Valid Logic Systems before settling with Cadence Design Systems, which maintains the specification—last formally updated in 1989.^[4] Despite its age, GDSII remains ubiquitous due to its robustness in handling hierarchical data, where designs are broken into reusable cells to manage complexity in modern chips with billions of polygons.^[4] Key features of GDSII include its use of a record-based binary structure for compact storage, with coordinates defined in integer nanometers (10⁻⁹ meters) to support high-precision layouts.^[4] It organizes data into libraries containing structures (cells) composed of elements like boundaries, paths, polygons, and references to other structures, each tagged with layers and datatypes for process-specific routing.^[2] This hierarchy allows unlimited nesting—typically up to nine levels in practice—optimizing file sizes that can reach several gigabytes for advanced nodes.^[4] Text elements and attributes further annotate designs for verification and documentation.^[3] In semiconductor workflows, GDSII files represent the culmination of the design process, often termed "tape-out," a nod to the magnetic tape storage of early versions.^[2] They are exported from EDA tools like those from Synopsys or Mentor Graphics and imported by foundries such as TSMC or Intel for mask creation and wafer production.^[3] While effective for ICs, printed circuit boards (PCBs), and micro-electro-mechanical systems (MEMS), GDSII's limitations—such as vertex count caps on polygons (up to 8191 in later versions) and lack of native support for three-dimensional or optical proximity correction data—have prompted alternatives like OASIS.^[4] Nonetheless, its entrenched adoption ensures GDSII's continued relevance in the global electronics supply chain.^[3]

Overview

Definition and Purpose

GDSII, or Graphic Design System II, is a binary database file format designed for the exchange of electronic design automation (EDA) data in integrated circuit (IC) design. It specifically represents 2D planar geometric shapes, text labels, and hierarchical layout information, enabling the precise depiction of IC layouts in a structured, efficient manner.^[3]^[4] As the de facto industry standard since the late 1970s, GDSII facilitates photomask data preparation and interoperability between diverse EDA tools from various vendors.^[5] This standardization ensures that layout data can be reliably shared across the semiconductor design ecosystem without loss of fidelity, supporting the complex requirements of modern IC fabrication.^[6] GDSII files commonly bear the extensions .gds or .gdsii and represent the culminating output of the physical design phase in very-large-scale integration (VLSI) workflows. In this role, they encapsulate the complete geometric and annotative details needed for mask production, serving as the handoff mechanism from design teams to foundries for chip manufacturing.^[4]^[7]

Role in IC Design

In the VLSI design flow, GDSII serves as the standard format for representing the physical layout of integrated circuits after the completion of place-and-route and verification stages, facilitating the seamless transfer of geometric data from electronic design automation (EDA) tools to semiconductor foundries for fabrication.^[3] This role begins once the logical netlist is transformed into a detailed mask layout, where GDSII files encapsulate polygons, paths, and other primitives that define the circuit's structure, enabling mask generation for photolithography processes.^[8] GDSII plays a pivotal role in the tape-out process, the critical milestone where finalized design data is delivered to foundries for photomask production, ensuring interoperability across diverse EDA platforms from vendors such as Synopsys, Cadence, and Siemens EDA (formerly Mentor Graphics).^[9] During tape-out, the GDSII stream file is generated, verified for compliance, and transmitted, often via secure channels, to initiate wafer fabrication while minimizing errors in pattern transfer to silicon.^[10] This compatibility standard has been essential for multi-vendor workflows, allowing designs from tools like Synopsys IC Compiler or Cadence Innovus to integrate without format conversion issues.^[11] Despite originating in the 1970s, GDSII remains prevalent in modern IC production, adeptly handling the complexity of layouts for advanced nodes with billions of transistors, such as those in high-performance computing and mobile processors.^[3] Its binary hierarchical structure supports efficient representation of massive designs—often exceeding several gigabytes—through cell referencing and layering, making it indispensable for scaling to sub-5nm processes without obsolescence.^[2] This enduring utility underscores GDSII's foundational impact on the semiconductor industry, where it continues to bridge design intent and manufacturable reality.^[12]

History

Origins and Development

Calma Company, established in 1964 in Sunnyvale, California, pioneered early computer-aided design (CAD) tools for the electronics industry. In 1971, the company introduced the Graphic Design System (GDS), a layout software system designed to facilitate the creation and manipulation of integrated circuit (IC) mask designs using interactive graphics on storage tube displays. This initial format addressed the emerging need for precise geometric representation in semiconductor layout.^[13]^[14] By 1978, Calma evolved GDS into GDSII to accommodate more advanced computing architectures, such as 32-bit processors, and to enable broader data interoperability. The key innovation was the GDSII stream format, a binary, record-based structure optimized for sequential writing to magnetic tapes, which served as the primary medium for data exchange at the time. This format provided a reliable basis for transferring IC layout data to photomask plotting equipment, streamlining the production of photolithography masks essential for chip fabrication. Its binary nature offered advantages in compactness and processing speed over text-based alternatives, though detailed record specifications are covered elsewhere.^[14]^[15]^[16] During the 1980s, GDSII rapidly gained traction as an informal de facto standard in the semiconductor sector, largely due to the absence of viable competing formats and the explosive growth of the industry, which demanded efficient, standardized methods for sharing complex layout data between design teams, foundries, and mask houses. As IC designs increased in density and scale, the format's hierarchical structure and portability proved indispensable for collaboration, solidifying its role despite not being formally ratified by any standards body. By the mid-1980s, it had become ubiquitous for tape-outs and data handoffs, underpinning the workflow of major players in electronics manufacturing.^[4]^[17]

Ownership and Evolution

Following its initial development by Calma in the late 1970s, the GDSII format underwent a series of corporate ownership changes that shaped its stewardship. In 1981, Calma was acquired by General Electric (GE), which integrated the technology into its broader electronics portfolio.^[13] By 1988, GE sold its electronics division, including the GDSII specification, to Valid Logic Systems, a specialist in electronic design automation (EDA) tools.^[4] This transfer positioned Valid as the custodian of the format during a period of growing EDA industry consolidation.^[18] In 1991, Valid Logic Systems was acquired by Cadence Design Systems for approximately $200 million, establishing Cadence as the current owner of the GDSII specification.^[19] Under Cadence's ownership, the format has seen no formal revisions beyond its last official update in 1989 with Revision 7.0, which primarily removed certain structural limits from prior versions, such as polygon point counts.^[4]^[20] Since then, the core specification has remained unchanged, though EDA tool vendors have implemented informal extensions to handle larger designs while preserving backward compatibility, such as increased support for hierarchical references and extended precision in non-standard implementations.^[4] Discussions on transitioning from GDSII to successor formats began in the early 2000s, with the Open Artwork System Interchange Standard (OASIS) emerging as a proposed replacement around 2004 to address GDSII's file size and complexity limitations for advanced nodes.^[21] Despite these efforts and OASIS's formal adoption by SEMI, GDSII has endured as the dominant standard, particularly for smaller designs, due to its entrenched ecosystem and compatibility in legacy workflows.^[22]

File Format Specifications

Record Structure

The GDSII file format is organized as a sequential stream of binary records, each beginning with a 4-byte header that specifies the record's structure and content. The header consists of two bytes indicating the total length of the record in 8-bit bytes (with a maximum of 65,536 bytes), followed by one byte for the record type and one byte for the data type.^[23] Data follows immediately after the header, with records processed in order without indexing or random access support.^[24] Key records delineate the file's logical sections and elements. The file commences with the BGNLIB record (type 0102), which includes 12 bytes of modification and last-access timestamps encoded as six pairs of 2-byte signed integers for year, month, day, hour, minute, and second.^[23] This is followed by the LIBNAME record (type 0206), containing an ASCII string for the library name (up to 32 characters, padded to even length if necessary), and the UNITS record (type 0305) specifying scaling factors. The library concludes with the ENDLIB record (type 0400). Within the library, individual structures are bounded by BGNSTR (type 0502, including creation and modification timestamps similar to BGNLIB), STRNAME (type 0606, an ASCII string for the structure name), and ENDSTR (type 0700) records.^[23]^[24] Entity records, such as BOUNDARY (type 0800) for polygonal shapes, PATH (type 0900) for stroked paths, and TEXT (type 0C00) for labels, define the geometric and textual content within structures.^[23] The format employs empty records (type 0000 or 0001, with no data) for padding to align data on even byte boundaries or between physical blocks, ensuring compatibility with storage media.^[23] All records are strictly binary, with data types including bit arrays (type 1), 2-byte integers (type 2), 4-byte integers (type 3), 8-byte reals (type 5), and ASCII strings (type 6), optimized for efficient parsing and minimal storage in integrated circuit design workflows.^[24] There is no ASCII-equivalent representation of the format, as the binary structure prioritizes compactness and speed over human readability.^[23]

Data Units and Precision

In the GDSII format, the fundamental measurement system relies on a database unit that is conventionally set to 1 nanometer (10^{-9} meters), providing the base resolution for all spatial data within the file.^[23]^[4] This unit is specified through the UNITS record (type 0305), which contains two 8-byte floating-point values: the first represents the size of the database unit in user units (typically 0.001 for a user unit of 1 micron), and the second defines the database unit size in meters (1.0 \times 10^{-9}).^[23] The user unit allows designers to work in more intuitive scales, such as microns, while the underlying database maintains nanometer precision; for instance, a user unit of 1 micron equates to 1000 database units.^[23] This structure ensures consistent scaling across tools but ties all measurements to the fixed nanometer grid. Coordinates and geometric positions in GDSII are represented exclusively as 4-byte signed integers, with no support for floating-point values in spatial data.^[23] Each integer spans a range from -2^{31} to 2^{31} - 1, or approximately \pm 2.147 \times 10^9 database units, which translates to \pm 2.147 meters when using the standard 1 nm database unit.^[23]^[4] These integers are stored in XY records (type 1003) as pairs defining points, such as for boundaries or paths, with up to 200 pairs per element to limit record size.^[23] The integer-only format enforces grid alignment to the database unit, simplifying processing but restricting flexibility in coordinate placement. Due to the integer-based system, GDSII imposes precision limitations, particularly for features smaller than the database unit, requiring approximations to the nearest nanometer.^[4] This constraint extends to element references, where records like SREF (structure reference) and AREF (array reference) use the same 4-byte integer coordinates for placement and scaling, ensuring hierarchical elements adhere to the overall precision bounds without sub-unit offsets.^[23] While the UNITS record's floating-point values allow for scalable interpretation, the core data remains quantized, making GDSII suitable for most IC layouts but less ideal for ultra-precise simulations.^[23]

Core Elements

Geometric Primitives

The geometric primitives in GDSII form the foundational building blocks for representing integrated circuit layouts as 2D planar shapes, consisting primarily of the BOUNDARY and PATH records. These primitives are defined using integer coordinates in database units, where 1 DBU typically equals 1 nanometer (10^{-9} m) for IC layouts, ensuring precise but discrete positioning without support for floating-point or 3D elements. All shapes are strictly 2D, with no native representation of curved surfaces beyond approximations using multiple straight segments.^[23] The BOUNDARY record defines closed polygonal shapes, such as filled areas or outlines, by specifying a sequence of XY coordinate pairs that form the vertices of the polygon. Each boundary requires at least four coordinate pairs, with the first and last points coinciding to close the shape, and is limited to a maximum of 200 pairs per record in the standard specification, though some implementations extend this to thousands for complex contours. Coordinates are provided as 4-byte signed integers via the XY record, allowing for efficient storage of planar polygons that can represent features like transistor gates or metal interconnect regions. These primitives are assigned to specific layers and datatypes for contextual meaning within the layout. The format's structure enables handling billions of such polygons across large designs through hierarchical organization, minimizing redundancy while maintaining computational efficiency during processing.^[23]^[25]^[24] The PATH record, in contrast, represents open linear features such as wires or traces, defined by a centerline polyline of two or more XY coordinate pairs, also limited to 200 per record in the core specification. Paths include a WIDTH record specifying a constant thickness as a 4-byte signed integer in database units, defaulting to zero if omitted, which determines the feature's breadth perpendicular to the centerline. End extensions are controlled by the PATHTYPE record, a 2-byte integer that dictates cap styles: 0 for flush square ends aligned with the digitized endpoints, 1 for round ends with semicircular caps centered on the endpoints, and 2 for square ends extended by half the path width beyond the endpoints; a value of 4 enables custom extensions via BGNEXTN and ENDEXTN records for variable distances. The point list is encoded directly in the XY records, supporting straight-line segments between points, with arcs approximated by dense sequences of vertices rather than native curves. Like boundaries, paths use integer coordinates exclusively and are confined to 2D planes, facilitating scalable representation of routing in high-density layouts.^[23]^[24]^[26]

Layers and References

In the GDSII format, layers serve as a primary mechanism for organizing geometric elements, such as boundaries, paths, and text, according to their intended role in the integrated circuit fabrication process. Each layer is identified by a unique number ranging from 0 to 63 per the original specification, though commonly extended to 0-255 in modern implementations, allowing up to 256 distinct layers in a design file.^[2]^[24] These layers are specified via the LAYER record, a two-byte signed integer that precedes the relevant element records and groups features like routing wires or implant regions for process-specific handling during mask generation.^[24] Associated with each layer, datatypes provide further sub-classification of elements within that layer, ranging from 0 to 63 per the original specification, though commonly extended to 0-255, enabling finer distinctions such as active areas versus contacts on the same layer.^[2]^[27] The DATATYPE record, structured similarly to LAYER as a two-byte signed integer, follows the LAYER record for applicable elements and supports process-specific routing or validation, where, for example, datatype 0 might represent a base polygon while datatype 1 denotes a via cut.^[24] This dual numbering system—layer for broad categorization and datatype for detail—facilitates efficient data management in electronic design automation tools without exceeding the format's integer constraints.^[4] Text annotations in GDSII are managed through the TEXT record, which defines labels for documentation, net naming, or process notes, positioned via XY coordinates and classified by LAYER and TEXTTYPE (ranging from 0 to 63 per the original specification, though commonly extended to 0-255).^[2] The record includes a PRESENTATION field specifying font style (e.g., standard or custom stroke), text height, and justification (left, center, or right), while the STRING record holds the ASCII content, limited to 512 characters.^[24] Transformations for text orientation are handled by the STRANS record, a bit array that flags mirroring across the x-axis (bit 0) and indicates absolute magnification (bit 13) or angle (bit 14), allowing rotated or reflected labels without altering the underlying geometry.^[23]^[4] References enable hierarchical reuse of structures in GDSII, promoting design efficiency by instancing predefined cells rather than duplicating geometry. The SREF (structure reference) record instantiates a single copy of a named structure (via SNAME), applying transformations from STRANS, optional MAG (magnification factor) and ANGLE (rotation in degrees), and positioning via XY coordinates.^[2]^[24] For repetitive patterns, the AREF (array reference) record places multiple instances in a rectangular or skewed lattice, specified by COLROW (up to 32,767 columns and rows) and three XY pairs defining the array vectors.^[23]^[4] Node-specific properties enhance references and other elements by marking connection points, such as pins, through the NODE record, which includes LAYER, NODETYPE (0-63 per the original specification, though commonly extended to 0-255 for classification), and up to 50 XY coordinates for polygon nodes.^[2] Custom attributes are attached via PROPATTR (attribute number 1-127 or up to 999 in extended implementations) and PROPVALUE (ASCII string up to 126 characters), allowing metadata like net names or design rules to be associated with SREF, AREF, or NODE elements, with a total property size limit of 128 bytes per element (or 512 for references).^[24]^[23] These features collectively support modular, annotated layouts while maintaining the format's binary efficiency.^[2]

Applications and Workflow

Integration in EDA Tools

GDSII files are generated as the output from layout tools in electronic design automation (EDA) workflows following the completion of place-and-route and design rule checking (DRC) verification stages. In Cadence Virtuoso, custom analog and mixed-signal layouts undergo stream out to produce GDSII after DRC clearance, ensuring the geometric data accurately represents the finalized design hierarchy.^[15] Similarly, Synopsys IC Compiler II, as part of its place-and-route process, exports GDSII post-verification to encapsulate the physical implementation for downstream processing.^[28] Upon export, GDSII files are imported into dedicated verification environments to support further analysis, including layout-versus-schematic (LVS) checks, additional DRC, and mask data preparation. Tools like Synopsys IC Validator seamlessly ingest GDSII for high-performance DRC and LVS, enabling rapid iteration by maintaining the file's hierarchical structure during import.^[29] This hierarchy preservation facilitates efficient design cycles, allowing modifications at various abstraction levels without full flattening, which is critical for large-scale integrated circuits.^[3] GDSII's role as an industry-standard format ensures broad compatibility across EDA vendors, making it indispensable for foundry sign-off procedures. Foundries such as Samsung provide certified DRC decks that validate GDSII compliance against process-specific rules, bridging tools from multiple providers like Synopsys and Cadence in a unified ecosystem.^[30] This interoperability minimizes translation errors and supports collaborative workflows essential for tape-out readiness.^[3]

Tape-Out Process

The tape-out process in integrated circuit (IC) design refers to the critical handover of finalized layout data from the design team to the manufacturing foundry, marking the transition from digital design to physical production. Historically, the term "tape-out" derives from the era when design files, including GDSII streams, were stored on magnetic tapes and physically delivered to fabrication facilities for mask creation. This practice, prevalent in the 1970s and 1980s, ensured reliable transfer of geometric data representing layers and primitives essential for photolithography. Today, while physical tapes are obsolete, the terminology persists as a milestone signifying design closure. Prior to tape-out, the GDSII file undergoes rigorous final verification to ensure manufacturability and correctness. This includes layout-versus-schematic (LVS) checks, which compare the physical layout against the original schematic to detect connectivity errors, such as opens or shorts. Antenna checks verify compliance with rules preventing charge buildup on metal interconnects during plasma etching, which could damage thin gate oxides. Density rules are also enforced to avoid over- or under-population of features in specific areas, mitigating issues like chemical-mechanical polishing nonuniformity or electromigration in advanced nodes. These verifications, typically performed using foundry-provided design rule decks, must pass without violations before export to prevent costly respins. Once verified, the GDSII file—containing hierarchical representations of geometric primitives and layer assignments—is submitted to foundries such as TSMC or Intel Custom Foundry. Submission occurs via secure file transfer protocol (SFTP) or equivalent encrypted channels to protect intellectual property during transit. Accompanying the GDSII are job decks, which are control files specifying mask layout, layer processing instructions, and alignment marks for the mask house. These decks guide the conversion of GDSII data into photomask patterns using tools like MEBES writers. For example, TSMC requires GDSII handoff through certified portals that validate file integrity upon receipt. In modern workflows, especially for advanced nodes below 7 nm, GDSII files can exceed several gigabytes due to the complexity of multi-layer designs, necessitating compression techniques to reduce transfer times and storage needs. Tools apply hierarchical optimization or format-specific compression, achieving size reductions of up to 50% without data loss, while encryption standards like AES ensure secure delivery over networks. This evolution from magnetic tapes to digital streams maintains the tape-out's role as a high-stakes checkpoint, with any errors potentially delaying production by months.

Supporting Tools

Viewers and Editors

GDSII viewers and editors are specialized software tools that allow semiconductor designers to visualize, inspect, and modify layout data stored in the binary stream format, facilitating tasks such as design review, debugging, and iterative refinement. These applications parse the hierarchical structure of GDSII files to render geometric primitives like polygons and paths on layers, enabling precise manipulation within electronic design automation (EDA) environments. By supporting features tailored to the format's precision requirements, such tools bridge the gap between abstract design data and tangible layout analysis.^[31] Among free and open-source options, KLayout stands out as a robust viewer and editor for GDSII files, offering fast rendering of large layouts and support for hierarchy zooming to efficiently navigate multi-level designs.^[31] Its open-source nature allows community-driven enhancements, including in-place editing capabilities for drawing and transforming hierarchical elements directly within the viewer interface.^[31] Similarly, LayoutEditor provides cross-platform access to GDSII editing, with annotation tools that enable users to add markers, notes, and visualizations for collaborative design workflows.^[32] The tool excels in handling multi-gigabyte GDSII files with real-time performance, incorporating layer-based annotations and measurement functionalities to assess design dimensions accurately.^[33] Commercial solutions offer advanced editing for professional-grade applications. Cadence Virtuoso Layout Suite delivers comprehensive editing of GDSII layouts, featuring connectivity-driven tools for interactive modification, multi-threaded processing, and in-design verification to streamline custom IC development.^[34] It supports GDSII import and export, allowing seamless integration into broader EDA flows for analog and mixed-signal designs. Synopsys Custom Compiler, part of the Custom Design Platform, enables advanced manipulation of GDSII data through visually assisted automation, schematic-to-layout editing, and support for multi-technology nodes down to 3nm.^[35]^[36] This tool facilitates precise layout adjustments and analysis, optimizing for performance in analog, RF, and mixed-signal circuits.^[37] Key features across these tools include layer toggling to isolate specific design layers for focused inspection, integrated measurement tools for verifying distances and areas, and options for 3D visualization. For instance, gds2pov converts GDSII files into POV-Ray scene descriptions, enabling 3D extrusion and ray-traced rendering of layouts for enhanced spatial understanding.^[38] These capabilities rely on interpreting the GDSII file's record structure, as detailed in the File Format Specifications section.

Conversion and Analysis Utilities

Conversion tools for GDSII facilitate the transformation of binary stream files into other formats, enabling interoperability with diverse software ecosystems and aiding in debugging processes. The gdspy Python library (now in maintenance mode since version 1.6, with development focused on bug fixes and users encouraged to migrate to its successor gdstk) provides robust capabilities for importing, exporting, and manipulating GDSII files, supporting operations such as polygon creation, boolean merging, and hierarchical cell management to convert data into formats suitable for scripting and analysis workflows.^[39]^[40] Similarly, Artwork's gds2ascii utility converts binary GDSII streams into human-readable ASCII text files, which is particularly useful for debugging layout issues by allowing inspection of records like boundaries, paths, and references without specialized viewers.^[41] Analysis utilities extend GDSII processing by performing verification and extracting quantitative insights from layout data. Magic VLSI, an open-source tool from Open Circuit Design, integrates design rule checking (DRC) directly on GDSII imports, enforcing scalable CMOS rules to identify violations in real-time during layout analysis while preserving hierarchy.^[42] For comprehensive sign-off verification, Siemens' Calibre platform (formerly Mentor Graphics) processes GDSII files through advanced DRC, layout-versus-schematic (LVS), and physical verification flows, ensuring compliance with manufacturing constraints in high-density designs. In hybrid workflows combining GDSII with OASIS formats, tools like gdstk enable efficient polygon and area counting scripts by parsing both standards, reducing file sizes and computation times for statistical reports such as total geometry counts across layers.^[43] Open-source C++ libraries further support parsing and statistical analysis of GDSII data. The libGDSII library offers low-level record parsing for extracting structural elements, facilitating custom scripts to generate reports on layer usage, cell hierarchies, and polygon distributions without full layout rendering.^[44] These utilities collectively streamline data transformation and insight generation, bridging GDSII's legacy format with modern computational needs in electronic design automation.

Limitations and Alternatives

Technical Constraints

The GDSII format utilizes 32-bit signed integers for all coordinate representations, confining precision to discrete steps defined by the user-specified database unit (DBU), typically 1 nanometer for contemporary semiconductor processes. This integer-only system precludes direct support for sub-nanometer resolutions without adjusting the DBU to smaller values, such as 0.1 nm, which in turn diminishes the overall spatial extent. With a standard DBU of 1 nm, the maximum coordinate range spans from -2,147,483,648 to +2,147,483,647 units, equivalent to approximately ±2.1 meters, a limitation that proves inadequate for expansive layouts like large-area displays or panels exceeding this scale without resorting to coordinate scaling or file segmentation.^[45]^[4]^[27] Furthermore, GDSII provides no native primitives for true curves or arcs, necessitating their approximation through paths—straight-line segments with specified widths—or multi-segment polygons, which can inflate data volume and complicate rendering accuracy. Layer and datatype assignments use 16-bit signed integers, allowing up to 65,536 unique layers and datatypes each (typically 0–65535), though practical limits in tools and processes often cap usage at 256 unique layers and 256 datatypes, a constraint that can hamper scalability for advanced manufacturing processes involving 3D integrated circuits or multi-layer stacking, where far more categorical distinctions are required.^[46] The hierarchical structure of GDSII, while promoting design reuse through nested structure references, introduces significant computational demands during operations like flattening, where deep nesting levels require recursive traversal and expansion, potentially escalating processing times exponentially for complex designs. Absent any integrated compression mechanisms, file sizes swell dramatically for cutting-edge nodes; for instance, 3 nm system-on-chip layouts routinely surpass 100 GB, with some exceeding 200 GB, exacerbating challenges in storage, transmission, and tool handling.^[47]^[14]

Modern Successors

The Open Artwork System Interchange Standard (OASIS), standardized by SEMI as P39 in 2004, serves as a primary modern successor to GDSII, addressing key limitations in data efficiency and expressiveness for photomask layout interchange. This binary format supports hierarchical structures with variable-length encoding for coordinates and properties, enabling up to 20-fold file size reductions compared to GDSII through repetition records that compactly represent arrays and boundaries. Additionally, OASIS incorporates CBLOCK records for internal GZIP compression of cell definitions, further minimizing storage and processing demands for large-scale designs. Unlike GDSII's 65,536-layer limit (often constrained to 256 effective layers via datatype pairings), OASIS employs 32-bit layer numbering, accommodating millions of layers to handle the complexity of advanced nodes. OASIS also advances geometric representation by supporting curvilinear elements via the experimental SEMI P49 MULTIGON extension, which defines splines and Bézier curves for precise modeling of non-Manhattan shapes critical in inverse lithography techniques. This capability is particularly relevant for extreme ultraviolet (EUV) mask preparation, where curvilinear data reduces approximation errors and data volume in optical proximity correction flows. Adoption has accelerated since the 2010s for EUV processes at 7nm and below; as of 2024, OASIS adoption continues to grow for advanced nodes, with SEMI P49 extensions enabling native curvilinear support in EUV mask preparation.^[48] All major foundries and EDA vendors provide native support, though GDSII endures for legacy compatibility in simpler or smaller designs. Transition challenges include maintaining dual-format tool compatibility to avoid conversion-induced precision loss or hierarchy disruptions, as well as retraining workflows accustomed to GDSII's fixed-length simplicity. Beyond OASIS, alternative formats target specific aspects of design exchange and tool interoperability. The Library Exchange Format (LEF) and Design Exchange Format (DEF), jointly maintained since the 1990s, enable abstract physical data sharing in ASCII text; LEF describes process technology, standard cells, and macros (e.g., pin locations and routing layers), while DEF captures netlists, placements, and routing for place-and-route handoff, facilitating modular IC flows without full geometric detail. For in-memory operations, the OpenAccess database—developed by the OpenAccess Coalition including Cadence and Synopsys—provides a standardized API and schema for real-time EDA data access, supporting hierarchical layouts and multi-user collaboration to bypass file-based bottlenecks in custom design environments. These successors collectively mitigate GDSII's scalability issues, with OASIS leading for detailed mask data and LEF/DEF plus OpenAccess emphasizing upstream abstraction and integration.

References

[1]
GDSII | LayoutEditor Documentation
GDS II is a database file format which is the industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file format ...
[2]
GDSII - AnySilicon Semipedia
GDSII stands for Graphic Data System II, a binary file format originally developed for the accurate representation of integrated circuit designs. It captured ...
[3]
All About Calma's GDSII Stream Format - Artwork Conversion Software
GDSII is an integer database. The basic unit of measurement is a nanometer (10 -9 meter) Since four byte signed integers are used to describe a coordinate.
[4]
From GDSII to OASIS - Electronic Design Automation - Xyalis
Aug 1, 2008 · GDSII was introduced by Calma in 1978 as a successor of GDS format created in 1971. Since almost 30 years, no major change have been made to ...
[5]
Going from GDSII to OASIS - Design And Reuse
Aug 4, 2008 · GDSII was introduced by Calma in 1978 as a successor of GDS format created in 1971. Since almost 30 years, no major change have been made to ...
[6]
From Concept to GDSII: A Deep Dive into the VLSI Design Flow
Jan 3, 2025 · The final step in the VLSI design flow is the generation of the GDSII file, which is the standard format used for IC manufacturing. This file ...
[7]
ASIC Design Flow in VLSI Engineering Services – A Quick Guide
Jun 4, 2019 · Step 11. GDS II – Graphical Data Stream Information Interchange. In the last stage of the tapeout, the engineer performs wafer processing, ...
[8]
What is Electronic Design Automation (EDA)? – How it Works
The three primary companies leading this phase were Synopsys, Cadence, and Mentor (now Siemens EDA). This phase saw the birth of the term EDA (electronic design ...
[9]
Tapeout in Semiconductor Manufacturing: An In-depth Exploration
Jan 19, 2024 · The tapeout event involves sending the final design data to the foundry. This data, known as the GDSII file, contains the geometric descriptions ...
[10]
Cadence RTL-to-GDSII Flow Training Course
In this course, you learn how to implement a design from RTL-to-GDSII using Cadence tools. You will start by coding a design in VHDL or Verilog.Cadence Rtl-To-Gdsii Flow... · Learning Objectives · Software Used In This CourseMissing: Mentor Graphics<|control11|><|separator|>
[11]
From Design to Silicon: A Deep Dive into Tapeout, GDS-II, and Mask ...
May 16, 2025 · Tapeout is the final design phase, GDS-II is the physical layout file, and mask set is photomasks for transferring design patterns.
[12]
Calma Company - History of CAD - Shapr3D
Introduced in 1980, it initially required the use of Calma's Vector Memory Display (VMD). With the availability of GDS II Release 4.0, voice input was available ...Expanding Ddm Into The Aec... · Overview Of Calma's Product... · Calma's Mechanical Products...Missing: origins | Show results with:origins
[13]
Going from GDSII to OASIS - EE Times
Aug 4, 2008 · GDSII was introduced by Calma in 1978 as a successor of GDS format created in 1971. Since almost 30 years, no major change have been made to ...Missing: origins | Show results with:origins
[14]
Why Do Layout Designers Say "Stream Out"? - Cadence Blogs
Dec 2, 2015 · The format that the design was stored in was known as GDSII stream format, and so saving the design back to tape was called "stream out", ...
[15]
The GDSII Stream Format - VLSI - Automation...
Dec 15, 2011 · GDS = Graphic Database System. Initially, GDSII was designed as a format used to control integrated circuit photomask plotting.
[16]
[PDF] Photomask - SPIE
GDS pattern format became the de facto standard by the mid- eighties. A conversion step to a machine-proprietary format like. Mask Writer, Mask Inspection ...
[17]
GDSII, the data format for chip and integrated circuit design - WELSIM
Nov 1, 2023 · GDSII, short for Graphic Design System, is a data format used for the exchange of integrated circuit or layout data in Electronic Design ...Gdsii Format · Path Element · Sref Element
[18]
Cadence Acquires Valid Logic Systems | Mergr M&A Deal Summary
On December 31, 1991, Cadence acquired semiconductors company Valid Logic Systems. Acquisition Highlights. This is Cadence's 2nd transaction in the ...
[19]
GDS stream version - Custom IC Design - Cadence Community
Mar 9, 2010 · The last format version is generically called 7 which has lots of the limits removed. In this version, polygons can have more than 200 points, ...Missing: 1989 | Show results with:1989
[20]
Oasis comes up short as GDSII replacement - EDN Network
Feb 19, 2007 · Another reason I think GDSII needs replacement is its lack of sufficiency. In this respect, Oasis provides some additional features over GDSII.Missing: revisions | Show results with:revisions
[21]
Deployment of OASIS In The Semiconductor Industry
Mar 19, 2014 · With a demonstrated benefit of roughly 10x over the GDSII format, it was expected that the new OASIS format would be embraced quickly by the ...
[22]
[PDF] GDSII™ St-ream Format Manual
Jul 12, 1985 · Defines the format type of a Stream tape in two bytes. The two possible values are: 0 for Archive format, 1 for Filtered format. An Archive ...Missing: 1978 | Show results with:1978
[23]
CHAPTER 1 GDSII format - Boolean klaas holwerda
GDSII Stream format is the standard file format for transfering/archiving 2D graphical design data. It contains a hiearchy of structures.
[24]
Getting Started — gdspy 1.6.13 documentation
GDSII files contain a hierarchical representation of any polygonal geometry. They are mainly used in the microelectronics industry for the design of mask ...Polygons · Paths · Integrated Photonics
[25]
All About Calma's GDSII Stream File Format [3]
GDSII BOUNDARY. The GDSII BOUNDARY record (geometric entity) is one of the two key geometries used to describe the layout (the other being the PATH). The ...Missing: primitives | Show results with:primitives
[26]
All About Calma's GDSII Stream File Format [4]
### Summary of GDSII PATH Record
[27]
IC Compiler II: Place & Route Solution - Synopsys
Synopsys IC Compiler II is the industry leading place and route solution that delivers best-in-class quality-of-results (QoR) for next generation designs.Missing: GDSII export
[28]
Physical Verification: IC Validator - Synopsys
Boost productivity with Synopsys IC Validator. Achieve accurate, fast physical verification for all process nodes with seamless integration and scalability.<|control11|><|separator|>
[29]
Synopsys Full EDA Flow First to Achieve Samsung Foundry 4LPP ...
Nov 17, 2021 · As the first EDA vendor to achieve full-flow certification for the 4LPP process via the SAFE-QEDA program, Synopsys is poised to accelerate ...
[30]
KLayout Layout Viewer And Editor
Start KLayout in viewer mode for an accurate and fast viewer for big mask layout files. It can read GDS2, OASIS, DXF, CIF, Gerber, LEF/DEF and other formats.Download or Build Yourself · KLayout Project · Documentation · KLayout Basics
[31]
LayoutEditor the universal editor for GDSII, OpenAccess, OASIS ...
The LayoutEditor is the most popular software to edit designs for MEMS and IC fabrication. It is also often be used for Multi-Chip-Modules (MCM), Chip-on-Board ...Download · Licenses for the Full and... · Features · Support ForumMissing: Cadence Virtuoso Synopsys gds2pov
[32]
Features | LayoutEditor
### Extracted Features Summary
[33]
Virtuoso Layout Suite - Cadence
Virtuoso Layout Suite speeds custom IC layout with differentiated analog, digital, and mixed-signal designs at device, cell, block, and chip levels.
[34]
[PDF] Virtuoso® Layout Editor
Apr 6, 2005 · You can open a design window by using either the Open File form or the. Library Manager. The Library Manager allows you to edit the data inside ...
[35]
Custom Compiler Design Environment - Synopsys
The Synopsys Custom Compiler design environment is a modern solution for full-custom analog, custom digital, and mixed-signal IC design.Missing: GDSII export<|separator|>
[36]
[PDF] Custom Compiler | Synopsys
Custom Compiler is a solution for IC design, providing design entry, simulation, analysis, and layout editing, including visually-assisted automation.
[37]
ralight/gds2pov - GitHub
GDS2POV is a program to take a GDS2 layout file and output a POV-Ray scene description file of the GDS2 data. This allows the creation of attractive 3D ...
[38]
Gdspy's Documentation — gdspy 1.6.13 documentation
gdspy is a Python module that allows the creation of GDSII stream files. Most features of the GDSII format are implemented, including support for polygons.
[39]
GDS2ASCII - Bi-directional translator - Artwork Conversion Software
GDS2ASCII is a utility program that converts the binary GDSII stream format into an ASCII file. Once in ASCII the designer can use a variety of powerful tools.
[40]
Magic VLSI - Open Circuit Design
Oct 28, 2025 · Magic version 8.3 is the official current released version of the program, a combined effort of the "Magic Development Team". Development ...Magic Documentation Page · Release Notes · Magic Development · Download PageMissing: DRC GDSII
[41]
gdstk 0.9.61 documentation
Gdstk (GDSII Tool Kit) is a C++ library for creation and manipulation of GDSII and OASIS files. It is also available as a Python module meant to be a successor ...Python API Reference · Getting Started · How-Tos · C++ Reference<|separator|>
[42]
HomerReid/libGDSII: C++ library and command-line utility ... - GitHub
libGDSII is a C++ library for working with GDSII binary data files, intended primarily for use with the computational electromagnetism codes scuff-em and meep.Missing: parsing | Show results with:parsing
[43]
[PDF] GDS II - Bitsavers.org
Among the features and facilities described in the following pages are: 32-bit integer coordinate space to support VLSI . •Databases with information ...
[44]
Circle Recognition in GDSII to Gerber - Artwork Conversion Software
Introduction. The GDSII specification does not contain any circle or arc entity. A round pad in the GDSII world is approximated by using a polygon of anywhere ...<|control11|><|separator|>
[45]
GDSII Layer Mapping - WRcad
Typically, the layer number and datatype can be in the range 0-255, or 0-63 for some older versions of the GDSII specification.Missing: limit | Show results with:limit
[46]
Design and implementation of a real-time hierarchical parallel ...
The file is 0.5 Mb in GDSII format and 6.1 Gb in flat- tened LBNL format. In the following benchmarks, the mas- ter processor was a 150 MHz Pentium™ and the ...