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Optical proximity correction

Optical proximity correction (OPC) is a photolithography enhancement technique in semiconductor manufacturing that compensates for image distortions on the wafer caused by optical effects such as diffraction, interference, and process variations by modifying the geometrical shapes on the photomask.^[1] These modifications, often including added sub-resolution assist features or edge adjustments, ensure that the printed patterns on the silicon substrate accurately reproduce the intended integrated circuit design despite the limitations of light wavelengths longer than modern feature sizes.^[2] OPC is essential for achieving the high fidelity required in advanced nodes, where critical dimensions are below 10 nanometers, enabling continued scaling under Moore's Law.^[3] Developed in the late 1980s as feature sizes approached the wavelength of exposure light, OPC initially used simple rule-based methods to bias line widths and spaces based on proximity to neighboring patterns.^[4] By the early 2000s, as lithography pushed toward 130 nm and below, model-based OPC (MB-OPC) became standard, employing simulations of the optical imaging process to predict and correct distortions more precisely.^[5] This evolution was driven by the need to mitigate proximity effects in dense logic and memory devices, where uncorrected images could lead to systematic yield losses.^[6] In contemporary applications, OPC integrates with other resolution enhancement technologies like sub-resolution assist features (SRAFs) and source mask optimization (SMO), particularly in extreme ultraviolet (EUV) lithography for nodes at 5 nm and beyond.^[7] Computational demands have spurred advancements, including machine learning-accelerated models that reduce turnaround times while maintaining edge placement accuracy below 1 nm. Despite these improvements, challenges persist in handling stochastic noise and curvilinear masks, underscoring OPC's ongoing role in enabling reliable high-volume manufacturing of complex chips.^[8]

Basic Principles

Proximity Effects in Lithography

In photolithography, proximity effects arise primarily from diffraction, where light waves passing through the photomask undergo bending and spreading at pattern edges, leading to interference patterns that distort the aerial image on the wafer. These interference effects occur because the photomask features act as apertures that diffract incoming light into various orders, with only a limited number captured by the projection lens, resulting in incomplete reconstruction of the intended pattern. Near edges of mask features, constructive and destructive interference between diffracted waves alters the intensity profile, causing variations in the printed linewidth and shape depending on the proximity of adjacent structures.^[9]^[10] Key manifestations of these proximity effects include line-end shortening, where the ends of linear features print shorter than designed due to reduced intensity at terminations from diffracted light spillover; corner rounding, in which sharp 90-degree corners on the mask appear smoothed in the resist image because of intensity gradients at the vertices; and density-dependent critical dimension (CD) variations, where the printed width of features changes based on local pattern density, such as isolated lines printing wider than those in dense arrays. For instance, in a typical i-line lithography setup with 365 nm wavelength and 0.52 numerical aperture, a 0.5 μm isolated line may exhibit a wider aerial image intensity profile compared to the same feature in a dense grating, leading to an iso-dense bias of up to 50 nm or more as resolution approaches the diffraction limit. These distortions become pronounced when feature sizes shrink relative to the wavelength, exacerbating the need for corrective measures.^[11]^[9] The fundamental limit of resolution in lithography is described by the Rayleigh criterion, given by

R = k_1 \frac{\lambda}{\mathrm{NA}},

where R is the minimum resolvable feature size, \lambda is the wavelength of the exposing light, \mathrm{NA} is the numerical aperture of the imaging system (a measure of its light-gathering capability), and k_1 is a process-dependent factor typically ranging from 0.25 to 1.0. This equation highlights how diffraction inherently constrains pattern fidelity, with proximity effects intensifying as R approaches smaller values through reduced \lambda or increased \mathrm{NA}.^[12] These proximity effects were first observed in the early integrated circuit fabrication processes of the 1970s, as feature sizes began scaling below 5 μm and optical modeling revealed diffraction-induced distortions in early projection systems. By the 1980s, with the adoption of step-and-repeat scanners and shorter wavelengths, empirical adjustments to mask patterns emerged as initial strategies to mitigate these issues, paving the way for more systematic corrections in advanced nodes.^[13]^[14]

Role and Objectives of OPC

Optical proximity correction (OPC) is a resolution enhancement technique in photolithography that modifies photomask patterns by incorporating auxiliary geometries, such as serifs at corners and hammerheads at line ends, to compensate for diffraction-induced distortions and proximity effects during wafer patterning.^[15] These modifications pre-distort the mask to ensure the final printed features on the silicon wafer more accurately replicate the original integrated circuit design intent.^[16] The primary objectives of OPC are to achieve precise critical dimension (CD) control and edge placement accuracy, minimizing deviations such as line-end shortening to maintain pattern fidelity within manufacturing tolerances, typically targeting edge placement errors below 10 nm for advanced nodes.^[4] By enhancing the process window—specifically through increased depth of focus and exposure latitude—OPC improves yield and robustness against variations in lithography conditions, enabling reliable production at sub-wavelength feature sizes.^[15] At a high level, the OPC workflow involves fracturing the design data into polygons, simulating aerial images to predict optical distortions, and iteratively adjusting mask features until the simulated wafer image aligns with target specifications.^[4] This approach delivers key benefits, including the ability to scale semiconductor technology to smaller nodes without immediate upgrades to exposure tools, while recovering approximately 20% of edge placement accuracy by reducing mean and standard deviation errors in feature positioning.^[17] OPC was first commercialized in the 1990s by Numerical Technologies (subsequently acquired by Synopsys), marking a pivotal advancement in mask engineering for high-volume IC manufacturing.^[18]

Key Imaging Distortions

Resolution Limits and the k1 Factor

In optical lithography, the fundamental limit of pattern resolution is described by Rayleigh's criterion, which defines the minimum resolvable half-pitch R = k_1 \frac{\lambda}{\mathrm{NA}}, where \lambda is the wavelength of the illumination light, NA is the numerical aperture of the projection optics, and k_1 is the process factor encapsulating all enhancements and limitations beyond the basic optical system, such as mask design, resist properties, and illumination conditions.^[19] This equation arises from diffraction theory: for a circular aperture, the angular resolution limit is \theta = 1.22 \frac{\lambda}{D} (where D is the aperture diameter), corresponding to the point where the central maximum of the Airy diffraction pattern from one point source aligns with the first minimum of the adjacent pattern. In lithographic projection systems, NA = n \sin \alpha (with n the refractive index and \alpha the half-angle of the maximum cone of light), yielding the linear resolution R = 0.61 \frac{\lambda}{\mathrm{NA}} for coherent illumination; partial coherence and process optimizations adjust this to the general form with k_1 \approx 0.5 for conventional imaging, but values below 0.25 enter the diffraction-limited regime where image contrast approaches zero without advanced corrections like OPC.^[20]^[21] Over time, relentless scaling of semiconductor features has driven k_1 downward, reflecting the industry's push beyond optical limits through innovations in wavelength reduction and NA increases. In the 1980s, g-line lithography (\lambda = 436 nm) operated at k_1 \approx 0.8, supporting half-pitches around 1 \mum with minimal proximity distortions. By the 2020s, EUV lithography (\lambda = 13.5 nm) routinely achieves k_1 \approx 0.3, enabling half-pitches below 20 nm but demanding precise control of diffraction orders to maintain pattern fidelity.^[22]^[23] Decreasing k_1 intensifies proximity effects, as diffracted light from neighboring features increasingly overlaps, degrading aerial image contrast and causing critical dimension (CD) errors up to 50% in dense patterns—such as lines shrinking significantly relative to isolated ones—without OPC to compensate for these interactions.^[4] While lower k_1 enables finer resolution to support denser circuits, it narrows the process window by reducing tolerance to defocus and dose variations, often limiting exposure latitude to below 10% and depth of focus to tens of nanometers, thereby amplifying the need for robust OPC to widen the viable parameter space.^[24] For instance, in 5 nm nodes circa 2020 using DUV immersion lithography, k_1 \approx 0.28 approaches the practical limit, resulting in OPC convergence times of several hours per layer due to the extensive simulations required for accurate correction of complex, low-contrast images.^[21]^[25]

Illumination Coherence Effects

Illumination coherence in photolithography refers to the degree of spatial correlation in the light source, quantified by the partial coherence parameter σ, defined as the ratio of the illuminator numerical aperture to the projection lens numerical aperture, ranging from 0 (fully coherent) to 1 (fully incoherent).^[26] Low σ values, corresponding to more coherent illumination, enhance aerial image contrast for isolated features by promoting stronger interference, but they degrade contrast and intensify proximity distortions in dense patterns through amplified diffraction interactions.^[26] This trade-off arises because coherent light (low σ) admits fewer diffraction orders, improving resolution for sparse structures while exacerbating edge blurring and sidelobe printing in proximity-limited scenarios.^[27] Off-axis illumination schemes, such as annular sources, effectively reduce the average σ to boost the k1 resolution factor beyond conventional limits, enabling finer feature printing. However, these configurations introduce direction-dependent coherence, leading to asymmetric critical dimension (CD) variations in two-dimensional features like contact holes, where horizontal and vertical edges print with differing widths due to uneven diffraction capture.^[27] For instance, in annular illumination at σ ≈ 0.5–0.7, contact patterns can exhibit CD asymmetries up to 10–15% across orientations, necessitating targeted OPC to restore symmetry.^[28] The influence of partial coherence on image formation is mathematically captured by the Hopkins imaging model, where the aerial image intensity is expressed as:

I(\mathbf{x}) \propto \int J(\phi) \left| h(\mathbf{x}, \phi) \right|^2 \, d\phi

Here, J(\phi) represents the source intensity distribution over angles φ, and h(\mathbf{x}, \phi) is the coherent pupil function modulating the image at position \mathbf{x}.^[29] This integral highlights how source shape J(\phi) weights the contributions from different coherence states, directly affecting proximity distortions by altering the balance of diffracted light from adjacent mask features.^[29] In dipole illumination tailored for horizontal line patterns, isolated lines benefit from sharpened edges and higher contrast due to selective enhancement of relevant diffraction orders, while dense line arrays suffer relative blurring from incomplete order capture in the orthogonal direction. Such imbalances require OPC corrections, often involving subresolution features or biasing up to 20 nm, to equalize CD across pitch variations and prevent printability failures in logic gates.^[30] The management of coherence effects has progressed from empirical conventional illuminators in early nodes to computational source optimization in the 2010s, exemplified by Source Mask Optimization (SMO) techniques that iteratively refine J(\phi) alongside mask patterns to minimize coherence-induced asymmetries. SMO, introduced in tools like those from ASML and Synopsys around 2010, achieves up to 20–30% process window improvements by tailoring source shapes for balanced resolution and proximity control in sub-22 nm nodes.^[31] This evolution underscores the shift toward holistic RET integration, where coherence modulation directly informs OPC strategies.^[32]

Optical Aberrations

Optical aberrations in projection lithography systems stem from imperfections in the lens elements, causing deviations in the wavefront that distort the aerial image beyond diffraction limits alone. These aberrations are categorized into even and odd types based on their symmetry in the pupil plane, as described by Zernike polynomials. Even aberrations, including defocus (Zernike term Z₄) and spherical aberration, exhibit rotational symmetry and predominantly influence critical dimension (CD) uniformity by symmetrically blurring features. Odd aberrations, such as coma and astigmatism, lack this symmetry and primarily induce asymmetric distortions like pattern shifts, exacerbating proximity effects in off-axis field positions.^[33]^[34]^[35] The wavefront aberration, expressed as optical path difference (OPD), is mathematically represented using Zernike polynomials:

\text{OPD}(\rho, \theta) = \sum_{n=1}^{N} a_n Z_n(\rho, \theta)

where a_n are the aberration coefficients, \rho is the normalized radial coordinate, and \theta is the azimuthal angle in the unit pupil. This deviation reduces image quality, quantified by the Strehl ratio S \approx 1 - (2\pi \sigma / \lambda)^2, where \sigma is the root-mean-square (RMS) wavefront error and \lambda is the wavelength; a Strehl ratio below 0.8 indicates significant degradation in peak intensity and contrast.^[35] In 193 nm immersion scanners, residual aberrations typically induce across-field CD variations of 3-5%, with higher impacts in peripheral field regions where proximity effects from adjacent features are amplified. For instance, coma aberration can cause line-end shortening or shifts on the order of 10-20 nm in patterns at 7 nm nodes, leading to overlay errors and reduced process margins.^[36]^[37] Optical proximity correction (OPC) addresses these distortions preemptively by adjusting mask features to counteract aberration-induced shifts, though optimal results require concurrent scanner tuning to minimize wavefront errors. Even with partial coherence from illumination shaping, aberrations dominate distortion in high-numerical-aperture systems.^[38] By the 2020s, extreme ultraviolet (EUV) lithography tools from ASML have achieved aberration specifications below 1 nm RMS wavefront error, enabling tighter control for sub-5 nm nodes compared to earlier 193 nm systems.^[39]

OPC Methodologies

Rule-Based OPC

Rule-based optical proximity correction (OPC) applies predefined geometric rules to adjust mask patterns, compensating for diffraction-induced distortions such as line-end shortening and corner rounding without relying on real-time simulations. These rules, derived from empirical observations of pattern behavior, dictate specific modifications like adding serifs to corners or extending line ends based on local features such as pitch and density, making it well-suited for one-dimensional or sparse patterns where interactions are predictable.^[4]^[6] The process begins with rule development, where experimental data from test structures or preliminary simulations identify correction values for common geometries, forming a lookup table indexed by parameters like line width and spacing. The integrated circuit layout is then fragmented into small edge segments, and a pattern recognition algorithm scans for matching configurations to apply the corresponding adjustments automatically, ensuring consistent corrections across the design. For example, rules may add serifs to acute corners or extend line ends to sharpen printed features in less dense areas.^[4] This approach offers significant advantages in speed and simplicity, enabling full-chip corrections in seconds on standard hardware and producing masks with minimal additional data volume compared to uncorrected designs. However, its limitations become evident in complex two-dimensional layouts, where rules fail to capture intricate interactions, leading to inaccuracies; moreover, as feature sizes shrank, the number of required rules exploded to thousands by the 130 nm node, complicating maintenance and increasing error risks.^[4]^[6] Historically, rule-based OPC emerged in the late 1980s and early 1990s, with seminal automated implementations like those by Otto et al. enabling its adoption for 0.35 μm processes to address proximity effects in i-line lithography. It dominated corrections for non-critical layers through the 1990s but was largely phased out for critical layers by the early 2000s as model-based methods proved necessary for sub-130 nm nodes. Line-end extension rules, for instance, typically lengthen ends to counteract shortening in isolated lines.^[4]

Model-Based OPC

Model-based optical proximity correction (MBOPC) employs detailed physical simulations of the lithography process to predict pattern distortions and iteratively adjust the mask design for accurate wafer printing. Unlike simpler rule-based approaches used for basic cases, MBOPC relies on computational models that account for diffraction, interference, and process variations to achieve sub-wavelength resolution. The core process begins with aerial image simulation, typically using the Hopkins equation for partially coherent illumination or Abbe theory for coherent approximations, which computes the intensity distribution at the wafer plane. These simulations are coupled with resist models, such as the Mack threshold model, to predict the developed resist contours and identify deviations from the target layout.^[40]^[41] The aerial image intensity I(x,y) for coherent imaging is derived from the transfer function formulation:

I(x,y) = \left| \int P(f_x, f_y) \, M(f_x, f_y) \, \exp\left(i 2\pi (f_x x + f_y y)\right) \, df_x \, df_y \right|^2

where P(f_x, f_y) represents the pupil function of the optical system, and M(f_x, f_y) is the mask transmission function in the spatial frequency domain. This equation captures the interference of diffracted light waves, enabling precise prediction of proximity-induced blurring and corner rounding in the printed image. For partially coherent systems, the Hopkins formulation extends this by integrating over the illumination source. The workflow of MBOPC involves segmenting the mask edges into fragments, simulating the aerial image and resist contours for each iteration, and optimizing corrections to minimize edge placement errors (EPE). This optimization often uses least-squares methods to reduce the overall EPE across the layout, with convergence achieved when the root-mean-square (RMS) error falls below thresholds like 2 nm. The process iterates until the simulated contours match the target within specified tolerances, ensuring high fidelity for complex patterns. In advanced implementations, inverse lithography technology (ILT)—an evolution of MB-OPC—formulates mask optimization as an inverse imaging problem to generate curvilinear masks for better fidelity at sub-7 nm nodes.^[42]^[43]^[18] MBOPC excels in handling two-dimensional effects, such as line-end shortening and density-dependent interactions, which rule-based methods struggle with in dense layouts. Commercial tools like Calibre from Mentor Graphics (introduced in the late 1990s) and Proteus from Synopsys (deployed since the mid-1990s) implement these simulations, enabling full-chip corrections with integrated verification. In advanced 3 nm nodes (production as of 2022), MBOPC runtimes for full-chip layers typically require thousands to millions of CPU-hours, reflecting significant increases in model complexity to account for EUV-specific effects like stochastic noise and multi-patterning interactions.^[44]^[6]

Advanced Techniques

Subresolution Assist Features

Subresolution assist features (SRAFs), also known as scattering bars, are non-printing elements added to photomasks in optical lithography. These features consist of narrow lines or spaces, typically smaller than the resolution limit defined by k_1 \lambda / \mathrm{NA} (where k_1 is the process factor, \lambda is the wavelength, and NA is the numerical aperture), and are strategically placed adjacent to isolated or semi-isolated main features to equalize aerial images across varying pattern densities.^[45] By creating a more periodic local environment, SRAFs prevent the weaker imaging of isolated features compared to dense arrays, thereby enhancing overall pattern fidelity without themselves resolving on the wafer.^[46] The mechanism of SRAFs relies on optical interference: they diffract light in a way that boosts the aerial image contrast for primary features by simulating denser patterning conditions, particularly under off-axis illumination schemes like quadrupole sources. This increased local periodicity improves the focus response and reduces iso-dense bias, with placement rules often centering SRAFs at pitches around 1.5 to 2 times the main feature pitch to optimize interference without printing— for instance, a 50 nm wafer-scale SRAF at a 260 nm optimized pitch. Quantitative benefits include a contrast boost that can widen the overlapping depth of focus by approximately 33%, from 0.3 μm to 0.4 μm for isolated lines, thereby enhancing the process window for lines and spaces.^[45]^[47] SRAFs are integrated into model-based optical proximity correction (OPC) workflows, where calibrated lithography models simulate and optimize their size, position, and number alongside main feature adjustments to maximize image quality. Verification occurs through simulated aerial image contours and wafer-level testing to ensure non-printability while confirming process window gains, such as reduced critical dimension (CD) variations across pitches. In advanced nodes like 45 nm, SRAFs have been shown to reduce CD variations in contact holes, stabilizing patterns against proximity effects.^[48]^[49] In the EUV era, SRAFs continue to be employed, particularly in hybrid DUV-EUV workflows for enhancing pattern fidelity in advanced nodes.^[50] Originally evolving from assist features introduced in phase-shifting masks during the early 1990s, SRAFs have become a standard resolution enhancement technique in deep ultraviolet (DUV) lithography, particularly for logic layers in semiconductor manufacturing below 100 nm nodes.^[46]^[51]

Integration with Multiple Patterning

Multiple patterning techniques, including litho-etch-litho-etch (LELE) double patterning and self-aligned double patterning (SADP), enable the fabrication of features with half-pitches below 80 nm using 193 nm immersion lithography by decomposing dense layouts into multiple masks.^[52]^[53] In quadruple patterning variants, such as self-aligned quadruple patterning (SAQP), the process extends this decomposition to four masks for even denser patterns, with optical proximity correction (OPC) applied independently to each mask to mitigate proximity effects arising from the specific exposure and neighboring features in that step.^[52] This per-mask OPC ensures that the printed patterns from successive exposures align and combine accurately to form the target layout, addressing distortions that would otherwise limit resolution due to the k1 factor constraints in single-exposure lithography.^[52] A primary challenge in integrating OPC with multiple patterning is managing overlay errors, which must be controlled within 1-2 nm tolerances to prevent amplification of proximity distortions across exposures.^[54]^[55] Even minor misalignments can cause critical dimension (CD) variations by altering the effective spacing between patterns from different masks, leading to over- or under-etching in merged regions. Additionally, stitch conflicts arise at pattern cut boundaries, where features from adjacent masks meet, potentially creating gaps or shorts if OPC does not account for these interfaces, thus requiring iterative verification to maintain pattern fidelity.^[56]^[57] OPC in multiple patterning relies on model-based decomposition algorithms that enforce spacing rules, such as minimum cut widths exceeding 20 nm, to ensure conflict-free mask assignment and predictable merging during fabrication.^[58] These models simulate the full multi-step process, optimizing mask patterns to counteract interactions between exposures. For instance, in 10 nm FinFET devices using SADP for gate patterning, OPC compensates for CD shifts induced by proximity to features from prior or subsequent exposures, preserving fin width uniformity critical for device performance.^[59] Multiple etch steps in these processes introduce further complexities, as plasma loading variations—arising from differing pattern densities across masks—can produce etch bias, nonuniformly altering feature profiles.^[60]^[61] OPC addresses this by incorporating etch proximity models that pre-compensate for loading effects, simulating plasma chemistry and ion flux to adjust mask features proactively and minimize post-etch CD deviations. Historically, multiple patterning with integrated OPC was essential for 7 nm node production starting in 2018, enabling sub-40 nm pitches before extreme ultraviolet (EUV) lithography became viable for high-volume manufacturing; as of 2025, it persists in hybrid DUV-EUV flows for select layers.^[62]^[63]^[50]

Modern Applications and Challenges

OPC in Advanced Nodes

In sub-7 nm semiconductor processes, such as the 5 nm and 3 nm nodes introduced between 2020 and 2023, optical proximity correction (OPC) has evolved to address the unique challenges of extreme ultraviolet (EUV) lithography, particularly stochastic noise arising from photon shot noise and secondary electron blur.^[64] This noise contributes to line edge roughness (LER) values typically in the 3-5 nm range for initial EUV implementations, impacting pattern fidelity and yield in dense logic and memory structures.^[65] OPC algorithms now incorporate stochastic-aware models to predict and mitigate these variations, shifting from deterministic approaches to ones that simulate photon and electron statistics for more accurate edge corrections.^[8] The computational demands of OPC in these nodes have escalated dramatically due to the need for high-fidelity simulations across complex layouts. Full-chip OPC processing can generate data volumes exceeding 60 GB per mask and require runtimes of 30+ hours on conventional hardware, often extending to days for iterative refinements in EUV flows. To counter this, GPU acceleration has become standard, enabling 10x or greater speedups in model-based OPC and inverse lithography techniques (ILT) for 3 nm and below, as adopted by leading foundries.^[66] Edge placement error (EPE) targets have tightened to below 2 nm (3σ) to ensure device performance, with stochastic contributions alone accounting for 2-3 nm shifts in critical features without advanced correction.^[67] Industry leaders like TSMC and Samsung integrate OPC deeply into their EUV-based 5 nm and 3 nm processes, combining it with design for manufacturability (DFM) flows to optimize yield and variability.^[68] For instance, TSMC's N3 platform employs EUV single patterning with OPC to achieve approximately 70% logic density improvements over the N5 node, while Samsung's 3 nm GAA process relies on similar corrections for gate-all-around structures.^[69]^[70] Post-2020 advancements in stochastic OPC, validated through wafer-level experiments, have reduced defect probabilities by 1-2 orders of magnitude (e.g., >90% fewer stochastic failures in SRAM and logic), using compact models with sub-1 nm fitting errors for efficient full-chip application.^[8] This integration with DFM ensures holistic control over process variations, from mask design to final patterning.^[71]

Future Trends in Computational Lithography

Inverse lithography technology (ILT) represents a paradigm shift in computational lithography by treating mask design as an inverse problem, where the goal is to optimize a pixelated mask to produce a desired wafer pattern despite optical distortions. In ILT, the mask is represented as a dense grid of pixels, each with adjustable transmittance values, enabling fine-grained control over the aerial image formation. Optimization proceeds through iterative algorithms, such as gradient descent, that adjust pixel values to minimize discrepancies between the simulated printed contour and the target layout, often incorporating level-set methods to evolve mask boundaries smoothly.^[6]^[72] The core of ILT optimization involves solving a cost function that quantifies the mismatch between the simulated and target images. A typical formulation minimizes the L2 norm of the difference:

F\{M(\mathbf{r})\} = \|\mathbf{Z}(\mathbf{r}) - \tilde{\mathbf{Z}}(\mathbf{r})\|_2^2

where \mathbf{Z}(\mathbf{r}) is the simulated imaged pattern from mask M, and \tilde{\mathbf{Z}}(\mathbf{r}) is the target pattern; manufacturability is enforced via constraints like limiting pixelated area coverage to under 10% to avoid excessive mask complexity.^[6]^[73] This approach outperforms traditional OPC by enabling curvilinear mask shapes that better compensate for diffraction effects in advanced nodes. Emerging trends in computational lithography emphasize AI and machine learning integration to accelerate ILT and OPC, particularly for beyond-2nm scaling. Neural networks, such as generative adversarial networks (GANs), predict mask corrections by learning from simulation data, achieving up to 50% runtime reduction compared to conventional ILT—for instance, GAN-OPC cuts processing time from 788.5 seconds to 371.3 seconds while reducing L2 error by 9%.^[6] Model-driven deep learning further enhances efficiency by embedding physical lithography models into neural architectures, yielding speedups exceeding 5x in model-based OPC through GPU-accelerated simulations.^[74] These AI-driven methods also support verification by predicting edge placement errors and process variations, addressing gaps in traditional rule checks for complex patterns. Hybrid extreme ultraviolet (EUV) systems with high numerical aperture (NA=0.55) are poised to integrate ILT for sub-2nm nodes, where source-mask optimization (SMO) refines pixelated masks to counter asymmetric aberrations and improve pattern fidelity. As of 2025, high-NA EUV systems are entering pilot production lines at leading foundries.^[6]^[75] However, curvilinear masks from ILT pose fabrication challenges, as their irregular shapes increase write times on conventional variable-shaped beam writers due to complex fracturing; multi-beam mask writers mitigate this by enabling constant write times independent of pattern density.^[76] In post-2025 logic nodes like 1.4nm, ILT has demonstrated doubled process windows compared to Manhattan geometries, recovering significant margins against variations in dose and focus.^[6]

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https://spiedigitallibrary.org/journals/Journal-of-MicroNanolithography-MEMS-and-MOEMS/volume-12/issue-4/043001/Extreme-ultraviolet-lithography-resist-based-aberration-metrology/10.1117/1.JMM.12.4.043001.full
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Optical Aberrations - RP Photonics
Types of Optical Aberrations · Defocus · Chromatic Aberrations · Spherical Aberrations · Astigmatism · Coma · Field Curvature · Image Distortion · Zernike Polynomials.
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[PDF] Zernike Polynomials
For a symmetrical optical system, the wave aberrations are symmetrical about the tangential plane and only even functions of q are allowed. In general, however, ...
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optical lithography into the millennium: sensitivity to aberrations ...
For a CD change, it seems reasonable to allow up to 5%. CD change due to the maximum lens aberration. For the pattern shift, a “rule of thumb” is usually ...
[37]
CD error caused by aberration and its possible compensation by ...
Mar 24, 2017 · Non-negligible critical dimension (CD) variation and position shift are obtained with the reported maximum 25 mλ of coma aberration.Missing: end | Show results with:end
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(PDF) Aberration evaluation and tolerancing of 193-nm lithographic ...
Aug 9, 2025 · Described here is an approach to aberration tolerancing utilizing aerial image parameterization based on photoresist capability.
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[PDF] 0.55 NA EUV lithography: Imaging & Overlay
All High NA mirrors are meeting design specs for wavefront aberrations, apodization, transmission and flare. Performance. Optics. Wavefront aberrations <0.23nm.Missing: <1nm 2020s
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Model based optical proximity correction runtime saving with ...
Dec 4, 2009 · The Hopkins equation is normally used to calculate aerial image intensities on a photomask for fast OPC models. In this section, the OPC ...
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[PDF] Development of Positive Photoresists - Semantic Scholar
A mechanism for the development of positive optical photoresists is proposed, leading to the derivation of a development rate equation.
[42]
[PDF] Fast Lithography Simulation under Focus Variations for OPC and ...
Hopkins Equation. The aerial image can be described by the Hopkins Equation12. I(f,g) = T(f. + f,g. + g; f ,g. )F(f. + f,g.
[43]
[PDF] Optical Proximity Correction with Linear Regression
Dec 2, 2007 · In comparison on the same computing platform, it takes 340 and 220 seconds to perform model based OPC without predictions for designs. A and B ...
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Method for optical proximity correction based on a vector imaging ...
Mar 27, 2024 · This paper proposes a model-based edge OPC method starting from the vector imaging model by establishing an analytical relationship between the ...
[45]
(PDF) An efficient method for transfer cross coefficient approximation ...
Aug 9, 2025 · Model Based Optical Proximity Correction (MBOPC) is since a decade a widely used technique that permits to achieve resolutions on silicon ...
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Siemens EDA celebrates 20 years of collaboration with imec
Mar 28, 2023 · In 1999, Mentor Graphics (now Siemens EDA) acquired a small ... released their first model-based OPC tool, Calibre OPCpro. The team ...Missing: date | Show results with:date
[47]
Synopsys optimizes OPC tool for Intel-based servers - EDN Network
Feb 27, 2007 · Anantha Sethuraman, VP of DFM marketing at Synopsys said the Proteus OPC engine has been in production for 10 years over seven consecutive ...
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https://www.researchgate.net/publication/283553601_Sub-resolution_assist_feature_SRAF_study_for_active_area_immersion_lithography
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[PDF] Optical lithography—a historical perspective
Nov 22, 2006 · In the late 1980s, step and repeat systems with reduction projection optics were introduced, also commonly known as 'steppers'. The reason for ...
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Imaging contrast improvement for 160-nm line features using subresolution assist features with binary, six percent ternary attenuated phase-shift mask with process-tuned resist
### Summary of Quantitative Results on Contrast Improvement Using SRAFs
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Sub-resolution assist feature (SRAF) study for active area immersion ...
Sub-resolution assistant feature (SRAF) is applied to enhance the process window of isolated and semi-isolated features by taking advantage of the optical ...<|control11|><|separator|>
[52]
[PDF] Inverse lithography for 45-nm-node contact holes at 1.35 numerical ...
The results also suggest that the process window may be enhanced by a high trans- mission PSM, shown in Fig. 13 as the lower average PV band area. 4.3 ...
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A History of Resolution Enhancement Technology - ResearchGate
Aug 10, 2025 · ... line end shortening and corner rounding. One established method to mitigate the impact of diffraction is optical proximity correction. This ...
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Multiple Patterning - Semiconductor Engineering
Multiple patterning enables chipmakers to image IC designs at 20nm and below. Basically, there are two main categories of multiple patterning: pitch splitting ...
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[PDF] Double Patterning
Nov 7, 2017 · Double patterning can further reduce pitch size without changing NA or 𝜆. R = 0.25 7 193. 1.35. ≈ 36 nm. 80 nm. 40 nm. Rasha ...
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Overlay error statistics for multiple-exposure patterning
Apr 4, 2019 · Results: The overlay error between two patterns is usually less than the root sum square of the two overlay error values of the patterns ...
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Overlay error components in double-patterning lithography
The remainder residual error of about 2nm should be more than adequate to handle 2Xnm and 1Xnm design rules, according to industry guidelines and prevailing ...
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Overlay Challenges On The Rise - Semiconductor Engineering
Nov 16, 2017 · The overlay metrology tool detects a misalignment in the layers or what's called an overlay error. A mishap with the scanner and mask can cause overlay errors.
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Impact of CD and overlay errors on double-patterning processes
Aug 9, 2025 · Double patterning (DP) is today the main solution to extend immersion lithography to the 32 nm node and beyond. Pitch splitting process with ...Missing: proximity | Show results with:proximity
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[PDF] Self-aligned double-patterning layout decomposition for two ...
Dec 4, 2014 · Thus, layout decomposition for random 2-D logic features which have various wire widths and spaces is a primary challenging issue for a ...
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10nm Fab Challenges - Semiconductor Engineering
May 21, 2015 · With SAQP, chipmakers also can move towards a simpler two-step patterning flow using lines and cuts. Patterning the lines is relatively simple.
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(PDF) A new method for post-etch OPC modeling to compensate for ...
Aug 9, 2025 · In this paper, we demonstrate a new methodology for post-etch OPC modeling to compensate for effects of underlayer seen on product wafers.
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Photomask plasma etching: A review - AIP Publishing
Jan 10, 2006 · CD etch bias has been an important parameter for photomask plasma etch because it determines the CD deviation from nominal values.
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7nm Lithography Choices - Semiconductor Engineering
Mar 7, 2016 · For example, with immersion/multi-patterning, there are 34 lithography steps at 7nm, according to ASML. With EUV alone, there are just 9 steps, ...
[65]
Why EUV Is So Difficult - Semiconductor Engineering
Nov 17, 2016 · Chipmakers are capable of extending immersion/multi-patterning from 16nm/14nm to 10nm and 7nm. Beyond 7nm, though, there is some uncertainty.<|control11|><|separator|>
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A Photolithography Process Design for 5 nm Logic Process Flow
Aug 9, 2025 · In a typical 5 nm logic process, the contact-poly pitch (CPP) is 44-50 nm, the minimum metal pitch (MPP) is around 30-32 nm.
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Line Edge Roughness Reduction Techniques in EUV Lithography
Oct 13, 2025 · Discover how EUV lithography revolutionizes semiconductor manufacturing and the critical challenges of Line Edge Roughness in sub-10nm chip ...<|control11|><|separator|>
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Accelerating Computational Lithography & Chip Design with NVIDIA
Mar 21, 2023 · We explain computational lithography and explore how our partnership with NVIDIA accelerates semiconductor scaling and the chip design flow ...
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Tough road ahead for device overlay and edge placement error
Mar 26, 2019 · EPE requirements of a "single digit nanometer number" is now a harsh reality in 5nm nodes and below. In this technical presentation we will ...Missing: 3nm | Show results with:3nm
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Comparative Stochastic Process Variation Bands For N7, N5, And ...
Feb 21, 2019 · We compare the performance of organic chemically-amplified and condensed metal-oxide resists exposed at different sizing doses using a proxy 2D SRAM layout.
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3nm Technology - Taiwan Semiconductor Manufacturing Company ...
In 2022, TSMC became the first foundry to move 3nm FinFET (N3) technology into high-volume production. N3 technology is the industry's most advanced process ...Missing: Samsung OPC EUV
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Photomask Challenges At 3nm And Beyond
Jan 25, 2022 · Specifically, as you try to do OPC (optical proximity correction), where you're using smaller features, these effects really have an impact.
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[PDF] Advances in Inverse Lithography - UCLA Mathematics
Jul 14, 2022 · Inverse lithography technology (ILT) is a method of solving the mask synthesis problem by setting the problem up as an inverse problem ...
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[PDF] L2O-ILT: Learning to Optimize Inverse Lithography Techniques
Problem 1 (Mask Optimization): Given a target image Zt, the objective of mask optimization is to find a mask M, whose printed image through the lithography ...
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[PDF] Model-based OPC Extension in OpenILT - CUHK CSE
This paper presents an MB-OPC extension of OpenILT, an open-source library for computational lithography, to enable model-based optical proximity correction. It ...
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5 things you should know about High NA EUV lithography - ASML
Jan 25, 2024 · High NA EUV is the next step in our constant pursuit of shrink. Like NXE systems, it uses EUV light to print tiny features on silicon wafers.
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Breakthrough curvilinear ILT enabled by multi-beam mask writing
Nov 17, 2021 · Multi-beam mask writers can write curvilinear masks in a constant write time, and curvilinear mask patterns are more resilient than Manhattan ...