Fact-checked by Grok 2 weeks ago

Electromigration

Electromigration is the transport of material within a metallic conductor driven by the momentum transfer from high-density electron flow to metal ions, resulting in atomic diffusion under combined influences of electric fields and elevated temperatures.^[1]^[2] This phenomenon poses a major reliability challenge in modern integrated circuits (ICs), where shrinking interconnect dimensions—now often below 10 nm—exacerbate current densities exceeding 10^7 A/cm², accelerating atomic migration and leading to material depletion or accumulation.^[3]^[4] Voids form preferentially at the cathode end of interconnect lines due to atomic divergence, potentially causing open circuits and increased resistance, while hillocks or whiskers at the anode can induce short circuits or mechanical stress.^[1]^[2] In very-large-scale integration (VLSI) technologies, these failures limit device lifespan, with mean time to failure (MTTF) critically dependent on operating conditions like temperature (typically 100–200°C) and current magnitude.^[3]^[4] The primary driving force is the electron wind, where electrons colliding with ions impart sufficient momentum to enable diffusion, dominating over the weaker direct electrostatic force on ions.^[1]^[4] Atomic movement occurs via thermally activated processes along lattice sites, grain boundaries (fastest path in polycrystalline metals), or surfaces/interfaces, with diffusivity following the Arrhenius relation D = D_0 exp(-Q/RT), where Q is the activation energy (0.5–1.0 eV for common metals like Al or Cu).^[1]^[2] Additional coupled effects include thermomigration from temperature gradients and stress migration from mechanical gradients, which can either mitigate or intensify electromigration damage in confined structures.^[4] Reliability assessment relies on empirical models like Black's equation, originally derived in 1969, which predicts MTTF as t_{50} = A j^{-n} \exp(E_a / kT), where j is current density, n ≈ 2 for line failures (1 for via failures), E_a is activation energy, k is Boltzmann's constant, and T is absolute temperature.^[5]^[3] More advanced physics-based approaches, such as the atomic flux divergence model and Korhonen's stress evolution equation, account for void nucleation and growth, enabling simulations for complex IC layouts.^[4] First observed in 1861 by M. Gerardin, with the term "electromigration" coined by physicist H.B. Huntington in the late 1950s, it gained prominence in the 1960s with aluminum interconnect failures in early ICs, prompting the shift to more resistant copper metallization in the 1990s, which offers ~5–10 times longer lifetimes due to its lower resistivity and higher melting point.^[6]^[1] As of 2025, electromigration remains a critical challenge in sub-2 nm nodes, driving exploration of alternative interconnect materials like cobalt and ruthenium.^[7] Mitigation strategies include alloying (e.g., Cu with Mn or Al), barrier layers to block fast diffusion paths, and design rules limiting current density below thresholds like the Blech product (jL < (jL)_{crit} ≈ 3000 A/cm for Cu lines), alongside pulsed current operation to leverage recovery effects.^[2]^[4] Recent advances incorporate machine learning and multi-physics simulations for full-chip electromigration analysis, addressing nanoscale challenges in sub-5 nm nodes.^[4]

Fundamentals

Definition and Basic Principles

Electromigration is the transport of material in a conductor resulting from the gradual movement of ions due to momentum transfer between conducting electrons and diffusing metal atoms. This phenomenon occurs in metallic interconnects under high current densities, where the drift of electrons imparts force to the lattice ions, leading to atomic diffusion predominantly in the direction of electron flow.^[4] The primary cause of electromigration is the direct electron wind force, arising from collisions between drifting electrons and metal ions, which dominates atomic transport in most cases. An indirect cause involves temperature gradients, which can induce thermomigration by driving atoms from hotter to cooler regions, though this is secondary to the electron wind effect. A key prerequisite is Joule heating, the resistive dissipation of electrical power that elevates local temperatures and exponentially enhances atomic diffusion rates, thereby accelerating the process.^[4]^[8] Central concepts in assessing electromigration include the mean time to failure (MTTF), which quantifies the operational lifespan of an interconnect before degradation leads to circuit malfunction; the critical current density, representing the threshold above which significant material transport occurs; and the activation energy for diffusion, the energy barrier that governs the temperature dependence of atomic mobility. For instance, in integrated circuits, electromigration has historically affected aluminum interconnects, where high current densities caused rapid voiding and failure, prompting the industry-wide shift to copper interconnects in the late 1990s for their superior resistance to this effect due to higher activation energies and lower resistivity.^[9]^[4]

Forces on Ions in Electric Fields

In electromigration, the movement of metal ions in a conductor under an applied electric field is driven by two primary microscopic forces: the electrostatic force and the electron wind force. The electrostatic force arises from the direct interaction of the electric field with the positively charged ion core, pulling the ion in the direction of the field (toward the cathode). This force is given by F_{\text{direct}} = Z e \vec{E}, where Z is the valence of the ion, e is the elementary charge, and \vec{E} is the electric field. However, due to screening by conduction electrons, the effective magnitude of this force is significantly reduced, often making it secondary to other contributions.^[10] The electron wind force is the dominant driver of ion migration, resulting from the transfer of momentum from drifting conduction electrons to the metal ions during collisions. As electrons flow through the lattice under the influence of the current, they scatter off ions, imparting a net momentum in the direction of electron drift (opposite to the conventional current, toward the anode). This "wind" effect biases the random thermal motion of ions, leading to directed atomic transport. The concept was first theoretically developed in the ballistic model by Fiks and independently by Huntington and Grone, who described it as arising from the asymmetric scattering of electrons by lattice defects and ions.^[10] The electron wind force can be approximated in a classical model as \vec{F}_{\text{wind}} \approx - \left( N_e m_e v_d / \tau \right) \left( \sigma / n \right), where N_e is the electron density, m_e is the electron mass, v_d is the electron drift velocity, \tau is the electron mean free time between collisions, \sigma is the electrical conductivity, and n is the density of metal atoms. This approximation captures the rate of momentum transfer per unit volume from electrons to the lattice, scaled by the relative scattering efficiency (via \sigma / n), resulting in a force per ion directed opposite to the electric field. The negative sign indicates its opposition to the electrostatic force in typical metals.^[11] The total force on an ion is the vector sum \vec{F} = Z e \vec{E} + \vec{F}_{\text{wind}}, which is often expressed in terms of an effective valence Z^* as \vec{F} = Z^* e \vec{E}. Here, Z^* = Z - \Delta Z, where \Delta Z is a positive correction term accounting for back-scattering effects. In the simple ballistic model, the wind contribution would yield a large negative valence proportional to the number of conduction electrons per atom, but back-scattering—where ions reflect some electrons without full momentum transfer—reduces this magnitude, making \Delta Z a measure of the backscattered fraction. This adjustment ensures Z^* is typically negative (e.g., -3 to -10 for common interconnect metals like Al and Cu), driving net ion migration against the electric field.^[4] These forces produce a net drift of ions, quantified by the atomic flux \vec{J} = (D / kT) \vec{F}, where D is the diffusion coefficient, k is Boltzmann's constant, and T is the temperature. This expression, derived from linear irreversible thermodynamics, links the electromigration driving force to a biased diffusion process analogous to Fick's laws, where the force \vec{F} acts as an effective chemical potential gradient. Thermal effects can amplify this flux by enhancing D, though their detailed role involves additional stress and temperature gradients.^[10]

Historical Development

Early Discovery and Observations

Electromigration as a phenomenon was first observed in liquid metals in the 19th century and studied in solid alloys during the 1950s, with theoretical models developed by V.B. Fiks in 1959 and H.B. Huntington and A.R. Grone in 1961 describing the electron wind force. The term "electromigration" was coined by physicist H.B. Huntington in the late 1950s.^[12] The phenomenon of electromigration in thin metal films gained significant attention in the mid-1960s as integrated circuit technology emerged, with the first detailed observations reported in 1966 by I. A. Blech and H. Sello at Fairchild Semiconductor. They identified void formation in aluminum interconnects subjected to high current densities, attributing these failures to atomic mass transport driven by electron momentum transfer in the films. This work highlighted electromigration as a critical reliability issue in early semiconductor devices, where current densities exceeded 10^6 A/cm², leading to rapid degradation.^[13] Throughout the 1960s, experimental studies on thin metal wires, particularly aluminum, demonstrated consistent mass transport along the direction of electron flow, often resulting in material depletion at the cathode end and accumulation at the anode. Researchers at institutions like Texas Instruments conducted engineering tests on sputtered films, observing that electromigration accelerated under elevated temperatures and current stresses, with voids nucleating preferentially at grain boundaries. These experiments, often using resistive heating to simulate operating conditions, established that the process was unidirectional and proportional to current density, providing initial quantitative insights into failure rates in high-power applications.^[13] Initial reports linked electromigration to premature failures in high-power devices and metallization in nascent integrated circuits, where devices failed within weeks due to open circuits from void growth. At Texas Instruments and other labs, such failures were traced to aluminum lines in early ICs operating at power levels that induced currents far above ambient thresholds, prompting urgent reliability investigations. These observations underscored the need for current density limits in device design.^[12] In the late 1960s, pioneering microscopy techniques enabled direct visualization of electromigration-induced defects. Transmission electron microscopy (TEM) was employed by Blech to observe real-time atomic migration and void evolution in aluminum films under current, revealing dynamic hillock formation and void migration speeds on the order of micrometers per hour. In the early 1970s, scanning electron microscopy (SEM) was adapted to image surface topographies, capturing hillocks and voids in post-stressed samples, which confirmed the role of surface and grain boundary diffusion in defect morphology. These techniques marked a shift from indirect electrical measurements to structural analysis, facilitating deeper understanding of failure modes.^[14]^[15]

Key Milestones in Microelectronics

In the 1970s, electromigration emerged as a critical reliability concern in microelectronics with the advent of very large-scale integration (VLSI) technologies, where shrinking aluminum interconnect dimensions led to higher current densities and accelerated atomic diffusion. A seminal contribution was the development of Black's equation in the late 1960s, formalized by J.R. Black, which modeled the mean time to failure (MTTF) of aluminum lines as MTTF = A * j^{-n} * exp(E_a / kT), where j is current density, n is a scaling exponent (typically 1-2), E_a is activation energy, k is Boltzmann's constant, and T is temperature; this semi-empirical relation enabled quantitative prediction and design guidelines for interconnect reliability in early VLSI circuits.^[16] The 1990s marked a pivotal shift from aluminum to copper interconnects, driven by the need to mitigate electromigration failures amid continued scaling, with copper's adoption facilitated by the damascene process that etches trenches in the dielectric and electroplates copper, followed by chemical-mechanical polishing. This transition, beginning in the late 1990s, reduced electromigration susceptibility due to copper's higher melting point (1085°C versus aluminum's 660°C), which strengthens atomic bonds and lowers diffusivity, as well as the bamboo-like microstructure in narrow damascene lines that minimizes grain boundary paths for atomic transport. A key milestone was IBM's high-volume manufacturing of copper interconnects starting in 1998, which extended electromigration MTTF by orders of magnitude compared to aluminum, enabling reliable operation at higher current densities in advanced logic chips.^[17]^[18] In the 2000s, the integration of low-k dielectrics (with k < 3.0) into copper interconnect stacks, first commercialized around the 90 nm node, addressed RC delay issues but introduced new electromigration challenges in sub-micron features, as these porous, mechanically weaker materials (modulus ~5-10 GPa versus silicon dioxide's 70 GPa) amplified stress gradients from voiding and extrusion, leading to delamination risks under high current densities.^[19] The 2010s and 2020s have seen electromigration risks intensify with the emergence of 3D integrated circuits (ICs), FinFET transistors (introduced at 22 nm in 2011), and advanced nodes like 5 nm (production ramp in 2020), where current densities exceeding 10^6 A/cm² in scaled interconnects and through-silicon vias drive faster void nucleation due to elevated Joule heating and thermal gradients (>10°C between stacked dies). These structures demand enhanced modeling to manage multi-physics interactions, as higher drive currents for performance gains outpace traditional mitigation, threatening reliability in stacked FinFET-based chips.^[4]

Physical Mechanisms

Atomic Diffusion Processes

In electromigration, metal atoms migrate primarily through three key diffusion mechanisms: lattice (volume) diffusion, grain boundary diffusion, and interface diffusion, each characterized by distinct pathways and activation energies that determine their relative contributions in thin-film interconnects.^[20] Lattice diffusion involves atomic jumps through the ordered crystal lattice of the bulk material and requires overcoming high activation energies, such as approximately 2.2 eV for copper, rendering it negligible at typical operating temperatures below 200°C in microelectronics.^[21] In polycrystalline metals, grain boundary diffusion dominates due to the disordered atomic structure at grain boundaries, which provides lower activation energies around 1.2 eV for copper and facilitates faster atomic transport along these short-circuit paths.^[21] The grain boundary diffusivity follows the Arrhenius relation:

D_{gb} = D_0 \exp\left( -\frac{Q_{gb}}{kT} \right),

where D_0 is the pre-exponential factor, Q_{gb} is the activation energy for grain boundary diffusion, k is Boltzmann's constant, and T is the absolute temperature.^[22] Interface diffusion occurs at the boundaries between the metal film and adjacent layers, such as dielectrics or liners, with activation energies as low as 1.0 eV for copper, making it particularly significant in thin-film structures where surface or near-surface paths are accessible.^[20] The electron wind force imparts directionality to this atomic movement, driving a net flux of atoms in the direction of electron flow; this is captured in the atomic flux equation:

\mathbf{J} = \frac{D C}{kT} \mathbf{F},

where \mathbf{J} is the atomic flux, D is the diffusivity (specific to the mechanism), C is the atomic concentration, and \mathbf{F} includes the wind force from momentum transfer by conduction electrons.^[23] Comparisons across mechanisms highlight that bulk lattice diffusion is orders of magnitude slower than grain boundary or interface diffusion at interconnect operating temperatures, with the latter two often competing based on microstructure—grain boundaries prevail in uncapped polycrystalline lines, while interface paths become prominent under passivation layers.^[21] In copper interconnects, diffusion of copper atoms along tantalum (Ta) barriers is especially critical, as these thin Ta liners (typically 5–10 nm) serve to block copper penetration into dielectrics but can channel electromigration flux at the Cu/Ta interface, exacerbating void formation in damascene structures. Surface diffusion further contributes in uncapped copper lines, enabling rapid atomic redistribution along exposed topsides.^[21]

Thermal and Stress Effects

In electromigration, Joule heating arises as a secondary driver of material degradation due to the resistive dissipation of electrical power in conductors, leading to localized temperature rises that accelerate atomic diffusion. The local temperature increase can be approximated by the relation \Delta T = \frac{I^2 \rho l}{A^2 h}, where I is the current, \rho is the material resistivity, l is the segment length, A is the cross-sectional area, and h is the heat transfer coefficient.^[24] This self-heating effect becomes particularly pronounced in high-current-density scenarios, such as accelerated testing, where it can elevate the effective operating temperature and thereby enhance the overall electromigration flux beyond the primary electron wind force.^[25] Temperature gradients induced by Joule heating also contribute a thermomigration component to the atomic flux, which supplements the electromigration process. This thermal flux is given by J_{\text{thermal}} = -\frac{D C Q^*}{k T^2} \nabla T, where D is the diffusion coefficient, C is the atomic concentration, Q^* is the heat of transport, k is Boltzmann's constant, T is the absolute temperature, and \nabla T is the temperature gradient.^[26] The heat of transport Q^* reflects the energy carried by migrating atoms relative to the lattice, and its sign determines whether thermomigration reinforces or opposes the electromigration direction; in metals like copper, it often aligns to exacerbate degradation under nonuniform heating.^[26] These gradients are especially relevant in interconnect structures with varying current densities, where localized hot spots amplify the combined electromigration-thermomigration driving force. Mechanical stress gradients, arising from atomic accumulation or depletion, further modify the electromigration flux through a back-stress term that can oppose net material transport. The stress-induced flux is expressed as J_{\text{stress}} = \frac{D C \Omega}{k T} \nabla \sigma, where \Omega is the atomic volume and \sigma is the hydrostatic stress.^[26] In passivated interconnects, this gradient builds compressive stress at the anode and tensile stress at the cathode, creating a counterforce that reduces the effective driving force for diffusion.^[26] The interplay between these stress effects and the base diffusion flux—primarily driven by the electron wind—results in a total atomic flux that integrates chemical potential, electrical, thermal, and mechanical contributions, as described in coupled models of electromigration dynamics.^[26] A key manifestation of stress buildup occurs in short interconnect segments, known as the Blech effect, where accumulated mechanical stress inhibits net atomic migration once a critical length is exceeded. In such structures, the opposing stress gradient balances the electromigration force, leading to a steady-state condition with no further degradation. This phenomenon, first observed in aluminum films, underscores the role of line length in electromigration immunity, with critical lengths typically on the order of 10–15 μm depending on current density and passivation. In narrow interconnect lines below 100 nm, self-heating from Joule effects can significantly amplify degradation, effectively doubling the impact of the activation energy on electromigration rates by raising local temperatures and altering diffusion kinetics.^[27] This enhanced thermal influence in scaled structures necessitates careful consideration of heat dissipation in design to mitigate accelerated failure modes.^[27]

Failure Phenomena

Void Formation and Hillock Growth

Electromigration induces unbalanced atomic flux in metal interconnects, leading to material depletion at the cathode end where the flux diverges outward, resulting in void formation, and accumulation at the anode end where the flux converges, promoting hillock growth. This divergence arises from the direct electron wind force on metal ions, as established in early models of atomic transport under current. Void nucleation typically occurs at sites of high stress concentration, such as grain boundaries or interfaces with passivation layers, where vacancies cluster due to the local supersaturation from divergent flux. Once nucleated, voids grow through the coalescence of additional vacancies diffusing to the void surface, often elongating along the direction opposite to electron flow and increasing in cross-section until they compromise the interconnect's integrity.^[4] In aluminum lines, these voids exhibit significant migration against the electron flow due to the dominance of grain boundary diffusion, whereas in copper lines with bamboo-like microstructures, void migration is generally suppressed compared to aluminum, with growth occurring primarily via interface diffusion.^[28] Hillocks form at the anode through the extrusion of metal atoms under compressive stress buildup from convergent atomic flux, serving as a mechanism to relieve this hydrostatic pressure.^[4] These protrusions can pierce overlying dielectric layers, potentially creating electrical shorts between adjacent interconnects and exacerbating failure in dense integrated circuits.^[4] The progression of electromigration damage unfolds in distinct stages: an incubation period where flux divergence gradually accumulates vacancies and stress without visible voids; a growth phase characterized by void propagation and hillock extrusion, often marked by gradual resistance changes; and catastrophic failure, typically an open circuit from void-induced severance or a short from hillock bridging. This sequence underscores the morphological evolution from subtle atomic imbalances to overt structural degradation in interconnects.^[4]

Step Bunching and Surface Instabilities

Step bunching refers to the aggregation of atomic steps on vicinal surfaces of crystalline materials during electromigration, resulting in surface roughening and morphological instabilities.^[29] This phenomenon arises when high current densities drive adatoms along the surface, causing uneven step advancement and coalescence into larger bunches.^[30] The underlying mechanism involves unequal rates of adatom detachment from and attachment to steps, primarily induced by the electron wind force in electromigration. The electron wind imparts a directed momentum to adatoms, biasing their diffusion preferentially in the direction of electron flow, which leads to asymmetric fluxes at step edges.^[29] This asymmetry destabilizes the uniform step train on vicinal surfaces, promoting the faster migration of certain steps and their merging with neighboring ones.^[31] Such instabilities have been observed in silicon (Si) vicinal surfaces under current stress, where heating currents through the sample induce step bunching on Si(111).^[29] Mathematically, the velocity v of a step can be described by considering the electromigration-driven adatom flux, given approximately as

v = \frac{\Gamma \Omega j_e}{kT} (1 - \cos \theta),

where \Gamma is the attachment coefficient, \Omega is the atomic volume, j_e is the electron current density, k is Boltzmann's constant, T is temperature, and \theta is the step orientation angle relative to the current direction.^[29] This expression highlights the dependence on current density and orientation, explaining the directional sensitivity of bunching. Electromigration-induced step bunching was first theoretically analyzed and reported in the early 1990s for silicon surfaces during semiconductor processing, with implications for surface planarization challenges in advanced microelectronic nodes.^[29] In modern nanoscale devices, these instabilities remain relevant, as they can exacerbate interface roughness in heterostructure-based components, potentially limiting reliability and performance.

Atom Concentration Balance

The balance of atom concentration in metallic conductors subjected to electromigration is fundamentally described by the continuity equation:

\frac{\partial C}{\partial t} = -\nabla \cdot \mathbf{J} + G

where C is the atomic concentration, \mathbf{J} is the atomic flux vector, and G accounts for any generation or recombination terms, such as those from nucleation processes. In the steady-state regime, where concentration changes are minimal and generation is negligible, the equation reduces to \nabla \cdot \mathbf{J} = 0, implying no net divergence of atomic flux and thus a balanced distribution of atoms along the conductor. This condition is crucial for modeling the equilibrium in interconnects, preventing unbounded accumulation or depletion that could lead to failure. The atomic flux \mathbf{J} arises from the combined effects of diffusion and drift under applied forces, expressed as:

\mathbf{J} = -D \nabla C + \frac{D C \mathbf{F}}{kT}

where D is the diffusion coefficient, k is Boltzmann's constant, T is the absolute temperature, and \mathbf{F} is the total force per atom, incorporating the electromigration driving force Z^* e \mathbf{E} (with Z^* the effective valence, e the electron charge, and \mathbf{E} the electric field) alongside the back-stress force -\Omega \nabla \sigma (\Omega the atomic volume, \sigma the hydrostatic stress). In steady state with zero net flux (\mathbf{J} = 0), the equation yields \nabla C / C = \mathbf{F} / (kT), resulting in exponential (logarithmic in gradient form) concentration profiles along the conductor. These gradients reflect the competition between forward electromigration and opposing stress-induced diffusion, stabilizing the atomic distribution. A key outcome of this balance is the critical length, known as the Blech length \lambda_c, below which no net atomic migration occurs due to the back-stress fully counteracting the electromigration force. This length is given by \lambda_c = \frac{\Delta \sigma \Omega}{Z^* e \rho j}, where \Delta \sigma is the stress difference across the segment, \rho is the resistivity, and j is the current density. For lengths shorter than \lambda_c, the induced stress gradient establishes equilibrium rapidly, rendering the conductor "immortal" to electromigration damage. This framework, originally derived in the 1970s through experimental observations in thin aluminum films, has become essential for analyzing short interconnects in modern integrated circuits, where feature sizes often fall below traditional Blech lengths, enhancing reliability by exploiting back-stress effects.^[32]

Practical Implications

Impact on Integrated Circuit Reliability

Electromigration serves as a primary wear-out mechanism in on-chip interconnects, where sustained high current densities drive atomic diffusion, leading to gradual degradation over time. This process limits the scaling of interconnect dimensions as outlined in the International Technology Roadmap for Semiconductors (ITRS), with the lifetime of minimum-sized copper lines halving for each technology generation even at constant current density due to reduced cross-sectional area and increased vulnerability to atomic flux divergence.^[33]^[4] In advanced nodes, this wear-out exacerbates reliability challenges, as current densities approach or exceed 10^6 A/cm², pushing interconnects toward the electromigration limit and constraining overall circuit performance.^[33] The primary failure modes induced by electromigration involve void formation at the cathode end, which depletes material and creates open circuits by severing electrical continuity, and hillock growth at the anode, where atomic accumulation leads to protrusions that can cause short circuits between adjacent lines.^[4] These phenomena are quantified using the median time to failure (MTTF), a key reliability metric that estimates the time until 50% of interconnects fail under specified stress conditions, often modeled via Black's equation to predict degradation based on current density, temperature, and material properties.^[4] Prior to widespread mitigation, electromigration contributed significantly to field failures in integrated circuits, accounting for a notable fraction of early-term reliability issues in high-current paths.^[34] Electromigration further impacts power delivery networks by increasing interconnect resistance through void-induced cross-sectional reduction, which elevates voltage drops (IR drop) and compromises signal integrity and transistor performance.^[4]^[35] In 7 nm technology nodes and below, electromigration emerges as the dominant reliability killer for copper interconnects, with thermomigration effects from spatial Joule heating gradients reducing time-to-failure by up to 50% compared to isothermal conditions.^[36] Recent 2023 studies highlight exacerbated risks in high-performance computing applications, where combined electromigration, thermomigration, and stress migration in AC-driven lines shift stress profiles and diminish self-healing capabilities, necessitating integrated multi-physics modeling for robust design.^[37]

Effects in Solder Joints and Packaging

In flip-chip solder bumps, such as those composed of Sn-Pb or Sn-Ag-Cu alloys, electromigration drives the formation and growth of intermetallic compounds (IMCs) at the solder-metal interfaces, often leading to the development of Kirkendall voids due to unequal atomic diffusion rates between Sn and Cu atoms.^[38] These voids arise from the preferential outward diffusion of Sn compared to inward Cu migration, creating vacancy supersaturation at the IMC-solder boundary.^[39] The driving forces for electromigration are significantly amplified in microbumps with diameters below 100 μm, where current densities routinely exceed 10^4 A/cm², far surpassing those in conventional solder joints and accelerating atomic flux divergence.^[40] This high-density regime, common in advanced packaging, exacerbates IMC thickening and void nucleation, distinguishing off-chip interconnects from on-chip metallization by introducing greater thermal gradients and mechanical stresses.^[4] Failure in these structures exhibits pronounced polarity effects, with voids preferentially forming at the cathode-side IMC interface due to electron wind forces depleting Sn atoms and promoting rapid IMC dissolution.^[41] Recent studies on Sn-based microbumps in 3D stacking configurations indicate accelerated degradation owing to intensified thermal coupling and current localization across stacked dies.^[4] Current crowding at the edges of solder bumps further intensifies electromigration flux, concentrating atomic transport and hastening void propagation toward the bump center, which can reduce the mean time to failure (MTTF) by orders of magnitude. Consequently, MTTF scales inversely with bump size, as smaller dimensions elevate local current densities under fixed total currents, amplifying the electromigration rate per Black's equation framework. Advancements in 2023 have introduced hybrid bonding schemes using Cu/SiO₂ interfaces with direct Cu-Cu contacts, which mitigate electromigration by eliminating solder-induced diffusion paths and achieving up to 10 times higher resistance to void formation compared to traditional Sn-Ag-Cu microbumps.^[42] This approach leverages passivation layers to suppress IMC overgrowth, enhancing overall packaging reliability in high-density applications.^[43]

Design and Mitigation Strategies

Reliability Modeling with Black's Equation

Reliability modeling for electromigration in metallic interconnects commonly employs Black's equation to predict the mean time to failure (MTTF), which quantifies the lifetime before catastrophic voiding or hillock formation occurs. This empirical model relates the MTTF to operating conditions such as current density and temperature, serving as a foundational tool for assessing interconnect reliability in integrated circuits.^[16]^[44] The standard form of Black's equation is given by

\text{MTTF} = A j^{-n} \exp\left(\frac{E_a}{kT}\right),

where A is a material- and structure-dependent constant, j is the current density, n is the current density exponent, E_a is the activation energy for atomic diffusion, k is Boltzmann's constant, and T is the absolute temperature. The exponent n typically ranges from 1 to 2 for void-related failures, reflecting the dominance of either void growth (n \approx 1) or void nucleation (n \approx 2), while n \approx 2 is often used for hillock formation due to the quadratic dependence on atomic flux divergence in nucleation processes.^[44]^[16] Black's equation derives from the physical principles of atomic flux divergence and void nucleation rates in one-dimensional interconnect models. The electromigration-induced atomic flux J is proportional to j via the electron wind force, leading to a divergence \nabla J \propto j that causes local atomic depletion or accumulation; failure occurs when this divergence reaches a critical threshold for void nucleation, with the nucleation rate scaling as (\nabla J)^2 under certain assumptions, yielding the j^{-2} dependence. The model assumes a log-normal distribution of failure times across an ensemble of interconnects, where the MTTF corresponds to the median failure time in accelerated testing, and incorporates thermally activated diffusion through the Arrhenius term \exp(-E_a / kT).^[44]^[16] Originally developed for aluminum interconnects in 1969, Black's equation used n=2 and E_a \approx 0.5 eV, calibrated from experimental data on thin-film aluminum lines. For modern copper interconnects, parameters are adjusted based on bamboo-like microstructures and grain boundary diffusion, with n \approx 2 and E_a \approx 0.9-1.0 eV reported in dual-damascene Cu structures, though values up to 1.2 eV have been observed depending on capping layers and dielectrics. The activation energy E_a arises from the dominant diffusion mechanisms, such as grain boundary or interface diffusion.^[16]^[44] Extensions to Black's equation account for Joule heating effects, where high current densities elevate the local temperature beyond ambient conditions; this requires iterative calculation of T using \Delta T = \rho j^2 t / \kappa, with \rho as resistivity, t as thickness, and \kappa as thermal conductivity, to refine the MTTF prediction in self-heating scenarios. A key limitation is the neglect of the Blech effect, where stress gradients induce back-diffusion that saturates electromigration in short lines (below the critical length), preventing failure and invalidating the model for sub-micron segments.^[44]^[45]

Material and Structural Optimizations

Material selection plays a crucial role in enhancing electromigration (EM) resistance in interconnects. Copper has largely replaced aluminum in modern integrated circuits due to its higher melting point of 1083 °C compared to aluminum's 660 °C, which contributes to slower atomic diffusion and improved thermal stability under high current densities.^[46] Additionally, the activation energy for grain boundary diffusion in copper ranges from 0.7 to 1.2 eV, higher than the 0.5 to 0.7 eV typically observed in aluminum alloys, thereby reducing the rate of EM-induced mass transport.^[47] Structural optimizations, such as the bamboo microstructure, further mitigate EM by promoting single-crystal-like grains that span the full width of the interconnect line. In this configuration, grain boundaries are oriented perpendicular to the direction of current flow, effectively suppressing grain boundary diffusion—the dominant pathway for atomic migration in polycrystalline metals.^[48] This structure limits the number of fast-diffusion paths available for metal ions, leading to extended mean time to failure (MTTF) compared to polycrystalline lines with random grain orientations.^[49] Barrier layers are essential in copper damascene processes to prevent interfacial diffusion, a key factor in EM voiding. Tantalum nitride (TaN) barriers, typically deposited via physical vapor deposition, effectively block copper diffusion into the surrounding dielectric while providing strong adhesion, thereby enhancing overall EM reliability.^[50] Recent advancements include cobalt liners, which serve as both diffusion barriers and capping layers; 2024 studies on narrow cobalt lines in sub-10 nm nodes demonstrate reduced EM failure rates through interface stabilization and suppressed interdiffusion, particularly when alloyed with trace elements like manganese oxide.^[51] Emerging capping layers using ruthenium (Ru) or cobalt (Co) offer promising enhancements for advanced nodes by blocking fast diffusion paths at interfaces. For instance, Co capping layers promote stronger metal-dielectric adhesion and inhibit surface diffusion, resulting in significantly prolonged EM lifetimes—up to 36 times longer in graphene-encapsulated cobalt structures compared to conventional annealed cobalt lines tested at 30 MA/cm² and 200 °C.^[52] Similarly, barrierless Ru interconnects exhibit superior EM reliability over copper due to Ru's higher cohesive energy and shorter electron mean free path, which reduces atomic mobility under electron wind forces.^[53] To equalize current density and prevent localized EM hotspots, techniques like metal slotting incorporate via inlays or redundant conductive paths within interconnect segments. These approaches distribute current more uniformly, lowering peak densities in critical regions such as vias and junctions, and thereby extend MTTF without altering overall line geometry.^[54] Despite these benefits, trade-offs exist in material choices; for example, ruthenium's higher bulk resistivity (approximately 7.1 μΩ·cm versus copper's 1.7 μΩ·cm) can increase power consumption in scaled interconnects, though this is often offset by the elimination of thick barrier layers and Ru's enhanced EM resistance in sub-10 nm features.^[53] Grain boundary diffusion, being the primary EM mechanism in metals, is targeted by these optimizations to minimize divergence in atomic flux and maintain interconnect integrity.^[48]

Layout and Geometric Considerations

In electromigration-prone interconnects, the Blech length effect plays a crucial role in layout design, rendering short metal segments "immortal" to failure by establishing a steady-state balance between electromigration-induced atomic flux and back-stress diffusion. For copper interconnects, this critical length λ_c typically ranges from 10 to 100 μm, depending on current density, temperature, and microstructure; segments shorter than λ_c experience no net atomic migration, as compressive stress at the anode end counteracts the electron wind force.^[55] To exploit this, designers segment long wires using barriers or vias to create multiple short segments, effectively limiting the effective migration length and enhancing reliability without altering material properties.^[56] Via arrangements are optimized to distribute current evenly and minimize local electromigration hotspots, particularly in multilayer interconnect stacks. Employing redundant vias—multiple parallel connections between metal levels—reduces the current density per via, often by a factor proportional to the number of vias, thereby extending lifetime in high-current paths. Tapered via designs or arrays further promote uniform current density by gradually adjusting cross-sectional area, preventing void nucleation at via-line interfaces where flux divergence is high.^[57] Current crowding at geometric discontinuities, such as corner bends in interconnect paths, exacerbates electromigration by locally elevating current density j by 2-3 times compared to straight segments, accelerating void formation at the bend's upstream edge. Sharp 90° bends are particularly vulnerable due to the abrupt change in direction, leading to non-uniform electron flow; mitigation strategies include widening the inner radius of corners or introducing jogs (short perpendicular extensions) to smooth the path and redistribute current more evenly.^[56] Industry standards, such as those from JEDEC, guide these geometric rules by specifying maximum allowable current densities for interconnects, typically limited to 1-5 MA/cm² in copper lines for advanced nodes to ensure a mean time to failure exceeding 10 years under operating conditions. Recent 2023 guidelines, including updates to JESD63, integrate the Blech length into design rule checks (DRC) for sub-10 nm processes, allowing segmented layouts to exceed uniform density limits while maintaining reliability margins.^[58]^[59] Upstream and downstream rules account for the directional nature of electromigration, where electron flow determines void-prone and accumulation sites, necessitating asymmetric design thresholds. In upstream configurations (voids form at the cathode end), stricter current density limits apply due to faster depletion rates, often 20-50% lower than downstream cases where compressive stress buildup at the anode delays hillock extrusion. These rules are enforced in physical design tools by classifying net directions and applying tailored spacing or width adjustments to protect vulnerable ends.^[60]

Simulation and Predictive Tools

Technology computer-aided design (TCAD) tools employ finite element methods to solve coupled equations for electromigration (EM), stress, and heat transport, enabling detailed simulation of void nucleation and evolution in interconnects. These simulations track atomic flux divergence and hydrostatic stress buildup, predicting failure times by modeling void growth phases from incubation to propagation.^[61] For instance, Korhonen's stress evolution model, integrated into TCAD frameworks, computes time-dependent stress gradients in passivated metal lines to identify nucleation sites. IR drop noise, arising from voltage fluctuations in power distribution networks, generates transient currents that exacerbate EM by increasing local Joule heating and atomic flux. This phenomenon is modeled using SPICE-based simulations that incorporate EM-aware parasitic elements, coupling electronic circuit analysis with stress evolution to assess accelerated degradation under dynamic loads.^[62] Tools like EMSpice perform full-chip analysis of EM-induced IR drops, revealing how noise amplifies void formation risks in high-density grids.^[63] Physics-based models for void nucleation rely on partial differential equations (PDEs) describing atomic diffusion, stress gradients, and electron wind forces, providing accurate predictions of failure mechanisms in advanced nodes.^[64] Recent 2025 simulations extend these PDEs to capture multi-physics interactions, such as phase-field approaches for void dynamics in polycrystalline structures, improving fidelity over empirical baselines like Black's equation.^[65] Bayesian physics-informed neural networks (BPINNs) further enhance these models by enforcing PDE constraints during training, enabling efficient nucleation time estimates with reduced computational overhead. Machine learning models, particularly from 2022 to 2025, leverage neural networks to predict mean time to failure (MTTF) from interconnect layout features, often outperforming traditional methods in speed and scalability.^[61] Graph neural networks (GNNs), such as EMGraph and graph attention variants, treat interconnect trees as graphs to forecast EM stress and MTTF, achieving errors below 1.5% compared to physics simulations while serving as a rapid baseline to Black's equation.^[66] These approaches, including EM-GAN frameworks, extract features like current density and geometry to enable full-chip assessments, with reported accuracies exceeding 93% for stress evolution in complex networks.^[67] Commercial tools from Synopsys and Cadence integrate EM checks into their flows, combining physics-based solvers with ML surrogates to streamline reliability verification.^[3] Synopsys PrimeSim EMIR and PrimeRail perform coupled EM-IR drop analysis at transistor and full-chip levels, while Cadence Voltus solutions offer SPICE-accurate EM signoff for power integrity.^[68] ML integration in these tools reduces simulation times by up to two orders of magnitude, facilitating iterative design optimization without sacrificing accuracy.^[69]

Advanced Applications and Developments

Electromigrated Nanogaps

Electromigrated nanogaps are nanoscale voids intentionally created in thin metal nanowires through controlled electromigration, enabling the fabrication of ultra-small electrode separations for advanced nanoelectronic devices. The process typically involves lithographically patterning nanowires of metals such as gold (Au) or platinum (Pt) with widths of 50–200 nm and thicknesses of 20–50 nm on insulating substrates like silicon oxide. A high current density, often exceeding 10^10 A/m², is then applied at room temperature, driving metal atoms to migrate under the electron wind force, leading to localized heating, void nucleation, and growth until the nanowire breaks, forming a gap of 1–100 nm. This method leverages the same physical mechanisms responsible for unintentional failures in interconnects but applies them constructively for device engineering. The formation of these nanogaps is precisely controlled using feedback systems that monitor the electrical resistance of the nanowire in real time. As electromigration proceeds, resistance increases due to thinning and voiding; when it reaches a predefined threshold (e.g., several kΩ), the current is automatically reduced or ramped to prevent catastrophic runaway melting and ensure a clean break. This feedback-controlled electromigration, pioneered in the mid-2000s, achieves reproducible gap formation in ambient conditions without requiring vacuum or cryogenic setups. Recent refinements, such as voltage ramping, have further improved uniformity by mitigating thermal gradients and reducing atomic-scale irregularities in gap morphology.^[70] These nanogaps serve as critical components in various applications, particularly in quantum and molecular electronics. In single-electron transistors, gaps of ~1 nm allow tunneling of individual electrons or molecules like C₆₀, enabling observation of Coulomb blockade and quantized conductance at room temperature.^[71] Molecular junctions formed by bridging the gap with organic molecules facilitate studies of charge transport at the single-molecule level, revealing phenomena such as negative differential resistance.^[72] Additionally, the intense electromagnetic fields in these sub-10 nm gaps enhance surface-enhanced Raman scattering (SERS), providing ultrasensitive detection of analytes with enhancement factors up to 10^8 for chemical and biological sensing.^[73] Advancements in 2024 have pushed gap precision below 1 nm, with feedback-controlled processes yielding stable tunnel junctions of 0.5–3 nm in gold arrays, suitable for quantum devices like on-chip molecular sensors. These developments include electromigration in liquid media for in situ device testing and post-fabrication annealing to stabilize conductance. Voltage ramping protocols enhance gap uniformity by limiting Joule heating, achieving yields of 60–70% in batch production.^[70] Despite these progresses, challenges persist in achieving high reproducibility across devices due to the stochastic nature of void nucleation and growth, which can vary with nanowire geometry and impurities. Contamination from ambient fabrication, such as oxide layers or adsorbates in the gap, often degrades electrical characteristics, necessitating cleanroom protocols or encapsulation techniques to maintain atomic-scale cleanliness for reliable quantum tunneling.^[72]^[70]

Electromigration in 3D ICs and Hybrid Bonding

In three-dimensional integrated circuits (3D ICs), through-silicon vias (TSVs) and microbumps are subjected to elevated thermal gradients and current densities compared to traditional two-dimensional interconnects, accelerating intermetallic compound (IMC) migration in Cu-Sn bonds and leading to void formation and reliability degradation.^[74]^[75] These conditions arise from the dense vertical stacking, where heat dissipation is constrained, exacerbating electromigration (EM) rates and reducing mean time to failure (MTTF) in high-current paths.^[74] Hybrid bonding, involving direct Cu/SiO₂ dielectric-metal interfaces, mitigates EM by forming seamless Cu-Cu contacts that eliminate solder-induced weaknesses, though bonding misalignment can create current hotspots and localized voiding.^[76] Studies from 2023 demonstrate that such bonds achieve EM performance comparable to back-end-of-line (BEOL) interconnects, with improved resistance due to optimized diffusion barriers like TaN/Ta, outperforming traditional microbumps in density and efficiency.^[74]^[76] Recent advances include 2024 analyses of interfacial microstructure evolution in hybrid-bonded stacked dies, revealing that grain orientations (e.g., dominant {111} textures) and special boundaries (e.g., twins comprising over 60%) significantly influence void nucleation and EM propagation under stress.^[77] Physics-based models for TSV voiding incorporate thermo-mechanical stresses from coefficient-of-thermal-expansion mismatches, predicting failure modes through coupled electro-thermo-mechanical simulations to guide design optimizations.^[78] TSMC's System on Integrated Chips (SoIC) technology addresses EM in 3D stacking through advanced interconnect processes, including selective capping layers that enhance Cu diffusion barriers.^[79]^[80] The integration of chiplets in heterogeneous 3D ICs amplifies EM risks from varying current densities across diverse functional blocks, necessitating tailored mitigation strategies to maintain reliability in multi-die systems.^[81] In 2025, in situ atomic-scale investigations have provided further insights into EM behaviors in Cu-filled TSVs for 3D IC packaging, enhancing reliability predictions.^[82]

References

[1]
Electromigration (all content) - DoITPoMS
Electromigration is the transport of material in a conductor under the influence of an applied electric field. All conductors are susceptible to ...
[2]
Electromigration - an overview | ScienceDirect Topics
Electromigration is defined as the phenomenon where metal atoms migrate due to the combined effects of high temperatures and electric current, resulting in ...
[3]
What is Electromigration? – How Does It Work? | Synopsys
Electromigration is the movement of atoms based on the flow of current through a material. If the current density is high enough, the heat dissipated within ...
[4]
Electromigration Failures in Integrated Circuits: A Review of Physics ...
Electromigration (EM), current-driven atomic diffusion in interconnect metals, critically threatens integrated circuit (IC) reliability via void-induced ...
[5]
https://doi.org/10.1109/PROC.1969.7340
[6]
[PDF] Recent advances on electromigration in very-large-scale-integration ...
Electromigration damage in Al lines was discovered in the. 1960s and was soon ... eutectic SnPb solder joint is sensitive to the thermal history of the ...
[7]
Electromigration in metals - IOPscience
This paper provides an overview on the current understanding of electromigration in metals. The discussion is first focused on studies in bulk metals and ...
[8]
https://iopscience.iop.org/article/10.1088/0034-4885/52/3/002
[9]
https://ieeexplore.ieee.org/document/1475796
[10]
2.1 The Electromigration Driving Force - IuE
Electromigration is the atomic migration caused by the action of microscopic forces on mobile defects. These microscopic forces arise due to the local electric ...Missing: definition | Show results with:definition
[11]
Electromigration in Thin Al Films - AIP Publishing
The process of electromigration in thin Al films was studied directly by transmission electron microscopy during passage of current. Due to electromigration ...
[12]
30 Years of Electromigration Research: A Grand Masters' Perspective
Feb 15, 2011 · The distinguished speakers were 1) Jim Black, of Motorola, who was responsible for Black's Equation; 2) Ilan Blech, who was perhaps the first ...<|separator|>
[13]
2.1 The History of Electromigration
In 1861, he discovered electromigration in liquid alloys of lead-tin, potassium-sodium, gold, and bismuth in mercury.Missing: James 1966 Texas Instruments
[14]
The effect of electrical current (DC) on gold thin films - ScienceDirect
Pioneering studies by microscopy of the EM process were made in the 60's using transmission electron microscopy (TEM) [5]and scanning electron microscopy (SEM) ...Missing: 1960s | Show results with:1960s
[15]
Electromigration failure modes in aluminum metallization for semiconductor devices
- **Publication Date**: 1969
[16]
An introduction to Cu electromigration - ScienceDirect.com
A major change for the interconnect system involved the replacement of Al thin-film wiring with less resistive Cu in the late 1990s in order to decrease ...
[17]
Advanced Interconnects: Materials, Processing, and Reliability
Dec 17, 2014 · Metallic conductivity and resistance to electromigration of bulk copper (Cu) were known to be better than those for aluminum (Al), which was the ...
[18]
Challenges in the implementation of low-k dielectrics in the back ...
In this paper, the challenges appearing during the integration of ultra low-k dielectrics will be discussed, since a proper understanding of these issues is ...
[19]
https://www.sciencedirect.com/science/article/pii/S0167931705002273
[20]
https://doi.org/10.3390/electronics14153151
[21]
https://doi.org/10.1007/978-3-031-80023-8_2
[22]
https://doi.org/10.1016/j.mser.2010.09.001
[23]
https://doi.org/10.1016/0022-3697(61)90138-X
[24]
https://ieeexplore.ieee.org/document/7936344
[25]
https://ieeexplore.ieee.org/document/6248890
[26]
https://doi.org/10.1016/j.jmps.2023.105257
[27]
In-situ studies of electromigration voiding in passivated copper ...
Nov 3, 1999 · Electromigration voids in copper lines, however, behave very differently. Voids often span the width of the line early in an electromigration ...Missing: migration | Show results with:migration
[28]
The electromigration effect revisited: non-uniform local tensile stress ...
Jun 8, 2017 · The electromigration (EM) effect describes atomic diffusion in conductors driven by electric currents, which may lead to the formation of voids and hillocks.
[29]
Electromigration Induced Step Bunching on Si Surfaces - IOP Science
The results provide a reasonable explanation of the observed step bunching on the (111) Si surface, which occurs either at moderate or at high temperature ...
[30]
Experimental quantitative study into the effects of electromigration ...
Apr 25, 2011 · We experimentally studied the effects of a moderated electromigration field on the dynamics of the step bunching process on the Si(111) ...
[31]
Influence of electromigration field on the step bunching process on ...
Aug 6, 2025 · We managed to isolate the effects of electromigration in the dynamics of the step bunching process on the vicinal Si(111) surface.
[32]
Improving electron mobility in InAs quantum wells on GaAs by ...
Jun 11, 2025 · The bunched steps lower the electron mobility in the quantum wells considerably when the GaAs substrates are used instead of InP substrates due ...Missing: roughening | Show results with:roughening
[33]
[PDF] international technology roadmap
wear-out phenomena are of particular interest, because they cause gradual slowing of the interconnect wiring, which can be addressed at system level ...
[34]
Electromigration – A Brief Survey - imanager
Electromigration is increasingly relevant to physical design of the electronic circuits. It is caused by excess current density stress in the interconnect. The ...
[35]
Addressing Electromigration and IR Drop Within VLSI Interconnect ...
Jul 31, 2020 · Electromigration has an effect on IR Drop. Electromigration also has additional effects on circuit designs to consider.
[36]
[PDF] Fast Electromigration Stress Analysis Considering Spatial Joule ...
Electromigration (EM) is the top reliability killer for copper-based interconnects of current integrated circuits (ICs) in 7 nm technology and below. The EM ...
[37]
[PDF] Combined Modeling of Electromigration, Thermal and Stress ...
ABSTRACT. The migration of atoms in metal interconnects in integrated circuits. (ICs) increasingly endangers chip reliability. The susceptibility of.
[38]
Electromigration induced Kirkendall void growth in Sn-3.5 Ag/Cu ...
Feb 28, 2014 · Electromigration induced Kirkendall void growth in Sn-3.5Ag/Cu solder ... reported that localized Kirkendall voids in Cu/Sn/Cu flip chip ...
[39]
[PDF] Effects of Electromigration (EM) on the Kirkendall Void Formation in ...
Kirkendall voids were preferentially distributed at the Cu/Cu3Sn interface in Sn-. 3.5Ag/Cu solder joint. Main cause of the localized void was S segregation at ...
[40]
A new failure mechanism of electromigration by surface diffusion of ...
Apr 12, 2018 · A new failure mechanism was found obviously in microbumps, which is the surface diffusion of Sn. Under EM testing, Sn atoms tend to migrate along the surface.<|control11|><|separator|>
[41]
https://ieeexplore.ieee.org/document/1319461
[42]
Electromigration analysis of solder joints under ac load: A mean time ...
Mar 19, 2012 · It was observed that MTF was inversely proportional to ambient temperature T1.1 in Celsius and also inversely proportional to current density j ...
[43]
Low-temperature hybrid bonding with high electromigration ...
Feb 1, 2023 · The novel low-temperature Cu/SiO 2 hybrid bonding scheme using cluster-Ag passivation has been proposed in this study for the heterogeneous integration ...
[44]
https://www.sciencedirect.com/science/article/pii/S0026271410000193
[45]
Physically based models of electromigration: From Black's equation ...
In this paper we present various electromigration models which have appeared in the last decades. We start from the very simple, one-dimensional models.
[46]
[PDF] Method for Characterizing the Electromigration Failure Distribution ...
The method assumes that Black's equation [1] (eq. ... if the stress current used generates Joule heating that elevates the temperature of a given test line by ...
[47]
Dual Damascene - an overview | ScienceDirect Topics
The melting point of copper is 1083 °C compared to 660 °C for Aluminum. Also ... The GB diffusion activation energy in Copper is 0.7–1.2 eV, compared ...<|separator|>
[48]
Prospective development in diffusion barrier layers for copper ...
Activation energy measured for electromigration in Cu ranges from 0.8 to about 0.9 eV in comparison to the ones measured for Al and its alloys, which range ...
[49]
Electromigration-induced stress in a confined bamboo interconnect ...
This changes the line microstructure from polycrystalline to a bamboo structure, in which all grain boundaries lie approximately in planes perpendicular to the ...<|separator|>
[50]
Electromigration-induced void growth in bamboo structures
These results suggest that the bamboo grain boundaries have a blocking effect on vacancy flow. This blocking produces vacancy supersaturation near the grain ...Missing: suppression | Show results with:suppression
[51]
Recent Advances in Barrier Layer of Cu Interconnects - PMC
Nov 9, 2020 · The barrier layer in Cu technology is essential to prevent Cu from diffusing into the dielectric layer at high temperatures; therefore, ...
[52]
Understanding electromigration failure behaviors of narrow cobalt ...
Jan 5, 2024 · The shrinkage of device dimensions toward sub-10-nm regimes inevitably causes an increase in areal densities of the current flowing through Cu ...
[53]
Graphene-All-Around Cobalt Interconnect with a Back-End-of-Line ...
The graphene-all-around (GAA) structure with cobalt interconnects shows increased current density, reduced resistance, and longer electromigration lifetime, ...
[54]
Electromigration Reliability of Barrierless Ruthenium and Molybdenum for Sub-10 nm Interconnection
### Summary of Electromigration Reliability of Ru and Co
[55]
[PDF] Electromigration-aware Redundant Via Insertion
By inserting redundant vias, we can mitigate the adverse effect of electromigration, because it can reduce the current density of each via.
[56]
Electromigration threshold in copper interconnects - AIP Publishing
Jun 4, 2001 · The length-dependent electromigration degradation rate is observed and quantified in the temperature range of 295–400 °C. Based on the Blech ...<|separator|>
[57]
[PDF] Fundamentals of Electromigration-Aware Integrated Circuit Design
Migration in copper wires is greatly affected by boundary effects due to the low activation energy for surface diffusion in copper (see. Table 2.1). Page 19 ...
[58]
Effect of via arrangement on electromigration performance
This paper addresses the impacts of via configuration on electromigration from both physical and statistical point of view.
[59]
JESD63 - JEDEC
Apr 17, 2023 · STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE: JESD63. Published: Apr 2023.Missing: limits | Show results with:limits
[60]
Electromigration challenges for advanced on-chip Cu interconnects
This usually requires higher electric current limits for circuit and chip designs. The gap between the maximum allowed current limit and the current limit ...Missing: standards | Show results with:standards
[61]
(PDF) Study of upstream electromigration bimodality and its ...
In Figure 5, the distribution of TTF for upstream and downstream scenarios for a given interconnect dimension, technology and current are shown. ...
[62]
Recent Progress in Physics-Based Modeling of Electromigration in ...
This paper introduces recent studies on physics-based modeling of electromigration aging of on-chip interconnects.
[63]
Electro-migration (EM) and voltage (IR) drop analysis of integrated ...
In an embodiment, the voltage levels at each nodes are determined using SPICE simulation, and the current in each path are computed by dividing the voltage ...<|separator|>
[64]
EMSpice: Physics-Based Electromigration Check Using Coupled ...
A physics-based system-level electromigration (EM) modelling platform is employed to simulate EM and its impact on the IR drop from the supply voltage to the ...Missing: SPICE | Show results with:SPICE
[65]
Electromigration Failures in Integrated Circuits: A Review of Physics ...
Oct 10, 2025 · Black, J.R. Electromigration failure modes in aluminum metallization for semiconductor devices. Proc. IEEE 1969,57, 1587–1594. [CrossRef].
[66]
[PDF] Grain morphology effects on void formation and electromigration ...
In this work, we develop a physics-based phase field model to investigate the void formation and evolution in copper interconnects subjected to electromigration ...
[67]
EMGraph: Fast electromigration stress assessment for interconnect ...
Jul 1, 2021 · EMGraph is a graph convolution network (GCN) model that estimates transient electromigration stress of interconnect trees, using node and edge ...
[68]
Electromigration Analysis for Interconnects Using Improved Graph ...
Aug 18, 2024 · In this paper, a novel approach is proposed, conceptualizing circuit interconnect trees as a graph within a graph neural network framework.
[69]
Voltus IC Power Integrity Solution - Cadence
The Cadence Voltus IC Power Integrity Solution is a comprehensive full-chip electromigration, IR drop, and power analysis solution.
[70]
[PDF] Machine Learning Approach for Fast Electromigration Aware Aging ...
In this paper, for the first time, we propose a machine learning approach to obtain the EM-aware aging prediction of the PG network. We use neural network-based ...Missing: 2022-2025 | Show results with:2022-2025
[71]
Electromigrated Gold Nanogap Tunnel Junction Arrays: Fabrication ...
Jul 2, 2024 · We perform a comparative study of the formation and electrical behavior of arrays of gold nanogap tunnel junctions made by feedback-controlled electromigration.
[72]
Electromigrated Nanoscale Gaps for Surface-Enhanced Raman ...
We present a simple, scaleable substrate for surface-enhanced Raman spectroscopy (SERS) incorporating nanometer-scale electromigrated gaps between extended ...
[73]
Electromigrated gold nanogap tunnel junction arrays - ChemRxiv
Feb 19, 2024 · Fabricating nanogaps by electromigration is one of the most promising approaches to realize on-chip integrated tunnel junction sensors. However, ...
[74]
Electromigrated nanogaps: A review on the fabrications and ...
Jan 21, 2021 · In this review, we discuss the recent progress and challenges of electromigration methods for a nanogap creation as well as their applications for electronic ...
[75]
Electromigration in three-dimensional integrated circuits
May 16, 2023 · The diameters of the micro-bumps vary from 10 to 20 μm, resulting in an interconnect density of 1 × 105–1 × 106 joints/cm2. Reducing the micro- ...
[76]
Electromigration of Cu-Sn-Cu micropads in 3D interconnect
Aug 9, 2025 · In this paper the EM performance of 3D Cu-Sn microconnects formed by thermo-compression bonding is investigated and the failure mechanisms are ...
[77]
Recent Advances on Electromigration in Cu/SiO 2 to Cu/SiO 2 Hybrid Bonds for 3D Integrated Circuits | Request PDF
**Summary of Electromigration in Cu/SiO₂ Hybrid Bonds:**
[78]
Role of Interfacial Microstructure on Electromigration Behavior of ...
Apr 22, 2024 · In this study, we explore the scaling effect of Cu pad diameters (0.8 – 4 μm) and pitch spacings (2 – 10 μm) on the electromigration behavior of ...Missing: analysis ICs
[79]
TSV Electromigration Failure Prediction Using Multiphysics Coupled ...
TSVs undergo electro-thermo-mechanical multiphysics coupling during operation, where complex fabrication and extreme conditions precipitate novel failure modes.
[80]
TSMC-SoIC® - Taiwan Semiconductor Manufacturing Company ...
TSMC-SoIC® features ultra-high-density vertical stacking for high performance, low power, and minimum resistance, inductance, and capacitance (RLC). Key TSMC- ...Missing: electromigration | Show results with:electromigration
[81]
ECTC 2020 TSMC SoIC for Low-Temperature Multi-Layer 3D ...
Oct 21, 2021 · However, there are challenges in bandwidth, capacity, thermal dissipation and stacking height for the 3Dμ-bump stacking memory when more memory ...
[82]
Electromigration Concerns Grow In Advanced Packages
Apr 18, 2024 · Electromigration concerns grow in advanced packages. Higher density, heat, and more materials make it harder to ensure reliability.