MOS Technology 6507
The MOS Technology 6507 is an 8-bit NMOS microprocessor developed by MOS Technology, Inc., as a cost-reduced variant of the 6502 CPU, packaged in a 28-pin DIP with a 13-bit address bus (A0–A12) enabling access to 8 KB of memory, an 8-bit bidirectional data bus (D0–D7), and full compatibility with the 6502's instruction set and architecture.[1] It supports clock speeds up to 2 MHz with external clock inputs and includes features like a ready (RDY) signal for DMA or slow-memory interfacing, but omits pins for interrupts (IRQ and NMI) in its standard configuration to minimize complexity and cost.[1] Operating on a +5 V supply with typical power consumption of 70 mA at 1 MHz, the 6507 was optimized for embedded systems where full 64 KB addressing was unnecessary.[1][2] Introduced in 1975 as part of the broader 6500 family, the 6507 emerged from MOS Technology's efforts—led by engineers like Chuck Peddle who had defected from Motorola—to disrupt the microprocessor market with affordable alternatives to high-priced chips like the Intel 8080.[3] The 6502 debuted at $25 in 1975, and the 6507 further slashed costs by bonding out fewer pins from the same silicon die, targeting OEMs and consumer devices.[3] After Commodore acquired MOS Technology in 1976, the design was licensed to firms like Synertek and Rockwell International, ensuring its longevity into the 1980s.[2] This economical approach made the 6507 a key enabler of early personal computing and gaming innovations.[4] The 6507's most prominent application was in Atari's Video Computer System (VCS, rebranded Atari 2600 in 1982), where it served as the central processor running at 1.19 MHz, interfacing with custom TIA and RIOT chips for graphics, sound, and I/O in a system with only 128 bytes of RAM.[2] This configuration powered groundbreaking titles like Pong successors and Pac-Man, contributing to over 30 million units sold and defining the second-generation video game console era.[3] It also appeared in Atari's 810 floppy disk drive controller for the 8-bit computer family, handling data transfer in a memory-constrained peripheral.[2] Though less versatile than the full 6502—lacking direct interrupt support, which Atari mitigated via software polling—the 6507's efficiency influenced later 8-bit designs in gaming.[2]History
Development Background
MOS Technology was established in 1969 in Valley Forge, Pennsylvania, by former General Instrument executives John Paivinen, Mort Jaffe, and Don McLaughlin to produce metal-oxide-semiconductor (MOS) integrated circuits.[5] In 1974, Chuck Peddle, an engineer who had contributed to Motorola's 6800 microprocessor, joined the company along with several colleagues, shifting focus toward developing affordable 8-bit processors to challenge higher-priced offerings from Intel and Motorola during the mid-1970s microprocessor expansion.[6] This effort emphasized low-cost chips for logic replacement in industrial and consumer applications, leveraging MOS's expertise in high-yield fabrication techniques like mask fixing to achieve competitive pricing.[7] By 1976, following the successful launch of the 6502 microprocessor in 1975, MOS identified a market need for even more economical variants suited to embedded systems with constrained resources.[8] The 6507 emerged from this initiative as a lower-pin-count derivative, designed to minimize manufacturing costs and reduce printed circuit board space for applications like consumer electronics that required minimal memory addressing.[3] Priced lower than the full-featured 6502, the 6507 targeted emerging sectors such as video game consoles, where full 64 KB addressing was unnecessary.[6] The 6502's rapid adoption in development kits like the 1976 KIM-1 single-board computer demonstrated its versatility but highlighted opportunities to adapt the architecture for memory-limited environments.[9] MOS engineers, led by Peddle, retained the core 6502 instruction set and processing logic in the 6507 while simplifying the external interface to prioritize cost efficiency over expandability.[4] A pivotal design choice involved scaling the address bus from 16 bits to 13 bits, restricting direct addressing to 8 KB while preserving compatibility with the 6502's zero-page and stack operations for efficient code in small-memory systems.[1]Production and Release
The MOS Technology 6507 microprocessor was introduced in 1976, shortly following the 6502's market debut in September 1975.[4][3] Fabricated using NMOS technology, the 6507 was produced in a cost-optimized 28-pin dual in-line package (DIP), which eliminated unused pins from the full 40-pin 6502 design to lower packaging and material expenses.[2][10] MOS Technology's emphasis on affordability supported its use in embedded applications.[11][12] In October 1976, Commodore International acquired MOS Technology in exchange for a 9.4 percent equity stake in Commodore, renaming its semiconductor operations the Commodore Semiconductor Group (CSG) and sustaining 6507 production through the 1980s to support Commodore's systems and external customers.[9][13][14] MOS Technology provided early samples of the 6507 to partners including Atari in 1976, enabling its evaluation and subsequent incorporation into late-1976 prototypes for the Atari Video Computer System (VCS), later released as the Atari 2600.[2][12]Design and Architecture
Relation to the 6502
The MOS Technology 6507 is a derivative of the 6502 microprocessor, sharing an identical core logic implementation across the underlying silicon layers while differing primarily in the final metallization layer, which repurposes pins and configures internal interrupt connections.[1] This design approach allowed MOS Technology to produce a cost-optimized variant without altering the fundamental processing architecture.[1] With 28 pins compared to the 6502's 40-pin package, the 6507 achieves this reduction by removing the A13–A15 address lines and the external IRQ and NMI interrupt pins.[1] The absent address lines limit the processor to a 13-bit address bus (A0–A12), supporting only 8 KB of addressable memory space.[1] Meanwhile, the IRQ and NMI pins are hardwired internally to their inactive states, eliminating support for external hardware interrupts and requiring software polling for event detection.[15] Despite these hardware simplifications, the 6507 remains fully instruction-compatible with the 6502, executing the same 56 instructions across 13 addressing modes.[1] These modifications focused on reducing manufacturing and packaging costs while preserving software portability within the constrained address range.[1]Key Architectural Features
The MOS Technology 6507 is an 8-bit NMOS microprocessor featuring an accumulator-based architecture designed for efficient parallel processing of data and instructions.[1] Central to its design is the accumulator register (A), which serves as the primary location for arithmetic and logical operations, supported by two 8-bit index registers (X and Y) for addressing and temporary storage, a 16-bit program counter (PC) for instruction sequencing, an 8-bit stack pointer (S) for managing the hardware stack, and an 8-bit processor status register (P) that holds condition flags including carry (C), zero (Z), interrupt disable (I), decimal mode (D), break command (B), overflow (V), and negative (N).[1] This register set enables flexible data manipulation while maintaining a compact internal structure optimized for cost-sensitive embedded applications.[16] The 6507's instruction set comprises 56 distinct instructions, directly compatible with the MOS 6502, encompassing a range of operations such as arithmetic instructions like add with carry (ADC) and subtract with carry (SBC) in both binary and binary-coded decimal modes, logical instructions including bitwise AND (AND) and inclusive OR (ORA), control flow instructions such as unconditional jump (JMP) and jump to subroutine (JSR), and stack management instructions like push accumulator (PHA) and pull accumulator (PLA).[1] These instructions support 13 addressing modes, including immediate, absolute, zero-page, and indexed variants, allowing programmers to balance code density and execution efficiency without hardware-specific modifications.[16] Internally, the 6507 employs a two-phase non-overlapping clock mechanism to drive its minimal pipeline, which overlaps instruction fetch and execution phases to achieve throughput for instructions ranging from 1 to 7 cycles.[16] This design minimizes latency in opcode decoding and operand fetching while relying on an on-chip clock generator for simplified integration.[1] Power consumption is characteristic of NMOS technology, with a typical supply current of 70 mA at 5 V and 1 MHz, equating to approximately 0.35 W, and all I/O pins maintain TTL-compatible voltage levels for direct interfacing with standard logic families.[1]Addressing Capabilities
The MOS Technology 6507 features a 13-bit address bus (A0–A12), which enables direct addressing of up to 8 KB (8192 bytes) of memory space, corresponding to hexadecimal addresses 0000–1FFF.[1] This limitation arises from the chip's 28-pin package, which omits the higher address lines (A13–A15) present in the full 16-bit 6502, thereby reducing pin count while maintaining compatibility with the core instruction set.[1] The 6507 supports 13 addressing modes inherited from the 6502 architecture, adapted to its constrained bus width: zero-page (using the first 256 bytes, or 00–FF, for efficient single-byte operands), absolute (limited to the full 8 KB range for direct memory access), indirect (via a pointer in memory), indexed (with X or Y registers for offset addition), and implied (using no explicit operand).[1] Zero-page and indexed modes enhance code density and speed by avoiding full address fetches, while absolute and indirect modes provide flexibility within the 8 KB boundary, though page-crossing in indexed operations remains possible only up to the addressable limit.[1] These modes leverage the same accumulator, index registers (X and Y), and stack pointer as the 6502 for operand calculation.[1] Unlike some contemporaries with dedicated I/O ports, the 6507 employs fully memory-mapped addressing, where input/output operations share the same 8 KB space as program and data memory via the bidirectional 8-bit data bus (D0–D7).[1] To accommodate slower memory or peripherals, the RDY (Ready) input pin allows the processor to halt execution during the φ1 clock phase if pulled low, resuming upon return to high, thus supporting reliable interfacing without built-in wait-state generation.[1] This addressing scheme facilitates compact, low-cost embedded systems by minimizing external decoding logic, but the 8 KB ceiling necessitates techniques like bank-switching or address mirroring to expand effective memory in larger applications, such as video game consoles requiring more than 8 KB of ROM or RAM.[10]Technical Specifications
Electrical and Timing Parameters
The MOS Technology 6507 microprocessor operates on a single +5 V DC power supply with a tolerance of ±0.25 V (4.75 V to 5.25 V), ensuring stable performance within standard TTL environments. The absolute maximum supply voltage is +7 V to prevent damage from overvoltage conditions.[17] The device exhibits a maximum current consumption of 160 mA when operating at 1 MHz, reflecting its NMOS technology and integration of clock circuitry.[17] Operating temperature range spans 0°C to 70°C, suitable for consumer electronics applications, while storage temperature extends from -55°C to 150°C for reliability during non-powered conditions.[17] I/O characteristics employ totem-pole outputs, capable of sinking up to 1.6 mA at a low-level voltage of 0.4 V and sourcing 1 mA at a high-level voltage of 2.4 V, providing full compatibility with TTL logic thresholds.[17]| Parameter | Specification | Conditions/Notes |
|---|---|---|
| Supply Voltage (VCC) | +5 V DC ±0.25 V (recommended); +7 V max | Absolute maximum to avoid damage |
| Current Draw (ICC) | 160 mA maximum | At 1 MHz clock frequency |
| Operating Temperature | 0°C to 70°C | Ambient (TA) |
| Storage Temperature | -55°C to 150°C | Non-operating |
| Output Sink Current (IOL) | 1.6 mA at VOL = 0.4 V | Totem-pole configuration |
| Output Source Current (IOH) | 1 mA at VOH = 2.4 V | TTL-compatible levels |
Clocking and Performance
The MOS Technology 6507 employs a two-phase, non-overlapping clock system with φ1 and φ2 signals to synchronize internal operations. These clock phases can be provided externally or generated on-chip using a single-phase input from a crystal, RC network, or external source. The processor supports maximum clock frequencies up to 3 MHz in its configuration options, though the standard variant is rated up to 2 MHz.[10][1] Instruction execution on the 6507 requires between 2 and 7 clock cycles, varying by opcode and addressing mode, with no built-in wait states during normal operation. For instance, the LDA instruction in immediate mode completes in 2 cycles, while the JSR subroutine call takes 6 cycles. This cycle-based timing enables efficient pipelining of fetch, decode, and execute phases within each instruction.[1][10] Overall performance reaches approximately 0.5 MIPS when clocked at 1 MHz, influenced by factors such as code density and the mix of instruction types. The READY pin provides synchronization flexibility by allowing cycle stretching: when pulled low during φ1 or up to 100 ns after φ2, it halts the processor until the pin returns high, accommodating slower peripherals without additional hardware.[10]Interfaces and Pinout
Pin Configuration Overview
The MOS Technology 6507 microprocessor is packaged in a 28-pin dual in-line package (DIP), optimized for low-cost applications requiring only 8 KB of addressable memory space. This configuration reduces manufacturing expenses compared to the full 40-pin 6502 by omitting higher-order address lines (A13–A15) and certain control pins such as non-maskable interrupt (/NMI), synchronization (SYNC), and set overflow (SO).[10][18] The pins follow the conventional DIP numbering scheme, with pins 1 through 14 along one side (from the notch end) and pins 28 down to 15 along the opposite side. They are grouped into categories to facilitate interfacing: 13 unidirectional address output pins (A0–A12) for memory and peripheral selection; 8 bidirectional data pins (D0–D7) for input and output transfers; two non-overlapping two-phase clock inputs (φ1 and φ2) for timing synchronization; control signals including read/write (R/W) for bus direction, ready (RDY) for halting execution during slow memory access, and active-low reset (/RES) for initialization; and power supply pins consisting of Vss (ground) and Vdd (+5 V).[18][19] The following table illustrates the pin assignments, emphasizing their positions and types for hardware integration:| Pin | Signal | Type | Category |
|---|---|---|---|
| 1 | /RES | Input | Control |
| 2 | Vss | [Power | Supply](/page/Power_supply) |
| 3 | RDY | Input | Control |
| 4 | Vdd | [Power | Supply](/page/Power_supply) |
| 5 | A0 | Output | Address |
| 6 | A1 | Output | Address |
| 7 | A2 | Output | Address |
| 8 | A3 | Output | Address |
| 9 | A4 | Output | Address |
| 10 | A5 | Output | Address |
| 11 | A6 | Output | Address |
| 12 | A7 | Output | Address |
| 13 | A8 | Output | Address |
| 14 | A9 | Output | Address |
| 15 | A10 | Output | Address |
| 16 | A11 | Output | Address |
| 17 | A12 | Output | Address |
| 18 | D7 | Bidirectional | Data |
| 19 | D6 | Bidirectional | Data |
| 20 | D5 | Bidirectional | Data |
| 21 | D4 | Bidirectional | Data |
| 22 | D3 | Bidirectional | Data |
| 23 | D2 | Bidirectional | Data |
| 24 | D1 | Bidirectional | Data |
| 25 | D0 | Bidirectional | Data |
| 26 | R/W | Output | Control |
| 27 | φ1 | Input | Clock |
| 28 | φ2 | Input | Clock |