Printed circuit board
A printed circuit board (PCB) is a flat, rigid or flexible board composed of insulating material, such as fiberglass-reinforced epoxy, with thin layers of conductive material—typically copper foil—etched to form pathways that electrically connect and mechanically support electronic components like resistors, capacitors, and integrated circuits.[1][2] These boards serve as the foundational platform for constructing electronic circuits, enabling compact, reliable interconnections in devices ranging from simple radios to complex computing systems.[3][4] The origins of PCBs trace back to the early 20th century, with German inventor Albert Hanson receiving a patent in 1903 for a flat conductive foil laminated between insulating layers to replace point-to-point wiring in telephony equipment.[5] This was followed by Charles Ducas's 1927 patent for printed wiring using conductive inks on insulating boards. However, the modern etched PCB was pioneered by Austrian engineer Paul Eisler in 1936, who developed the technology while designing a radio set in England; his design used a copper foil pattern on a non-conductive base, which was patented in 1943 and first applied in military radio equipment during World War II.[4][5] Post-war commercialization in the 1950s, driven by the electronics boom and the U.S. space program, transformed PCBs into a mass-produced essential, evolving from single-layer boards to multi-layer designs with through-hole technology in the 1960s and surface-mount technologies in the 1980s.[5][4] Today, PCBs are ubiquitous in modern electronics, underpinning applications from consumer products like smartphones and appliances to advanced fields such as medical devices, automotive systems, and environmental sensors.[5][3] Common types include rigid PCBs for structural stability, flexible PCBs using polyimide substrates for bendable applications like wearables, and rigid-flex hybrids for compact, durable designs in aerospace and medical equipment.[2] Fabrication typically involves subtractive etching of copper from laminated sheets, followed by application of solder masks and silkscreen markings, with additive manufacturing emerging for rapid prototyping using conductive inks.[1][4] As electronic devices continue to miniaturize and integrate more functions, advancements in PCB design focus on high-density interconnects, thermal management, and sustainability to meet demands in high-speed computing and renewable energy systems.[6]History
Precursors and early inventions
Before the advent of printed circuit boards, electronic circuits were primarily assembled using manual point-to-point wiring techniques, where individual components were connected directly with soldered wires on a chassis or insulating base.[7] This method, common in early radio receivers and telephone equipment, involved hand-soldering wires from one component terminal to another, often resulting in bulky, tangled assemblies that were labor-intensive to construct and prone to failures from vibration-induced loose connections or solder joint fatigue.[8] Similarly, wire-wrap techniques emerged as a manual predecessor, originating from telephone switchboard wiring in the early 20th century, where insulated wire was tightly wrapped around component pins using a tool to create gas-tight, solderless connections; however, these methods remained unreliable for complex circuits due to their time-consuming nature and susceptibility to wiring errors in high-density applications.[9] One of the earliest conceptual precursors to modern PCBs appeared in 1903, when German inventor Albert Hanson filed British Patent No. 4,681, describing a method for creating flat foil conductors laminated between layers of paraffin-coated paper insulation to form multi-layer wiring for telephone systems. Hanson's design aimed to replace cumbersome manual wiring with a more organized, flat structure, though it lacked practical etching or printing processes and was not widely implemented at the time.[10] In 1913, British engineer Arthur Berry advanced these ideas with Patent No. 16,794, which outlined a print-and-etch method for producing conductive patterns by applying a resist to a metal sheet, etching away unwanted areas with chemicals, and leaving behind circuit traces on an insulating substrate. This technique introduced the foundational concept of selective metal removal to define wiring paths, addressing some limitations of manual methods by enabling more precise and reproducible circuit layouts, although production remained manual and small-scale.[11] Building on this, American inventor Charles Ducas patented a stencil-based approach in 1925 (U.S. Patent No. 1,563,731), using conductive inks—mixtures of metallic particles in a liquid carrier—to print electrical pathways directly onto an insulated surface, such as wood or paper, thereby simplifying the creation of fixed wiring without etching.[12] Conductive inks represented an early shift toward additive manufacturing of circuits, offering flexibility for curved or irregular substrates but limited by the inks' lower conductivity compared to solid metals.[13] During the 1920s, radio chassis designs began incorporating fixed component mounting to mitigate wiring issues, with vacuum tubes, resistors, and capacitors secured directly to metal frames using clamps or lugs, connected via short point-to-point wires or bus bars to reduce length and improve stability in tuned radio frequency (TRF) receivers.[14] These chassis-based assemblies, prevalent in battery-powered home radios, still relied on manual wiring but demonstrated growing efforts to standardize layouts for reliability amid the radio boom.[15] The foil etching concept gained further traction in 1936 through the work of Austrian inventor Paul Eisler, who developed a process involving photographic printing and chemical etching of copper foil on an insulating backing to produce radio circuits.[16] Eisler's innovation combined resist application, exposure, and etching to create durable, planar conductive patterns, laying the groundwork for scalable production while overcoming the unreliability of hand-wired prototypes.[7] These pre-1940s developments transitioned into practical PCB implementations during World War II, enabling mass production for military electronics.Development of modern PCBs
The etched foil technique, foundational to modern printed circuit boards (PCBs), was developed by Austrian engineer Paul Eisler in 1936 and patented in 1943 while working on military radio equipment during World War II. Eisler developed a method to print circuit patterns on copper foil laminated to an insulating substrate, followed by etching to remove excess metal, creating precise conductive traces without manual wiring. This innovation built on earlier precursors like conductive inks but introduced a scalable etching process for rigid boards. He filed the initial patent application in the United Kingdom on February 2, 1943 (GB639178A), which was granted in 1949, and a corresponding U.S. patent application followed on February 3, 1944, granted on May 25, 1948 (US2441960A).[17][18][19] The U.S. military adopted Eisler's technology during the war for proximity fuses in artillery shells, leveraging its reliability in compact, vibration-resistant electronics. In 1948, following declassification, the U.S. government released the invention for commercial use, enabling broader adoption. One of the earliest consumer applications was in hearing aids, with the Solo-Pak model from Allen-Howe Electronics Corp. introducing the first printed circuit-based device that year, significantly reducing size and improving portability compared to vacuum-tube predecessors.[20][21] By the early 1950s, commercial production ramped up, with companies like Technitrol adopting PCB manufacturing for electronic components such as transformers and delay lines. A key advancement came in 1953 when Motorola introduced double-sided PCBs with plated-through holes (PTH), allowing electrical connections between layers via electroplated vias, which overcame limitations of single-sided designs. Early PCBs, however, faced significant challenges, including insulation reliability issues where dielectric materials like paper-phenolic laminates degraded in humid or high-temperature environments, leading to shorts or failures. The shift from single-sided to double-sided boards addressed routing complexity for denser circuits but required precise PTH plating to ensure robust interlayer connections, marking a critical evolution in reliability and manufacturability.[22][23]Post-World War II expansion
Following World War II, the adoption of printed circuit boards (PCBs) accelerated as military technologies transitioned to commercial applications, fostering rapid industry growth and the need for standardization. The Institute for Printed Circuits (IPC), founded in 1957 by six U.S. PCB manufacturers, played a pivotal role in establishing uniform design, manufacturing, and testing standards to support expanding production.[24] Early military specifications, such as MIL-P-55110 issued in the early 1960s, further drove reliability requirements for PCBs in defense electronics, emphasizing rigorous qualification for environmental durability and performance.[25] The 1960s marked a breakthrough with the introduction of multilayer PCBs, typically featuring 4 or more layers, which enabled denser interconnections essential for emerging computing systems. IBM's System/360 mainframe, launched in 1964, utilized these multilayer boards in its Solid Logic Technology (SLT) modules, where small ceramic substrates with hybrid circuits were mounted on 2- to 4-layer printed cards to achieve higher integration and reliability in large-scale data processing.[26] This innovation supported the shift from single- and double-sided boards to more complex structures, accommodating the growing complexity of electronic systems in aerospace and early computers.[27] By the 1970s, manufacturing automation transformed PCB production, with mechanized drilling machines and chemical etching processes enabling precise hole formation and pattern transfer at scale, reducing labor costs and improving consistency. Precursors to surface-mount technology (SMT), such as planar mounting techniques developed by IBM in the late 1960s, gained traction during this decade, allowing components to be attached directly to the board surface without through-holes and paving the way for higher component density in consumer devices.[28][29] This period saw the PCB industry expand dramatically, transitioning from a niche military supplier to a cornerstone of consumer electronics, with U.S. shipments alone growing from approximately $1.3 billion in 1977 to $2.9 billion by 1981, driven by the boom in televisions, calculators, and home appliances.[30] reflecting widespread adoption in everyday products and the economic impact of miniaturized electronics.Contemporary developments and innovations
The 1990s marked a revolution in PCB design through the widespread adoption of computer-aided design (CAD) software, which enabled automated routing and streamlined the transition from schematic capture to physical layout. Tools like Protel, which evolved into Altium Designer, introduced user-friendly graphical interfaces under Microsoft Windows, allowing engineers to integrate schematic design with automated PCB routing for increasingly complex circuits. Similarly, Eagle software gained popularity among hobbyists and small firms for its affordability and ease of use in generating precise trace patterns, significantly reducing manual design time and errors in multilayer boards.[31] In the 2000s, high-density interconnect (HDI) technology emerged as a key innovation driven by the miniaturization demands of smartphones, incorporating laser-drilled microvias and finer line widths down to 40μm to pack more components into compact spaces. This shift from staggered to stacked vias and the introduction of "any layer" constructions allowed for higher functionality in mobile devices, maintaining the subtractive manufacturing process while enabling denser interconnections essential for early smartphones. Building on these foundations, the European Union's Restriction of Hazardous Substances (RoHS) directive, effective July 1, 2006, mandated lead-free soldering in PCBs to limit hazardous materials like lead to under 1000 ppm, prompting the adoption of higher-temperature alloys and surface finishes such as ENIG to ensure reliability without environmental harm.[32][33] Recent years have seen the PCB market expand rapidly, valued at USD 81.01 billion in 2025 with a projected compound annual growth rate (CAGR) of 5.24% through 2030, fueled by innovations in high-frequency applications and sustainable practices. Flexible PCBs have become integral to wearables, offering thin, lightweight, and bendable designs that conform to body contours while supporting compact electronics in devices like smartwatches and fitness trackers. Additive manufacturing techniques, including 3D printing, have transformed prototyping by building PCBs layer-by-layer with conductive inks like silver or graphene, achieving resolutions as fine as 20 microns and reducing material waste compared to traditional subtractive methods, which can cut energy consumption and emissions significantly.[34][35][36] From 2023 to 2025, AI-driven tools have advanced design optimization and auto-routing, shortening trace lengths by up to 20% and design cycles by 30% while predicting signal integrity for high-speed boards, as seen in platforms like Zuken's CR-8000. 3D-printed PCBs further support rapid prototyping of multilayer (up to 6 layers) and flexible structures using polyimide substrates, enabling data rates up to 10 Gbps at costs as low as $20–$100 per small board, ideal for custom IoT devices. Integration with 5G and IoT has necessitated PCBs capable of handling higher frequencies, including millimeter-wave bands, through low-loss materials and precise impedance control to minimize signal attenuation in dense networks.[37][38][39] Innovations in materials like graphene conductors continue to enhance performance, with graphene-coated copper traces providing five times the thermal conductivity of copper alone, reducing heat buildup in high-power 5G and RF applications while enabling lighter, flexible boards for wearables. These developments collectively address sustainability and efficiency, with additive processes and bio-based laminates lowering environmental impact amid growing demand for AI servers, electric vehicles, and 5G infrastructure.[40][34]Design Principles
Circuit layout and schematic design
The design of a printed circuit board (PCB) begins with the creation of an electrical schematic, which visually represents the interconnections and functions of electronic components using standardized symbols. This schematic captures the logical flow of signals, power, and ground paths, ensuring that the circuit's intended behavior is clearly defined before physical layout. Engineers use schematic capture software to draw these diagrams, verifying functionality through simulations that check for issues like timing errors or power imbalances. Once validated, the schematic generates a netlist—a textual file listing all electrical connections between components—which serves as the blueprint for translating the design into a physical board layout. Component placement follows the netlist, where engineers position parts on the board to optimize electrical performance, manufacturability, and thermal dissipation. Key considerations include minimizing signal path lengths to reduce noise and delays, grouping high-speed components together, and placing power-hungry elements away from sensitive analog sections. For instance, decoupling capacitors are strategically positioned close to integrated circuits—typically within 1-2 cm—to filter high-frequency noise and stabilize voltage supplies by providing local charge reservoirs. This placement rule stems from the need to counteract parasitic inductances in power traces, as outlined in industry guidelines. Ground planes, large copper areas connected to the circuit's reference ground, are incorporated during placement to provide a low-impedance return path for currents, shielding signals from electromagnetic interference and aiding in heat spreading. Thermal management in layout involves spacing components to allow airflow, using thermal vias under heat-generating parts like power transistors, and selecting pad sizes that facilitate efficient heat transfer without compromising board density. Trace routing connects the placed components according to the netlist, following design rules to prevent shorts, opens, or crosstalk. Traces are routed as copper paths on the board's surface or internal layers, with rules specifying minimum widths, clearances, and lengths; for high-density boards, minimum trace widths often reach 0.1 mm to accommodate fine-pitch components while maintaining reliability under current loads. Routing prioritizes critical nets first—such as clocks or high-speed data lines—using techniques like differential pairs for balanced signals and avoiding sharp bends (preferring 45-degree angles) to minimize reflections. Automated autorouters in software can assist, but manual intervention ensures adherence to constraints like avoiding traces under crystals to prevent microphonics. Electronic design automation (EDA) tools are essential for the entire schematic-to-layout process, enabling simulation, placement optimization, and routing. Popular open-source options like KiCad facilitate schematic entry, netlist generation, and interactive routing with built-in design rule checks, while commercial suites such as OrCAD from Cadence offer advanced features like SPICE-based analog simulation to predict circuit behavior pre-layout. These tools enforce design rules, such as minimum trace width and via sizes, configurable per project to match fabrication capabilities—typically starting at 0.15 mm for standard prototypes but scaling to 0.1 mm for high-density interconnects (HDI) boards. Trace sizing is determined using the resistance formula R = \rho \frac{L}{A}, where R is the trace resistance in ohms, \rho is the resistivity of the conductor material (1.68 × 10^{-8} Ω·m for copper at 20°C), L is the trace length in meters, and A is the cross-sectional area in square meters. For a typical 1 oz/ft² copper layer (35 μm thick), a 0.25 mm wide trace carrying 1 A over 10 cm would have A = 0.25 \times 10^{-3} \times 35 \times 10^{-6} = 8.75 \times 10^{-9} m², yielding R \approx 0.19 Ω, which is acceptable for low-voltage drops but requires wider traces (e.g., 0.5 mm) for higher currents to limit heating via I^2R losses. This calculation ensures traces can handle expected currents without excessive voltage drop or thermal runaway, often iterated within EDA tools.Layer stacking and via structures
In multilayer printed circuit boards (PCBs), layers are categorized by function to optimize signal routing, power distribution, and grounding. Signal layers primarily carry high-speed data traces, while power and ground layers provide dedicated planes for voltage supply and return paths, respectively, reducing noise and improving electromagnetic compatibility.[41][42] The buildup process alternates rigid cores—fully cured dielectric substrates with copper cladding on both sides—and prepregs, which are semi-cured resin-impregnated fiberglass sheets that bond layers during lamination while providing insulation.[43][44] Vias serve as vertical interconnects between layers, with types selected based on board density and manufacturing constraints. Through-hole vias penetrate the entire board thickness, connecting all layers and accommodating component leads, but they occupy more space and limit routing density.[45] Blind vias connect an outer layer to an inner layer without traversing the full board, while buried vias link only inner layers, both enhancing density by avoiding surface penetration.[46] Microvias, typically smaller than 0.15 mm in diameter, enable high-density interconnects (HDI) and are often laser-drilled for precision.[47] Aspect ratios, defined as the ratio of via depth to drill diameter, influence reliability; through-hole vias commonly achieve up to 10:1, whereas microvias are limited to 1:1 to prevent plating voids and ensure structural integrity.[46][48] Layer stacking sequences are designed to balance mechanical stability, thermal management, and electrical performance, with impedance control achieved by precise spacing between signal traces and reference planes. A common 4-layer configuration follows a signal-ground-power-signal sequence, where the inner ground and power planes sandwich the outer signal layers, minimizing crosstalk and providing a low-impedance return path.[49][50] This arrangement supports controlled impedance traces, often targeting 50 ohms for single-ended signals through optimized prepreg thickness and copper weight.[51] High-density interconnect (HDI) boards extend these principles using sequential lamination, where layers are built incrementally to incorporate complex via structures. In this process, subsets of cores and prepregs are laminated, drilled, and plated in cycles—up to eight for advanced designs—allowing stacked or staggered microvias with diameters under 0.1 mm.[52][53] Laser-drilled microvias in HDI facilitate finer pitch routing, supporting applications like smartphones and medical devices by reducing board size while maintaining connectivity across multiple layers.[54]| Via Type | Description | Typical Aspect Ratio | Diameter Range |
|---|---|---|---|
| Through-hole | Connects all layers; used for components and general interconnects | Up to 10:1 | >0.15 mm |
| Blind | Connects outer to inner layer; one end open on surface | 1:1 to 3:1 | 0.1–0.15 mm |
| Buried | Connects inner layers only; not visible on surfaces | 1:1 to 3:1 | 0.1–0.15 mm |
| Microvia | High-density, laser-drilled; for HDI boards | 1:1 | <0.1 mm |
Signal integrity and electrical properties
Signal integrity in printed circuit boards (PCBs) refers to the preservation of electrical signal quality as it propagates through traces and vias, influenced primarily by the board's material properties and layout geometry. The dielectric constant (ε_r) of the substrate material, such as FR-4, typically ranges from 3.8 to 4.8, depending on factors like glass weave style, thickness, and resin content; this value determines the effective permittivity surrounding the traces, affecting signal speed and impedance.[55] For FR-4, a representative ε_r of approximately 4.5 is common at low frequencies, leading to a signal propagation velocity of about 1.4 × 10^8 m/s, or roughly 47% of the speed of light in vacuum.[56] The loss tangent (tan δ), a measure of dielectric energy dissipation, is around 0.02 at 1 GHz for standard FR-4, increasing with frequency and contributing to signal attenuation, particularly in RF applications where it can degrade insertion loss by several dB per inch.[55] Additionally, capacitance between adjacent traces arises from their proximity and the intervening dielectric, modeled approximately as C ≈ ε_0 ε_r (A / d) for parallel structures, where A is the overlapping area and d is the separation; this inter-trace capacitance can couple unwanted signals if spacing is insufficient, typically requiring minimum clearances of 3–5 times the trace width for high-speed designs to limit it below 1 pF/cm.[57] Key signal integrity challenges in PCBs include crosstalk, reflections, and electromagnetic interference (EMI). Crosstalk occurs when electromagnetic fields from an aggressor trace induce noise in a victim trace, with near-end crosstalk (NEXT) and far-end crosstalk (FEXT) magnitudes depending on coupling length and trace separation; for unshielded microstrips, NEXT can exceed 20 dB degradation over 10 cm at 1 GHz if spacing is less than 3w (where w is trace width).[58] Reflections arise from impedance discontinuities, such as at vias or terminations, causing signal ringing and overshoot; these are exacerbated when trace characteristic impedance deviates from the driver's output or receiver's input, often by 10–20% in mismatched designs.[59] EMI involves unintended radiation or susceptibility, where high-speed edges (e.g., >1 ns rise times) generate broadband emissions that couple to nearby circuits or radiate from the board edges, potentially violating standards like FCC Part 15 with field strengths >40 dBμV/m at 3 meters.[60] To mitigate these issues, controlled impedance traces are essential, maintaining a target Z_0 (typically 50 Ω single-ended or 100 Ω differential) by adjusting trace width, thickness, and dielectric height. For microstrip lines, the characteristic impedance is given by Z_0 = \sqrt{\frac{L}{C}} where L is inductance per unit length and C is capacitance per unit length; in lossless approximations, this simplifies design calculations, though full models incorporate ε_r via empirical formulas like Z_0 ≈ 87 / √ε_r × ln(5.98h / (0.8w + t)) for microstrips, with h as substrate height, w as width, and t as copper thickness.[61][62] Signal attenuation per unit length, α, further degrades integrity and is approximated for low-loss lines as \alpha \approx \frac{R}{2 Z_0} + \frac{G Z_0}{2} where R is series resistance per unit length (dominated by skin effect at high frequencies, R ≈ √(π f μ / σ) / (w + 2δ) for traces) and G is shunt conductance per unit length (G ≈ ω C tan δ); this yields typical values of 0.5–1 dB/inch at 10 GHz for FR-4 microstrips, combining conductor losses (α_c ≈ R / Z_0) and dielectric losses (α_d ≈ (ω C tan δ) / 2).[63][64] In high-speed applications, such as 5G systems operating at GHz frequencies (e.g., 28 GHz mmWave bands), these properties demand specialized techniques like differential pairs and shielding to preserve eye diagrams with >90% opening. Differential pairs route two traces with equal length and spacing (e.g., 100–150 μm gap for 100 Ω impedance), rejecting common-mode noise and reducing crosstalk by 20–30 dB compared to single-ended lines; length matching within 0.1 mm minimizes skew.[65] Shielding via ground planes or guard traces adjacent to pairs further suppresses EMI, confining fields and lowering radiated emissions by up to 15 dB, essential for maintaining bit error rates below 10^{-12} in 5G PCB interconnects.[66] Layer structures, such as embedding signals between ground planes, briefly enhance these properties by stabilizing reference impedance, though primary control remains in trace geometry.[62]Materials and Components
Substrate materials and laminates
The substrate of a printed circuit board (PCB) serves as the insulating base that supports conductive traces and components, primarily composed of reinforcing fibers embedded in a polymer resin matrix to form laminates. The most widely used material is FR-4, a flame-retardant composite consisting of woven E-glass fiberglass cloth impregnated with a bifunctional epoxy resin, such as diglycidyl ether of bisphenol A (DGEBA), cured with dicyandiamide or phenolic hardeners.[67][68] This structure provides mechanical stability and electrical insulation, with the fiberglass weave (typically 1080 or 2116 style) offering tensile strength while the resin fills voids for uniformity.[68] Key performance parameters of FR-4 laminates include the glass transition temperature (Tg), which marks the shift from glassy to rubbery state and is typically 130–140°C for standard grades, ensuring dimensional stability during soldering processes up to 260°C.[69][68] The coefficient of thermal expansion (CTE) is anisotropic: in-plane (x-y directions) values range from 12–18 ppm/°C below Tg, matching closely with copper to minimize stress in multilayer boards, while z-axis CTE is higher at 40–70 ppm/°C, influencing via reliability.[70][71][68] FR-4 laminates are fabricated through a process involving the creation of B-stage prepregs—fiberglass sheets partially impregnated with uncured epoxy resin—followed by stacking with copper foil and hot-pressing at 170–190°C and 1–5 MPa to cure the resin and bond layers into a rigid sheet.[72] This method, standardized under IPC-4101, ensures consistent thickness (e.g., 0.8–1.6 mm) and UL 94 V-0 flammability.[68] For cost-sensitive applications like consumer electronics, CEM-1 serves as a lower-cost alternative, comprising a core of cellulose paper impregnated with phenolic or epoxy resin, surfaced with woven glass fabric and epoxy for improved punchability and strength at approximately 70% of FR-4's price.[73] Its Tg is lower at 110–130°C, and it is suited for single- or double-sided boards where high thermal demands are absent.[68] In high-temperature environments, such as aerospace or automotive systems, polyimide resins reinforced with glass fabric offer superior performance, with Tg values of 250–300°C and operational stability up to 260°C continuously.[68][74] These materials, like DuPont's Pyralux series, exhibit lower z-axis CTE (20–50 ppm/°C) for better reliability under thermal cycling.[68] For high-frequency applications as of 2025, specialized laminates such as hydrocarbon ceramics (e.g., Rogers RO4000 series) with low dielectric constants (3.0–3.5) and stable CTE are used to minimize signal loss in 5G and 6G systems.[75] Emerging sustainability efforts in the 2020s have introduced bio-based epoxy resins derived from renewable sources like epoxidized soybean oil, cured with bio-hardener systems such as tannic acid, to reduce reliance on petroleum-derived epoxies while maintaining Tg above 100°C and comparable mechanical properties.[76] These green laminates aim to lower the environmental footprint of PCB production without compromising dielectric insulation, which influences signal integrity in high-speed designs.[76]Conductor traces and thicknesses
Conductor traces in printed circuit boards (PCBs) are primarily formed from copper foil, which serves as the conductive pathways connecting components. The copper foil is laminated onto the substrate material during the PCB fabrication process. This foil is typically specified by its weight in ounces per square foot (oz/ft²), where 1 oz/ft² corresponds to a nominal thickness of 35 μm (1.4 mils). Common thicknesses range from 0.5 oz/ft² (18 μm) to 2 oz/ft² (70 μm), with 1 oz/ft² being the standard for most applications due to its balance of conductivity and manufacturability.[77] Two primary types of copper foil are used: electrodeposited (ED) copper and rolled annealed (RA) copper. ED copper is produced by electrodeposition, resulting in a rougher surface profile and a columnar grain structure that provides good adhesion to substrates but limited flexibility, making it suitable for rigid PCBs. In contrast, RA copper is created through repeated rolling and annealing processes, yielding a smoother surface and a more uniform, elongated grain structure that enhances ductility and bendability, ideal for flexible and rigid-flex boards.[78][79] Traces are formed from the copper foil through a photolithographic etching process, where unwanted copper is removed to define the circuit pattern. Etching tolerances typically range from ±10% to ±15% of the nominal trace width, influenced by factors such as copper thickness and etch factor, requiring design compensation to achieve final dimensions. The minimum trace width per IPC-6012 standards for Class 2 PCBs (dedicated service electronics) is 0.1 mm (4 mils), ensuring reliable performance in general commercial applications.[80][81] To protect exposed copper traces from oxidation and improve solderability, various surface finishes are applied. Hot air solder leveling (HASL) involves dipping the board in molten solder and removing excess with hot air, providing a cost-effective tin-lead or lead-free coating with excellent solder joint reliability but potential for uneven thickness. Electroless nickel immersion gold (ENIG) deposits a thin nickel layer followed by a gold flash, offering a flat, uniform surface with superior corrosion resistance and long shelf life, though it is more expensive.[82] While copper dominates due to its high conductivity and cost-effectiveness, alternatives exist for specific needs. Aluminum conductors are used in cost-sensitive, high-power applications like LED lighting and power supplies, where aluminum-core PCBs provide thermal dissipation benefits at lower material costs compared to copper-clad boards, though aluminum traces require specialized etching to avoid issues like pitting. Emerging technologies include silver nanoparticle inks for inkjet printing of traces, enabling additive manufacturing on flexible substrates with conductivities approaching bulk silver after low-temperature sintering, suitable for rapid prototyping and wearable electronics.[83][84] In 2025 developments for flexible PCBs, thin-film copper layers below 10 μm—such as 9-12 μm thicknesses—have gained traction for ultra-thin applications, enhancing bend radius and reducing weight while maintaining sufficient conductivity for low-power signals.[85]| Copper Foil Weight | Nominal Thickness (μm) | Typical Use |
|---|---|---|
| 0.5 oz/ft² | 18 | High-density, fine-pitch traces |
| 1 oz/ft² | 35 | Standard multilayer boards |
| 2 oz/ft² | 70 | High-current power traces |