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Memory coherence

Memory coherence is a fundamental property in shared-memory multiprocessor systems, ensuring that all processors maintain a consistent view of memory data by guaranteeing that a read operation returns the value of the most recent write to that location, as determined by a hypothetical serial order of operations across all processors.^[1] This coherence is typically achieved through cache coherence protocols, which manage multiple copies of data in private caches to enforce invariants such as the Single-Writer-Multiple-Reader (SWMR) rule—where only one cache can modify a data block at a time—and the Data-Value Invariant, ensuring all readers see the same value after a write.^[1] While closely related, memory coherence differs from memory consistency models, which define the global ordering of operations across different memory locations (e.g., Sequential Consistency preserves program order for all loads and stores, whereas Total Store Order relaxes store-to-load reordering for performance); coherence focuses on per-location value correctness and serves as a prerequisite for consistency.^[2]^[1] In practice, cache coherence protocols are categorized into snooping-based and directory-based approaches. Snooping protocols, suitable for bus-connected systems with a small number of processors, rely on each cache monitoring (or "snooping") bus transactions to maintain coherence states; common variants include MSI (Modified, Shared, Invalid), which handles basic write-invalidation, and its optimizations like MESI (adding Exclusive to reduce traffic) and MOESI (adding Owned for better write-back efficiency).^[1] Directory-based protocols scale to larger systems by using a centralized or distributed directory to track cache locations of data blocks and route coherence messages unicast rather than broadcast, as seen in systems like the SGI Origin 2000, which supported up to 1024 processors.^[1] Emerging paradigms, such as temporal coherence with leases or self-invalidation, further optimize for relaxed consistency models in GPUs and high-performance computing, where hardware like NVIDIA's Volta architecture integrates coherence for GPGPU workloads.^[1] The concept traces back to early shared-memory multiprocessors in the 1970s and 1980s, with foundational work on Sequential Consistency by Leslie Lamport in 1979 establishing the need for ordered operations, and subsequent innovations like weak ordering (1986) and release consistency (1990) balancing correctness with performance gains from relaxed models like x86's Total Store Order.^[1] Today, memory coherence remains essential for scalable parallelism in multicore processors, preventing issues like stale data or race conditions, though challenges in verification—addressed by formal tools like Murphi and TLA+—persist as core counts grow.^[1]

Fundamentals

Definition and Core Principles

Memory coherence is a fundamental property in shared-memory multiprocessor systems that ensures all processors maintain a consistent and unique view of the shared memory contents, such that any write operation to a memory location becomes visible to all subsequent reads across processors in a well-defined order.^[1]^[3] This property makes caches functionally transparent, propagating writes from one processor's cache to others to avoid discrepancies in data values observed by different processors.^[1] The core principles underpinning memory coherence include the single-writer-multiple-reader (SWMR) invariant, which ensures that only one cache can modify a data block at a time while multiple can read it, and the Data-Value Invariant, which guarantees that all reads return the value from the most recent write in a total serialization order of operations.^[1] A related visibility rule ensures that a write to a memory location is eventually visible to all processors, upholding the SWMR invariant where reads return the most recent write value in a serialized order.^[1]^[3] In multi-level cache hierarchies, the inclusion property—where higher-level caches contain a superset of the blocks in lower-level caches—can simplify coherence management by ensuring actions at lower levels propagate upward, though not all systems enforce strict inclusion.^[4] For instance, in a two-processor system, if processor A writes a value to memory location X, processor B's subsequent read must observe that updated value before B can perform its own write to X, ensuring serialized writes and consistent visibility across the system.^[1] Memory coherence emerged in the early 1980s amid the development of shared-memory multiprocessors, notably through projects like the IBM RP3 initiated in 1983, which addressed coherence challenges in scalable parallel architectures using software-assisted hardware mechanisms.^[5]^[6]

Role in Multiprocessor Architectures

In multiprocessor systems, memory coherence is essential to prevent inconsistencies that arise when multiple processors maintain private caches of shared memory locations. Without coherence mechanisms, a processor might operate on stale data from its local cache, leading to errors in parallel program execution where one processor's write must be visible to others accessing the same data. Coherence protocols enforce invariants such as single-writer-multiple-reader (SWMR), ensuring that all processors perceive a consistent view of memory despite local caching.^[1] Memory coherence integrates seamlessly into symmetric multiprocessor (SMP) architectures, which provide uniform memory access (UMA) through a shared interconnect like a bus, allowing all processors to access any memory location with equal latency. In SMP systems, coherence typically relies on snooping protocols where caches monitor shared traffic to maintain consistency across local caches. In contrast, non-uniform memory access (NUMA) architectures distribute memory across nodes, introducing varying access latencies, and extend coherence to span both local and remote caches using mechanisms like directories to track shared data locations efficiently. This integration preserves the abstraction of a single shared memory space while accommodating hardware scalability.^[1] The primary benefit of memory coherence in these architectures is enabling efficient parallel computing by permitting private caches to reduce latency and bandwidth demands on the shared interconnect, all while upholding global data consistency. For instance, in early bus-based systems like the Sequent Symmetry introduced in 1987, coherence protocols minimized bus traffic by allowing write-back caching and invalidation-based updates, supporting a moderate number of processors with improved throughput for multiuser workloads compared to uncached designs. This approach not only avoids the pitfalls of inconsistent views but also scales parallel program performance without requiring programmers to manage data placement explicitly.^[1]^[7]

Coherence Models

While memory coherence ensures that all processors see a consistent value for each memory location, the models discussed in this section are memory consistency models that define the ordering of operations across different locations and rely on underlying coherence protocols for per-location correctness.

Sequential Consistency Model

Sequential consistency, proposed by Leslie Lamport in 1979, is a memory consistency model that ensures all memory operations appear to execute instantaneously in some global total order consistent with the program order on each processor.^[8] This model provides a straightforward semantic guarantee for multiprocessor systems, making it intuitive for programmers by mimicking the behavior of a uniprocessor executing operations sequentially.^[9] The rules of sequential consistency dictate that every read must return the value of the most recent write according to the global order, and no operations from different processors are reordered relative to one another.^[9] Formally, as defined by Lamport, a multiprocessor is sequentially consistent if the result of any execution is the same as if the operations of all processors were executed in some sequential order, with the operations of each individual processor appearing in that order as specified by its program.^[8] For instance, consider operations where a write W1 on processor A precedes a read R1 on A, and another read R2 on processor B follows W1 in program order; sequential consistency requires R2 to return the value written by W1.^[8] This model offers a strong guarantee against unexpected reorderings, enabling correct execution of shared-memory programs without subtle race conditions.^[9] For example, in a program where two threads each increment a shared counter once, sequential consistency ensures the final value is 2, as the writes and reads interleave in a total order that respects each thread's sequence.^[9] However, achieving sequential consistency imposes significant hardware overhead, as it restricts common optimizations like operation reordering and buffering, often requiring strict serialization that limits parallelism and increases latency.^[9]

Relaxed Consistency Models

Relaxed consistency models relax the ordering constraints imposed by sequential consistency to enable greater concurrency and performance in multiprocessor systems, allowing hardware to reorder, buffer, or pipeline memory operations while preserving enough guarantees for correct program execution. These models recognize that most programs rely on explicit synchronization for data sharing, permitting optimizations that would violate the total global order of sequential consistency but align with typical usage patterns. By categorizing memory accesses based on their synchronization context, relaxed models reduce unnecessary coherence traffic and improve scalability, particularly in systems with write buffers or non-blocking caches.^[10] Key variants include processor consistency, weak ordering, and release consistency, each offering progressive relaxations tailored to different implementation trade-offs. In contrast to sequential consistency, which serves as the strict baseline requiring all operations to appear atomic and in a single global order, these models shift the burden to software synchronization to enforce critical orderings.^[11] Processor consistency extends sequential consistency by guaranteeing that each processor observes its own memory operations in program order, but allows writes from different processors to become visible to other processors in varying orders, without a global total order across all writes. This non-atomic visibility of remote writes enables effective use of write buffers without strict serialization, reducing latency while maintaining per-processor orderliness for reads and writes. The model ensures cache coherence but relaxes inter-processor write serialization, making it suitable for systems where synchronization primitives handle cross-processor dependencies. Introduced by Dubois, Scheurich, and Briggs, processor consistency provides a modest relaxation that supports efficient caching while avoiding anomalies in unsynchronized code.^[12] Weak ordering further relaxes constraints by partitioning memory operations into synchronized and non-synchronized categories, permitting arbitrary reordering, buffering, or overlapping within non-synchronized accesses but enforcing strict ordering around synchronization operations like locks or barriers. Non-synchronized accesses, which include most ordinary loads and stores not tied to synchronization, can be freely reordered relative to each other and even to some synchronized accesses, as long as synchronization points establish a total order for critical sections. This approach, formalized by Adve and Hill, allows hardware to aggressively optimize common-case operations while relying on programmer-inserted synchronization to delimit regions where ordering matters, thereby enhancing pipelining and reducing stalls in large multiprocessors.^[11] Release consistency builds on weak ordering by explicitly distinguishing acquire (e.g., lock acquisition) and release (e.g., lock release) synchronization points, treating ordinary memory accesses as potentially unordered except when bound to these events. Under this model, writes need only become visible to subsequent acquires on the same synchronization variable, enabling lazy update propagation and decoupling data coherence from strict operation ordering. A key optimization, lazy release consistency (LRC), defers the delivery of released updates until an acquire explicitly requests them, minimizing unnecessary invalidations and communication in distributed settings by using diff-based tracking of changes since the last synchronization. Formulated by Gharachorloo, Gupta, and Hennessy, release consistency, including its lazy variant, supports high-performance implementations by aligning coherence with program synchronization semantics rather than assuming all accesses are critical.^[10] These relaxed models offer significant trade-offs: they enhance scalability by reducing global synchronization overhead—significantly reducing coherence traffic in benchmark workloads—and allow better resource utilization in pipelined architectures, but demand that programmers explicitly manage ordering through fences, barriers, or atomic instructions to avoid subtle bugs from unexpected reorderings.^[10]^[11]

Cache Coherence Protocols

Snoopy-Based Protocols

Snoopy-based protocols maintain cache coherence in shared-bus multiprocessor systems by having each cache controller monitor all bus transactions initiated by other processors, a process known as snooping.^[13] This allows caches to invalidate or update their local copies of shared data blocks as needed to ensure consistency without centralized coordination.^[1] The protocols rely on a broadcast medium like a bus, where every transaction is visible to all caches, enabling simple hardware implementation through finite-state machines that track the state of individual cache lines.^[14] The foundational MSI protocol employs a three-state model for each cache line: Modified (M), indicating the line has been locally updated and is the sole valid copy; Shared (S), meaning the line is clean and potentially present in multiple caches; and Invalid (I), denoting the line is unusable and must be fetched from memory or another cache.^[14] In operation, a processor's read miss triggers a bus read request; if another cache holds the line in M state, it supplies the data and transitions to S, while the requesting cache enters S.^[1] A write miss, however, requires the cache to issue a bus invalidate (or upgrade) request, forcing all other copies to I state before the write proceeds, transitioning the local line to M.^[14] This invalidate-based approach enforces a single writer among multiple possible readers, aligning with coherence models like sequential consistency by ensuring writes are propagated appropriately.^[1] Extensions to MSI address inefficiencies in state transitions and bus traffic. The MESI protocol introduces an Exclusive (E) state, a clean version of M where the line is the unique copy, allowing the cache to silently discard it on eviction without bus notification.^[14] The MOESI protocol further adds an Owned (O) state, where the cache holds a potentially modified line but permits other caches to read it without immediate write-back to memory, optimizing data sharing in systems like those from IBM.^[15] These protocols excel in simplicity and low overhead for small-scale systems with up to 8-16 processors, as the broadcast nature avoids complex directory structures while leveraging the bus for atomic operations.^[14] They were employed in early multiprocessor implementations, such as Intel's Pentium series for intra-chip coherence and Sun's systems for bus-based shared memory.^[1] However, as processor counts grow, bus contention from frequent broadcasts degrades performance, restricting scalability beyond modest configurations.^[14]

Directory-Based Protocols

Directory-based protocols maintain cache coherence in multiprocessor systems by using a directory structure to track the state of each memory block across caches, avoiding the broadcast overhead inherent in snoopy protocols for small-scale systems.^[16] The directory, which can be centralized or distributed, records information such as whether a block is uncached, exclusively cached by one processor, or shared among multiple processors, along with the identities of the caching processors.^[17] When a processor requests a memory block, it sends a point-to-point message to the directory home node; the directory then responds by granting permission, invalidating copies in other caches if necessary, or supplying data from a sharer, ensuring coherence through targeted interventions rather than system-wide broadcasts.^[18] A full-map directory employs a bit vector for each memory block, where each bit corresponds to a specific processor or cache, indicating whether that cache holds a copy of the block.^[16] This approach precisely tracks all sharers, supporting scalability to hundreds of processors by allowing efficient point-to-point invalidations or supplies on write or read misses.^[16] However, the storage overhead is significant, requiring approximately one bit per processor per memory block, which can consume substantial memory in large systems.^[16] To mitigate the memory demands of full-map directories, coarse directories use compressed representations such as limited pointers or bit-vector summaries that group multiple processors.^[19] In a limited-pointer scheme, the directory allocates a fixed number of pointers (e.g., 2–4) to explicitly list sharers; if more sharers exist, it may overflow to a coarse indicator like "all caches" or a hierarchical summary, introducing minor imprecision but reducing storage to logarithmic in the number of processors per block.^[16] Hierarchical directories further enhance this for non-uniform memory access (NUMA) systems by organizing directories in a tree structure, where local nodes handle intra-cluster sharing and higher levels manage inter-cluster coherence, balancing storage and access latency.^[20] Early implementations of directory-based protocols include the DASH (Directory-based Architecture for Shared memory) multiprocessor developed at Stanford University around 1990, which used a distributed directory across processing nodes to enforce a directory-based invalidation protocol supporting up to 64 processors.^[21] In DASH, each node maintains a portion of the directory for its local memory, and coherence actions propagate via point-to-point messages over a scalable interconnect, demonstrating effective handling of shared-memory workloads without bus contention.^[17] A modern example is the SGI Origin 2000 server from the late 1990s, which employed a directory-based protocol in a ccNUMA architecture scalable to 1,024 processors, combining full-bit-vector directories for small sharer sets with coarse-vector approximations for efficiency.^[20] These protocols excel in large-scale systems by eliminating broadcast traffic, which grows quadratically with processor count in snoopy schemes, and by exploiting sparse sharing patterns common in parallel applications where most blocks are cached by few processors.^[16] This results in lower network contention and better scalability, with studies showing directory protocols maintaining performance up to 128 processors where snoopy systems saturate.^[17] Additionally, they support efficient handling of infrequent sharing through precise tracking in full-map variants or approximations in coarse ones, minimizing unnecessary messages.^[19]

Implementation and Challenges

Hardware Support Mechanisms

Hardware support for memory coherence relies on specialized cache states and transition mechanisms to track and update data copies across processors. The MESI protocol exemplifies this through four primary cache block states: Modified (M), where the block is dirty and exclusively owned by one cache, allowing read and write access while the memory copy is stale; Exclusive (E), a clean exclusive state where the block matches memory and permits read or write access by a single cache; Shared (S), a read-only state where multiple caches hold identical clean copies matching memory; and Invalid (I), indicating no valid data in the cache block.^[1] These states enable caches to respond appropriately to coherence events, ensuring the single-writer-multiple-reader invariant. In snoopy-based protocols, transitions occur via bus signals: from I to E or S on a processor read (PrRd) if no other sharers exist or multiple copies are allowed; from E to M on a local write hit without bus activity; from S to I on a bus read-exclusive (BusRdX) signal from another processor, invalidating shared copies; from M to S on a BusRd, supplying data while flushing to memory; and from M to I on BusRdX, triggering a write-back.^[1] Directory-based systems use point-to-point messages for transitions: from I to S on a read-shared request (GetS), adding the requester to a sharers list; from I to E on a read-exclusive (GetM) if no sharers; from S to I via directory-issued invalidations (Inv) on a write request; and from E or M to S by forwarding data and updating the directory.^[1] Interconnect support distinguishes write-back from write-through policies in bus-based snoopy systems. Write-back caches delay memory updates until eviction or coherence events, reducing bus traffic but requiring ownership tracking to supply data to other caches during transitions like M to S.^[22] Write-through policies immediately propagate writes to memory, simplifying invalidation in snoopy protocols but increasing bus contention, as seen in write-through-with-invalidate schemes where all caches snoop and invalidate on writes.^[22] In directory systems, interconnects handle request types such as read-shared for non-exclusive reads, read-exclusive for acquiring ownership, and invalidate messages to revoke permissions from sharers.^[1] Coherence operates at the granularity of cache blocks, typically 64 bytes, to balance transfer overhead and locality. Larger blocks exploit spatial locality but amplify false sharing, where unrelated data in the same block triggers unnecessary invalidations across processors, elevating miss rates without the sharp improvements seen in uniprocessors.^[23] Granularity effects manifest as processors contending for blocks containing independent variables, leading to coherence traffic disproportionate to true sharing.^[23] Hardware mitigates coherence misses—accesses requiring intervention due to invalid or outdated states—and protocol races through transient states and escalation mechanisms. Coherence misses are classified during cache lookups, distinguishing them from capacity or compulsory misses to enable targeted handling, such as reissuing requests if a transient state (e.g., pending ownership) blocks access.^[24] Protocol races, arising from concurrent requests on unordered interconnects, are resolved using token-based counting where blocks require specific tokens for reads (at least one) or writes (all tokens), with transient requests reissued on failure and persistent requests activated after timeouts to forward tokens and override races without global serialization.^[25] In ARM systems, the CoreLink CMN-600 coherent mesh network provides hardware coherence via the Coherent Hub Interface (CHI) protocol, supporting snoop filters and scalable mesh topology to track states and route requests across clusters of multi-core CPUs, enabling efficient sharing in large-scale Armv8-A configurations such as data center servers.^[26]

Scalability and Performance Issues

Snoopy-based cache coherence protocols face significant scalability challenges due to their reliance on broadcast mechanisms over shared interconnects, leading to bottlenecks as the number of processors increases. The broadcast traffic required for coherence actions, such as invalidations and interventions, grows linearly with the number of processors, overwhelming bus bandwidth and increasing latency. These protocols typically scale effectively only up to around 64 processors, beyond which the interconnect becomes a major performance limiter.^[1]^[27] In contrast, directory-based protocols address broadcast issues by using point-to-point communication but introduce storage overhead that scales as O(N) with N processors. A full bit-vector directory requires one bit per processor per cache line to track sharers, resulting in memory overhead proportional to the product of processors and memory size; for example, with 256 processors, this can exceed 50% of total memory. Limited-pointer directories mitigate this by tracking only a fixed number of sharers, but they risk overflow and additional traffic for unresolved cases.^[28] Coherence mechanisms impose substantial performance overhead in shared workloads, where traffic from invalidations and interventions can consume over 50% of available bandwidth, particularly in decision support systems. This overhead arises from frequent coherence misses, which force additional interconnect traversals and delay data access. Such misses elevate the average memory access time (AMAT) in multiprocessors compared to uniprocessors, as AMAT incorporates coherence-induced penalties alongside hit time, miss rate, and miss penalty.^[29]^[2] To alleviate these issues, techniques like victim caches and prediction-based prefetching have been proposed, though they offer partial relief rather than comprehensive solutions. A victim cache, a small fully associative buffer holding evicted lines from a direct-mapped cache, reduces conflict misses that exacerbate coherence traffic by up to 95% in some configurations. Prediction-based prefetching anticipates shared data accesses to preempt coherence requests, lowering overhead in chip multiprocessors by synchronizing prefetches with coherence events; for instance, synchronization-aware schemes can cut invalidation traffic while minimizing useless prefetches.^[30] A notable case study from the 1990s involves supercomputers like the Cray T3D, where potential coherence overhead in large-scale systems prompted a shift to non-cache-coherent NUMA designs. The T3D's architecture provided shared memory access without hardware coherence, relying on software management to avoid broadcast and directory costs, enabling scalability to thousands of processors at the expense of programmer effort for consistency. This approach optimized performance for NUMA latencies in high-performance computing workloads.^[31]^[32] Emerging challenges in 2025 arise from disaggregated memory architectures in data centers, where compute and memory resources are pooled separately using interconnects like Compute Express Link (CXL). Traditional cache coherence protocols struggle to scale across remote memory nodes, leading to high latency and complexity in maintaining consistency; recent research proposes selective coherence mechanisms or hybrid hardware-software solutions to address the "coherence conundrum" in these systems.^[33] In modern evaluations, tools like the gem5 simulator facilitate detailed traffic analysis for coherence scalability, modeling metrics such as bandwidth utilization, latency under varying processor counts, and coherence message distributions in multicore systems. These simulations reveal that coherence traffic can dominate network usage in shared-data benchmarks, guiding optimizations like snoop filters to reduce unnecessary broadcasts by up to 50%.

Applications and Extensions

Coherence in Distributed Systems

Distributed shared memory (DSM) systems extend the abstraction of a unified address space across networked nodes, emulating memory coherence in environments where physical memory is distributed, such as clusters of workstations or wide-area networks. Unlike tightly coupled multiprocessors with hardware cache coherence, DSM relies on software or hybrid hardware-software mechanisms to manage coherence over higher-latency interconnects. Early examples include the IVY system, developed in 1988, which implemented page-based DSM on a token-ring network of Apollo workstations using techniques like page migration—transferring entire pages to the accessing node—and replication to maintain consistency while minimizing communication overhead.^[34] These approaches allow programmers to use familiar shared-memory models without explicit message passing, though they introduce challenges in balancing coherence with performance. Key protocols in DSM emphasize relaxed consistency models to reduce communication costs, building on concepts like release consistency. The Munin system, introduced in 1990, employed lazy release consistency, where updates from multiple writers are propagated only at synchronization points, such as releases, using multiple protocols tailored to data types (e.g., write-once for barriers, write-all for locks) to optimize for different access patterns.^[35] Similarly, TreadMarks, developed in 1994, utilized diff-based updates in a page-fault-driven manner, computing and exchanging only the differences between page versions rather than full pages, which significantly reduced transfer volumes in update-heavy workloads on standard workstations connected via ATM LANs.^[36] These protocols leverage software coherence managers to track page states and handle invalidations or updates, often integrating with virtual memory systems for fault handling. DSM implementations face significant challenges, including hiding the high latency of network communication and managing coherence in the presence of failures like network partitions. Latency hiding is achieved through prefetching, overlapping computation with communication via software-managed queues, and optimistic protocols that delay coherence actions until necessary, as explored in systems that use compiler support or runtime optimizations to mask remote access delays.^[37] Network partitions require mechanisms such as quorum-based replication or version vectors to detect and resolve inconsistencies upon reconnection, ensuring eventual coherence without violating programmer expectations. Hybrid approaches mitigate these issues by combining DSM with explicit message passing; for instance, in Beowulf clusters—commodity Linux-based systems—programmers use shared memory within SMP nodes and MPI for inter-node communication, allowing fine-grained control over data movement while retaining DSM for intra-node locality.^[38] The evolution of DSM has progressed from research prototypes to large-scale production systems, adapting coherence to global distributions. Modern examples include Google's Spanner, deployed in 2012, which provides linearizable consistency—a strict form of external consistency—across datacenters using synchronized clocks (TrueTime API) and two-phase commit protocols over Paxos replication, enabling globally consistent reads and writes despite planetary-scale latencies.^[39] Recent advancements (2023–2025) leverage technologies like Compute Express Link (CXL) for memory disaggregation and RDMA for low-latency shared memory in AI and cloud workloads, including systems like Shray for distributed array storage and RMAI for remote shared memory in inference tasks.^[40]^[41]^[42] This represents a shift toward fault-tolerant, geo-replicated DSM integrated with database semantics and hardware acceleration, influencing cloud computing paradigms while inheriting relaxed models for scalability.

Modern Extensions in Multicore Processors

Modern multicore processors, as of 2025, have evolved to incorporate chiplet-based architectures and heterogeneous computing elements, necessitating extensions to traditional cache coherence protocols for improved scalability and performance. These extensions often build on directory-based mechanisms to handle larger core counts and diverse workloads, while integrating accelerators like GPUs and FPGAs into the coherence domain. For instance, AMD's 5th Gen EPYC (Turin) processors, released in 2024, employ a chiplet design where multiple dies are interconnected via Infinity Fabric—an enhanced coherent protocol that implements directory-based coherence across chiplets, enabling efficient NUMA handling in multi-socket systems with up to 128 cores per socket.^[43]^[44] This approach reduces latency for inter-die communication compared to earlier monolithic designs, supporting scalable coherence traffic. Intel's Xeon 6 (Granite Rapids) processors, launched in 2024, utilize a mesh interconnect topology for on-chip communication, combining directory-based coherence with snoopy-like optimizations to maintain consistency in up to 128 cores per socket.^[45]^[46] This extension enhances bandwidth allocation and reduces contention in NUMA configurations, where remote memory accesses are minimized through intelligent data placement. In ARM-based systems, the AMBA Coherent Hub Interface (CHI) protocol serves as a key extension, providing a scalable, link-layer interface for cache coherence in multicore SoCs, as seen in designs like NVIDIA's Grace CPU (2023), with recent integrations via NVLink Fusion for full coherency as of November 2025.^[47] CHI supports efficient snoop filtering and directory sharing across heterogeneous cores, enabling low-latency coherence in big.LITTLE configurations and integrated GPU setups.^[48]^[49] To address the demands of heterogeneous multicore environments, standards like Compute Express Link (CXL) extend coherence beyond the CPU socket to accelerators and memory devices. CXL leverages the PCIe physical layer with protocols such as CXL.cache and CXL.mem to enable asymmetric MESI coherence, allowing devices to participate in the host's cache domain for fine-grained sharing. This results in latencies comparable to remote socket access (around 57 ns) and bandwidth scaling up to 256 GB/s, benefiting AI and disaggregated systems by pooling memory resources without software-managed consistency.^[50]^[51] Additionally, fine-grain coherence specialization, as proposed in frameworks like Spandex (2022), tailors protocol actions per access—such as update forwarding or owner prediction—to optimize for low-locality workloads in CPU-GPU setups, reducing execution time by up to 61% and network traffic by 99% in benchmarks. These extensions prioritize hardware simplicity while enhancing reuse in diverse accelerator ecosystems.^[52]

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[PDF] Speeding-up Multiprocessors Running DSS Workloads through ...
such workload; ii) the kernel effects account for 50% of the coherence overhead. Previous studies that considered DSS workloads were mostly limited to 4 ...
[30]
Improving direct-mapped cache performance by the addition of a ...
Victim caching is an improvement to miss caching that loads the small fully-associative cache with the victim of a miss and not the requested line. Small victim ...
[31]
An Advanced Compiler Framework for Non-Cache-Coherent ...
The Cray T3D and T3E are non-cache-coherent (NCC) computers with a NUMA structure. They have been shown to exhibit a very stable and scalable performance ...
[32]
[PDF] Efficient Shared Memory with Minimal Hardware Support
To support this claim we have developed the. Cashmere family of software coherence protocols for NCC-NUMA (Non-Cache-Coherent, Non-Uniform-Memory ... Cray ...
[33]
[PDF] Richard Schaefer - cs.Princeton
Apr 10, 1989 · IVY: A Shared Virtual Memory System for Parallel Computing. In Proceedings of the 1988 International Conference on Parallel Processing, pages 94 ...
[34]
distributed shared memory based on type-specific memory coherence
This paper focuses on the design and use of Munin's memory coherence mechanisms, and compares our approach to previous work in this area. Formats available.
[35]
[PDF] TreadMarks: Distributed Shared Memory on Standard
This paper presents a performance evaluation of TreadMarks running on. Ultrix using DECstation-5000/240's that are connected by a 100-Mbps switch-based ATM LAN.
[36]
(PDF) Hiding Communication Latency and Coherence Overhead in ...
PDF | On Jan 1, 1996, Ricardo Bianchini and others published Hiding Communication Latency and Coherence Overhead in Software DSMs. | Find, read and cite all ...
[37]
[PDF] Using a PC Cluster for High-Performance Computing and Applications
One way to program SMP clusters is to use an all-message-passing model. This approach uses message passing even for intra-node communication. It simplifies ...
[38]
[PDF] Spanner: Google's Globally-Distributed Database
This paper describes how Spanner is structured, its feature set, the rationale underlying various design decisions, and a novel time API that exposes clock ...
[39]
Memory Performance of AMD EPYC Rome and Intel Cascade Lake ...
Apr 9, 2022 · This paper describes and experimentally evaluates the memory hierarchy of AMD EPYC Rome and Intel Xeon Cascade Lake SP server processors in ...
[40]
Memory Performance of AMD EPYC Rome and Intel Cascade Lake ...
This paper evaluates memory hierarchy of AMD EPYC Rome and Intel Cascade Lake SP, finding different performance patterns due to distinct microarchitectures.<|control11|><|separator|>
[41]
Benchmarking CPU-Requested GPU Memory Access
Apr 19, 2025 · Each core has a private 64 KB L1 and 1 MB L2 Cache [31]. The total L3 cache size is 114 MB [16]. NVIDIA Scalable Coherency Fabric is the CPU's ...3 Characterizing Gpu Memory... · 3.2 Throughput · 3.4 Latency<|separator|>
[42]
Data Prefetching on Processors with Heterogeneous Memory
Dec 11, 2024 · Our technique enables a prefetcher to dynamically determine the optimal prefetch degree and distance based on memory type.Missing: coherence | Show results with:coherence
[43]
An Introduction to the Compute Express Link (CXL) Interconnect
” The host processor orchestrates cache coherency, as described below. ... CXL is compatible with a range of coherence implementations inside the CPU.Missing: multicore | Show results with:multicore
[44]
https://exertisenterprise.com/wp-content/uploads/2024/11/5th-gen-amd-epyc-processor-architecture-white-paper.pdf
[45]
A Case for Fine-grain Coherence Specialization in Heterogeneous ...
There have been many coherence extensions proposed over the years (discussed further in Section 2), but these generally build upon conventional hardware ...