Programmable logic array
A programmable logic array (PLA) is a type of programmable logic device (PLD) designed to implement combinational logic functions through a reconfigurable architecture consisting of a programmable AND plane and a programmable OR plane, enabling the realization of sum-of-products (SOP) Boolean expressions.[1][2] Introduced around 1970 as one of the earliest forms of programmable logic integrated into very-large-scale integration (VLSI) circuits, PLAs provided a flexible alternative to fixed random logic by allowing post-manufacture customization of digital circuits.[2] The architecture typically features an input section with true and complementary signals feeding into the AND plane, where programmable interconnects generate product terms, which then connect via the OR plane to form output sums; this NOR-NOR or AND-OR structure supports efficient implementation of multiple logic functions sharing common terms.[1][2] Early PLAs were often mask-programmable, but field-programmable variants emerged in 1975 with devices like the Signetics 82S100, using fuse or PROM-based programming for user reconfiguration without custom fabrication.[3] PLAs found applications in control units, address decoders, and arithmetic logic units within digital systems, offering a regular structure that simplified design automation and testing compared to bespoke gate arrays.[1] Over time, their scalability limitations led to evolution into more advanced PLDs, such as programmable array logic (PAL) devices in 1978 with fixed OR arrays for faster performance, and eventually complex PLDs (CPLDs) and field-programmable gate arrays (FPGAs) by the 1980s and 1990s, which incorporated routing resources and sequential elements for broader use in prototyping and embedded systems.[2][4] Despite this, PLAs remain foundational in understanding programmable logic and are still relevant in specialized low-density or educational contexts.[1]Fundamentals
Definition and Purpose
A programmable logic array (PLA) is a simple programmable logic device (SPLD) used to implement combinational logic circuits in sum-of-products (SOP) form. It features a programmable AND array that generates product terms from inputs (or their complements), followed by a programmable OR array that sums selected product terms to produce outputs, enabling the realization of any Boolean function through configurable interconnections.[5][6] The purpose of a PLA in digital design is to facilitate the creation of custom logic without requiring a fully custom ASIC, which involves high development costs and long fabrication times. This makes PLAs ideal for prototyping, where rapid iteration is needed, and for low-volume production runs—typically up to several thousand units—offering low startup costs, quick turnaround, and easy design modifications compared to fixed-function alternatives.[7][6] PLAs exhibit a fixed two-level architecture with programmable connections in the AND and OR planes, often using fuses or antifuses for configuration, supporting multiple inputs and outputs while focusing exclusively on combinational logic without built-in sequential elements like flip-flops. This structure provides predictable propagation delays, small circuit area, and high pin-to-pin speeds, prioritizing efficiency for SOP-based functions over more versatile but complex devices.[5][7] A basic use case for a PLA is implementing address decoding logic to generate chip selects from microprocessor address lines or the next-state combinational logic in a state machine controller. The concept was first commercialized with Texas Instruments' TMS2000 in 1970, a mask-programmable device that coined the term PLA for such reconfigurable logic.[8]Comparison to Other Programmable Logic Devices
Programmable Read-Only Memories (PROMs) feature a fixed AND plane that generates all possible minterms from the inputs, coupled with a programmable OR plane for selecting desired outputs, making them suitable for simple address decoding or lookup table implementations but inefficient for sparse logic functions due to the exhaustive minterm generation.[9] In contrast, Programmable Logic Arrays (PLAs) employ both programmable AND and OR planes, allowing selective product term generation without full minterm decoding, which provides greater flexibility for implementing complex combinational logic while reducing unnecessary wiring and improving efficiency for non-dense functions.[10] Programmable Array Logic (PAL) devices, a variant of PLAs, incorporate a programmable AND plane but a fixed OR plane, restricting each OR gate to connect to a predetermined set of AND gate outputs (typically 3-16 terms per output), which limits the device to fewer simultaneous outputs and simpler logic structures compared to the fully programmable interconnects in PLAs.[11] This fixed OR structure in PALs simplifies manufacturing, reduces cost, and enhances speed by minimizing routing complexity, but it sacrifices the PLA's ability to share product terms across multiple outputs, making PALs better suited for applications with limited output requirements.[9] Field-Programmable Gate Arrays (FPGAs) differ fundamentally from PLAs through their use of configurable logic blocks based on lookup tables (LUTs), flip-flops, and extensive programmable interconnect resources, enabling gate-level reconfigurability and support for both combinational and sequential logic across high-density arrays of thousands to millions of gates.[12] While FPGAs offer superior scalability for large-scale designs like processors or signal processors, they introduce higher overhead in area, power, and configuration time, rendering them overkill and more costly for small-to-medium combinational tasks where PLAs' simpler AND-OR architecture provides balanced performance without extensive routing.[13] PLAs occupy a niche in programmable logic for medium-complexity combinational circuits, such as state machine decoders or arithmetic units, where their dual programmability delivers efficient sum-of-products implementations with moderate flexibility, outperforming PROMs and PALs in versatility while avoiding the complexity and expense of FPGAs for non-reconfigurable, logic-focused applications.[10]Historical Development
Origins and Early Innovations
The conceptual origins of programmable logic arrays (PLAs) trace back to the 1960s, when engineers began exploring programmable matrices and diode arrays to simplify complex logic functions in digital circuits. These early diode arrays, often implemented on printed circuit boards, allowed for configurable connections between inputs and outputs, providing a flexible alternative to hardwired logic gates and enabling rapid prototyping of custom combinational and sequential logic.[14] This approach evolved from broader efforts in semiconductor memory and associative arrays, such as IBM's read-only associative memory (ROAM), which influenced the development of integrated programmable structures for logic simplification.[15] The first commercial PLA was introduced by Texas Instruments in 1970 with the TMS2000, a mask-programmable integrated circuit based on ROAM technology. This device featured 17 inputs, 32 product terms, 18 outputs, and support for up to 8 JK flip-flops, allowing it to implement sum-of-products logic in a single chip for applications requiring custom sequential and combinational functions. Texas Instruments coined the term "programmable logic array" to describe this innovation, marking a shift from bipolar diode arrays to metal-oxide-semiconductor (MOS) technology for greater density and efficiency.[16][15] In 1975, Signetics introduced the 82S100, the first field-programmable logic array (FPLA), using fuse-based programming to allow user reconfiguration without custom masks.[17] Key innovations in the early 1970s included the adoption of fused-link and antifuse programming techniques, which provided permanent, one-time configuration of interconnections in the AND and OR planes, reducing manufacturing costs for custom logic compared to full custom ASICs. Fused links operated by selectively blowing thin metallic connections to open circuits, while antifuses created connections by rupturing insulating layers under high voltage, both enabling reliable, non-volatile programming without the need for mask changes in production. These methods facilitated cost-effective deployment of PLAs in volume applications, prioritizing conceptual flexibility over exhaustive reconfiguration.[5][18] Early adopters of PLAs in the 1970s included Texas Instruments, which integrated PLA structures into handheld calculators and simple control systems for arithmetic operations and state machine implementations, such as key decoding and display driving in early electronic calculators.[19]Evolution and Key Milestones
In the 1980s, programmable logic array (PLA) technology underwent significant advancements, particularly the transition from bipolar to CMOS processes, which enabled lower power consumption and improved performance for portable and battery-operated applications.[20] This shift was exemplified by the introduction of CMOS-based reprogrammable logic arrays, such as Altera's EP300 in 1984, which offered ultraviolet erasability and reduced power draw compared to earlier TTL devices.[21] The Signetics 82S100 FPLA was integrated into the Commodore 64 computer in 1982 to handle control logic functions.[20] The 1990s saw further milestones in PLA evolution, including deeper integration with microprocessors and the rise of electrically erasable variants for enhanced field reprogrammability. PLAs were commonly paired with MOS 6502 microprocessor variants, such as the 6510 in Commodore systems, where they served as flexible decode and control elements to support evolving system requirements without full chip redesigns.[4] Electrically erasable programmable logic devices, leveraging EEPROM technology, gained prominence through the decade for their ability to be reprogrammed multiple times without special equipment, addressing limitations of one-time fuse-based programming.[17] From the 2000s into the 2020s, standalone PLAs experienced a decline in popularity, largely superseded by more versatile field-programmable gate arrays (FPGAs) that offered greater density and reconfiguration flexibility for complex designs.[22] However, PLA structures persisted in embedded application-specific integrated circuits (ASICs) and as intellectual property (IP) cores within system-on-chips (SoCs), where their compact sum-of-products implementation proved efficient for glue logic tasks like signal routing and simple state machines.[23] In the 2010s, the emergence of open-source electronic design automation (EDA) tools, such as Yosys (initiated in 2011), facilitated PLA synthesis and optimization in custom VLSI flows, revitalizing their use in academic and hobbyist prototyping despite the dominance of FPGAs.[24]Architecture
AND-OR Plane Structure
The core architecture of a programmable logic array (PLA) consists of two primary planes: the AND plane and the OR plane, which together form a two-level logic structure for implementing combinational functions.[25][26] The AND plane precedes the OR plane, with product terms generated in the former serving as inputs to the latter. This arrangement provides a regular, array-based layout that supports flexible signal routing through programmable crosspoints.[27][28] The AND plane is an array of programmable AND gates designed to generate product terms from the input signals and their complements. Inputs, available in both true and complemented forms, are distributed across vertical lines within the plane, while horizontal lines represent potential product terms.[25][2] At each intersection of an input line and a product term line, a programmable crosspoint—such as a fuse, anti-fuse, or via—allows selective connection, enabling the formation of specific product terms by ANDing subsets of the inputs.[27] In practice, the AND plane often employs NAND or NOR gates for implementation, leveraging DeMorgan's laws to achieve the AND functionality with inverted outputs.[28] For N inputs, the plane can theoretically support up to 2^N minterms, though it is typically configured with K rows to produce a limited number of product terms for efficiency.[2] The OR plane follows the AND plane and comprises an array of programmable OR gates that sum selected product terms to produce the output signals. Product terms from the AND plane extend horizontally into this plane, intersecting with vertical lines dedicated to individual outputs.[25][26] Programmable crosspoints at these intersections determine which product terms contribute to each output, allowing multiple terms to be ORed together. Like the AND plane, the OR plane is frequently realized using NOR or NAND gates for compatibility with fabrication processes.[28] With K product terms feeding into the OR plane, up to M outputs can be generated, where M represents the number of output lines.[2] The interconnections between the planes are seamless, with the horizontal product term lines from the AND plane directly feeding into the OR plane without additional buffering in basic designs.[27] This vertical stacking of planes—inputs entering the top of the AND plane, product terms traversing horizontally, and outputs exiting the bottom of the OR plane—creates a compact, grid-like structure. A textual representation of a simple PLA with N=3 inputs, K=4 product terms, and M=2 outputs might appear as follows:This layout ensures predictable signal paths and minimizes wiring complexity.[25][28]Inputs (vertical): x1, x1', x2, x2', x3, x3' | AND Plane (crosspoints programmable) | Product Terms (horizontal): P1, P2, P3, P4 | OR Plane (crosspoints programmable) | Outputs (vertical): y1, y2Inputs (vertical): x1, x1', x2, x2', x3, x3' | AND Plane (crosspoints programmable) | Product Terms (horizontal): P1, P2, P3, P4 | OR Plane (crosspoints programmable) | Outputs (vertical): y1, y2
Programmable Elements and Wiring
In programmable logic arrays, the core of configurability lies in the programmable elements positioned at crosspoints within the AND and OR planes, where each intersection functions as a switchable link to selectively connect input lines to product terms and product terms to outputs. These elements determine whether a logical connection is established or severed, enabling the realization of arbitrary combinational functions in sum-of-products form. Typical densities range from 48 to hundreds of product terms per device, allowing for hundreds to thousands of configurable crosspoints depending on the implementation scale.[5][29][30] Various technologies serve as these programmable elements, with bipolar fuses being prominent in early designs; these consist of thin nichrome (Ni-Cr) links that are irreversibly blown by applying a high-current pulse (e.g., 300 mA at 17 V) to create an open circuit and disconnect unwanted paths. In contrast, CMOS-based PLAs often employ pass transistors as switches, where an nMOS or transmission gate is controlled by a configuration signal to either pass or block the signal between lines, offering lower resistance when on compared to fuses. EEPROM cells provide a non-volatile alternative, utilizing floating-gate transistors that store charge to control conductivity—programming applies high voltage to trap electrons, altering the threshold voltage and thus the connection state, while erasure reverses this electrically without UV exposure.[29][6][30] Wiring configurations are categorized by programmability: mask-programmed PLAs fix connections via custom metal layers during fabrication, ideal for high-volume applications with no user reconfiguration. Field-programmable options, such as those using EEPROM cells or fusible links, permit post-manufacture alterations by the user through electrical means, supporting iterative design. One-time programmable (OTP) wiring via antifuses involves initially high-resistance dielectric structures that are programmed by voltage-induced breakdown to form a permanent low-resistance path, balancing security and irreversibility without the need for repeated access.[5][30] The selection of programmable elements significantly influences power consumption, area efficiency, and overall density; for instance, bipolar fuse-based PLAs offer high speed but higher power draw (typically 600 mW) and larger footprints due to the physical links, whereas CMOS pass transistors and EEPROM cells enable compact layouts with reduced power (e.g., 37 mA at 25 MHz operation) and better scalability for denser crosspoint arrays, though at the potential cost of slightly slower switching in some cases.[29][30][5]Operation
Sum-of-Products Logic Implementation
A programmable logic array (PLA) realizes Boolean functions in the canonical sum-of-products (SOP) form, where each output is expressed as the logical OR of one or more product terms, and each product term is the logical AND of literals derived from the inputs or their complements.[31] This form allows for efficient implementation of combinational logic, as the AND plane in a PLA generates the necessary product terms, while the OR plane combines them to produce the outputs.[32] The SOP representation is particularly suited to PLAs because it directly maps to the device's two-level AND-OR structure, enabling flexibility in selecting which literals contribute to each term.[31] For a set of inputs x_1, x_2, \dots, x_n, a product term P_i is formed as the AND of selected literals, where each literal is either the true input x_j, the complemented input \overline{x_j}, or omitted (don't care condition, no connection to that input).[32] Each output Y_j is then the sum (OR) of selected product terms: Y_j = \sum_{i=1}^K P_i, where K is the number of product terms contributing to that output, and the selection is programmable via the OR plane.[31] In the AND plane, fuses or antifuses are configured to connect the appropriate literals to each AND gate, generating up to $2^n possible minterms, though optimization often uses fewer terms by incorporating don't cares to minimize the logic.[32] A representative example is the implementation of a 2-input multiplexer (MUX), which selects between two data inputs A and B based on a select input S. The Boolean function in SOP form is Y = \overline{S} \cdot A + S \cdot B, where the first product term \overline{S} \cdot A (with don't care for B) activates when S = 0, and the second term S \cdot B (with don't care for A) activates when S = 1.[32] In a PLA, the AND plane would program two product terms: one connecting \overline{S} and A (ignoring B), and the other connecting S and B (ignoring A); the OR plane then sums these for the single output Y. This configuration leverages don't cares to reduce the number of connections, demonstrating how PLAs optimize SOP expressions for compact realization.[31]Input/Output Configuration and Timing
Input signals to a programmable logic array (PLA) are typically processed through input buffering stages that provide both active-high and active-low decoding, enabling the generation of complemented literals directly for the AND plane. These buffers ensure signal integrity and include inverters to produce the true and inverted forms of each input variable, allowing flexible implementation of logic functions without additional external inversion circuitry.[33] Output configuration in PLAs often employs wired-OR connections in the OR plane to combine multiple product terms for each output, facilitating efficient multi-output logic realization. For shared bus interfaces or bidirectional operations, tri-state buffers are integrated at the outputs, enabling high-impedance states when disabled to avoid conflicts among multiple drivers. Don't care conditions in the logic specification are exploited during minimization to consolidate product terms, reducing the number of active lines in the OR plane and optimizing overall density.[12][34] Timing analysis in PLAs focuses on propagation delays through the two-level structure, where the total delay t_{PLA} = t_{AND} + t_{OR}, with t_{AND} representing the delay across the programmable AND plane and t_{OR} across the OR plane. Increased fan-in in the AND plane lengthens t_{AND} due to more parallel paths per product term, while higher fan-out from the AND to OR plane amplifies t_{OR} as signals drive multiple OR inputs; typical commercial PLAs exhibit delays of 2-35 ns depending on scale.[7][12] Converting a truth table to PLA configuration involves identifying minterms where outputs are logic 1 and grouping them into shared product terms via minimization techniques like Karnaugh maps. For a 4-input function with 16 possible rows, each minterm corresponds to a unique input combination; steps include listing the minterms for each output, deriving prime implicants to form product terms (e.g., combining adjacent minterms to eliminate variables), assigning these to AND plane rows, and connecting relevant terms to OR plane columns for each output.[35][31]Design and Programming
Implementation Procedure
The implementation procedure for a programmable logic array (PLA) involves a systematic workflow to translate logic specifications into a programmable structure. The process begins with deriving the required Boolean equations from the circuit specifications or truth table, expressing the desired outputs in sum-of-products (SOP) form.[36] These equations are then minimized to reduce the number of product terms, typically using Karnaugh maps for smaller input sets or the Quine-McCluskey algorithm for larger ones, prioritizing shared terms across multiple outputs to optimize PLA resource usage.[36] The minimized product terms are assigned to the AND plane by determining the input literal connections (including complements) that generate each term.[37] These terms are subsequently mapped to the OR plane, where connections are selected to form the SOP expressions for each output.[37] The final step generates a fuse map or netlist, specifying which fusible links to sever (in fuse-based PLAs) or program to establish the connections.[37] The architectural realization follows a five-block model to support efficient signal flow and logic computation. Input buffers receive and condition external signals, preventing loading on source circuits while providing both true and complemented literals to the AND array.[38] The AND array, a grid of programmable AND gates, produces the minimized product terms.[38] The OR array then combines selected product terms via programmable OR gates to yield the output logic functions.[38] Output buffers drive the final signals with sufficient strength for external interfacing, and optional flip-flops can be included at the outputs for sequential logic, enabling registered designs without additional components.[38] Verification ensures correctness prior to physical programming or fabrication, typically through simulation of the fuse patterns against the original truth table to confirm all input-output mappings.[37] This step identifies any mismatches in product term assignments or OR plane connections, allowing iterative refinement of the fuse map. For illustration, a three-input odd parity checker—which asserts an output for an odd number of input 1s—demonstrates the procedure. The canonical SOP form sums minterms m_1 + m_2 + m_4 + m_7, corresponding to inputs 001, 010, 100, and 111.[39] Minimization yields four terms: P = \bar{A}\bar{B}C + \bar{A}B\bar{C} + A\bar{B}\bar{C} + ABC [40]These are assigned to the AND plane (e.g., first term connects to \bar{A}, \bar{B}, C; second to \bar{A}, B, \bar{C}) and OR plane (all to the single output), fitting a small PLA with at least four product terms.[40]