Fact-checked by Grok 2 weeks ago

Successive-approximation ADC

A successive-approximation analog-to-digital converter (SAR ADC), also known as a successive-approximation register ADC, is an electronic circuit that converts a continuous analog voltage signal into a discrete digital value using a binary search algorithm to iteratively approximate the input by determining each bit from the most significant bit (MSB) to the least significant bit (LSB).^[1] This process begins with sampling and holding the analog input, followed by a series of comparisons between the input voltage and the output of an internal digital-to-analog converter (DAC), adjusting the approximation at each step until the full resolution is achieved after N clock cycles for an N-bit converter.^[2] The core architecture of a SAR ADC typically includes a sample-and-hold amplifier (SHA) to capture and stabilize the input signal, a successive approximation register (SAR) to control the bit-testing sequence, a capacitive DAC (CDAC) for generating reference voltages, and a high-speed comparator to evaluate whether the current DAC output exceeds or falls short of the held input.^[3] During operation, the SAR initializes the MSB to logic high (midscale), enabling the CDAC to produce half the full-scale voltage; the comparator then decides if this is higher or lower than the input, setting the bit accordingly and proceeding to the next bit, mimicking a binary search that converges on the digital code in logarithmic time relative to resolution.^[4] This design ensures no pipeline latency, making it suitable for applications requiring immediate data availability, such as single-shot measurements or multiplexed channels.^[2] SAR ADCs offer resolutions from 8 to 18 bits, with sampling rates up to 20 MSPS depending on the implementation, balancing speed and precision better than flash ADCs for medium resolutions while consuming lower power—often scalable with throughput—and occupying a smaller die area due to fewer components.^[1]^[5] Their advantages include high linearity, ease of integration in CMOS processes, and suitability for battery-powered devices like medical instruments, industrial sensors, and motor controls, though they are limited by conversion time scaling linearly with bit count and require precise component matching to avoid errors.^[3] Compared to delta-sigma ADCs, SAR types provide lower latency (1-3 samples) and better handling of transient signals but trade off higher effective resolutions and built-in noise shaping.^[2]

Overview

Definition and Principles

A successive-approximation analog-to-digital converter (SAR ADC) is a type of data converter that transforms continuous analog input signals into discrete digital representations through an iterative binary search process.^[6] This architecture approximates the input voltage by successively refining an estimate, bit by bit, to achieve the desired digital output code.^[7] SAR ADCs are valued for their balance of performance metrics, making them suitable for applications requiring precision without excessive power consumption.^[8] The fundamental principle involves first capturing the analog input using a sample-and-hold circuit to maintain a stable voltage during conversion.^[8] The process then proceeds by testing each bit from the most significant bit (MSB) to the least significant bit (LSB): an internal digital-to-analog converter (DAC) generates a reference voltage based on the current approximation, which is compared to the held input by a comparator.^[7] Depending on the comparison outcome, the successive-approximation register (SAR) logic sets or clears the bit and updates the DAC for the next iteration, effectively halving the uncertainty range with each step until the full digital code is determined.^[6] At a high level, the SAR ADC comprises four primary elements: the input sample-and-hold circuit, the comparator for voltage comparisons, the SAR logic to orchestrate the binary search, and the feedback DAC to produce trial reference voltages.^[8] These components enable resolutions typically ranging from 8 to 18 bits, with conversion requiring exactly N clock cycles for an N-bit output, thus trading off speed for higher accuracy compared to parallel architectures like flash ADCs.^[7] SAR ADCs provide moderate conversion speeds and excellent power efficiency, distinguishing them from faster but more power-intensive flash converters or slower, higher-resolution sigma-delta types.^[6]

Key Components

The successive-approximation analog-to-digital converter (SAR ADC) relies on several core hardware components that work together to perform binary search-based digitization of an analog input signal. These building blocks include the sample-and-hold circuit, comparator, successive approximation register, digital-to-analog converter, and clock and control logic, each contributing to the precision and efficiency of the conversion process.^[2] The sample-and-hold circuit captures the input analog voltage and maintains it at a constant level throughout the conversion to prevent signal variations from affecting accuracy. It typically consists of a switch and capacitor arrangement, where the switch closes to acquire the input during the sampling phase and opens to hold the charge on the capacitor, feeding a stable voltage to the comparator. This component ensures that dynamic input signals, such as AC waveforms, are accurately represented without droop or distortion during the multi-step approximation.^[9]^[2] The comparator serves as the decision-making element, comparing the held sample voltage against the output of the digital-to-analog converter to determine whether the input exceeds the current reference level. It outputs a single binary bit—high if the sample is greater than the DAC voltage, or low otherwise—which directly informs the next step in the approximation. High-speed, low-offset comparators are essential in SAR ADCs to minimize errors in bit decisions, often employing regenerative latch designs for rapid settling.^[1]^[2] The successive approximation register (SAR) is the digital control core that orchestrates the bit-testing sequence, starting from the most significant bit and proceeding to the least significant bit over N cycles for an N-bit resolution. It initializes the DAC to half the full-scale reference, loads the comparator's bit decision into a shift register, and updates the DAC accordingly for the next comparison, effectively implementing the binary search algorithm. The SAR also handles output formatting and end-of-conversion signaling, making it the central logic hub for the converter's operation.^[10]^[2] The digital-to-analog converter (DAC) generates precise analog reference voltages based on the current SAR bit pattern, enabling the comparator to test incremental approximations of the input. In SAR ADCs, the DAC is often implemented as a capacitive array for charge redistribution, converting the digital code to a voltage proportional to the reference, with the MSB initially set to produce midscale output. It is typically the most power-intensive component due to the need for high linearity and low noise across the full dynamic range.^[1]^[2] Clock and control logic provide the synchronous timing framework for the conversion, generating pulses to sequence operations such as sampling, bit trials, and result latching. An internal or external clock, often in the range of 1 MHz to 30 MHz, drives the SAR through each approximation step, while control signals like CONVERT START initiate the process and indicate busy or end-of-conversion status. This logic ensures precise coordination among components, preventing timing skews that could degrade resolution.^[2]^[9]

Historical Development

Origins and Early Designs

The successive-approximation analog-to-digital converter (ADC) emerged in the mid-20th century as a response to the growing need for efficient digitization in pulse-code modulation (PCM) systems, particularly for telephony and emerging military applications such as radar and telemetry. These systems required converters that balanced speed and resolution, filling the gap between high-speed but low-resolution flash ADCs and slower, higher-resolution integrating types. Early motivations centered on reducing hardware complexity and cost in PCM transmission, like the T1 carrier system, where analog voice signals needed to be digitized for multiplexing and noise-resistant transmission over long distances.^[2] The foundational design was described in 1947 by W. M. Goodall at Bell Telephone Laboratories, who detailed an experimental 5-bit successive-approximation ADC operating at 8 kSPS. This implementation used binary-weighted charge subtraction on a capacitor to approximate the input voltage iteratively, avoiding the need for complex mechanical or relay-based counters prevalent in prior converters. Goodall's work, published in the Bell System Technical Journal, represented a key step toward electronic realization, driven by wartime and postwar demands for reliable signal processing in communication networks.^[2] Commercialization arrived in 1955 with Bernard M. Gordon at EPSCO (now Analogic), who developed the first vacuum-tube-based successive-approximation ADC: an 11-bit device sampling at 50 kSPS, priced at $8,000 per unit. Gordon's design incorporated a binary-weighted digital-to-analog converter (DAC) and comparator for the approximation process, patented later as US 3,108,266 (1963, filed earlier). An additional patent by Gordon in 1958 (US 2,997,704, issued 1961) formalized the successive-approximation register (SAR) logic controlling the binary search. These innovations were spurred by instrumentation needs in defense and scientific measurement, where moderate resolution (8–12 bits) and speeds (10–100 kSPS) were essential.^[2]^[11] Initial designs faced significant challenges due to reliance on vacuum tubes and later discrete transistors, resulting in bulky circuits, high power consumption (often tens of watts), and limited scalability. For instance, Gordon's ADC required multiple tubes for amplification and switching, making it impractical for portable or low-power applications but suitable for rack-mounted instrumentation of the era. These limitations motivated subsequent shifts toward solid-state components in the 1960s, though early SAR ADCs established the architecture's viability for medium-performance conversion.^[2]

Key Milestones and Evolution

In the 1960s and 1970s, successive-approximation ADCs transitioned from discrete components to integrated circuits, with the introduction of MOS technology enabling lower power consumption and improved integration. A notable early example was the ADC-12U, a 12-bit SAR ADC released by Analog Devices in 1969, which utilized a µA710 comparator and Minidac for 10-µs conversion time.^[12] This period marked the shift toward commercial off-the-shelf products, culminating in the first complete monolithic SAR ADC, the 10-bit AD571 introduced by Analog Devices in 1978, designed by Paul Brokaw on a bipolar process.^[12]^[13] The 1980s saw the popularization of the charge-redistribution topology, originally proposed in 1975 by J.L. McCreary and P.R. Gray for all-MOS successive-approximation conversion using binary-weighted capacitors. This capacitor-based DAC approach reduced reliance on precision resistors, enhanced component matching through layout techniques, and facilitated CMOS implementations, as exemplified by 12-bit SAR ADCs like the AD574, which became an industry standard with 35-µs conversion time.^[2] By the late 1980s, CMOS SAR designs such as the AD7871 achieved 14-bit resolution at 83 kSPS, further leveraging charge redistribution for compact, low-power operation.^[12] During the 1990s and 2000s, advancements in sub-micron CMOS processes allowed SAR ADCs to scale to higher resolutions beyond 16 bits while maintaining efficiency. For instance, the AD7664, a 16-bit SAR ADC sampling at 570 kSPS, was introduced by Analog Devices in 2000 as part of the Pulsar series, benefiting from reduced parasitics in advanced nodes.^[12] Hybrid architectures, such as SAR-assisted pipeline designs, emerged to boost speeds, combining the precision of SAR with pipelined staging for throughputs exceeding traditional SAR limits, up to several MSPS in sub-micron implementations.^[14] From the 2010s onward, SAR ADC development emphasized ultra-low-power designs tailored for portable and battery-operated devices, achieving effective number of bits (ENOB) greater than 14 at power consumptions below 1 mW through techniques like asynchronous operation and digital calibration.^[6] This era's focus on fine-line CMOS nodes, such as 65 nm and below, enabled high-resolution, energy-efficient converters suitable for embedded systems, with innovations in capacitor switching reducing switching energy by over 90% compared to conventional methods.^[15]

Operating Mechanism

Algorithm Steps

The successive-approximation analog-to-digital converter (ADC) operates through a binary search algorithm that iteratively refines an estimate of the input voltage V_{in} over N clock cycles for an N-bit resolution.^[2] The process begins with initialization: the input voltage V_{in} is sampled and held by the sample-and-hold circuit, the successive approximation register (SAR) is reset to zero except for setting the most significant bit (MSB) to 1 (resulting in a code like 100...0), and the digital-to-analog converter (DAC) generates an output of V_{ref}/2, where V_{ref} is the reference voltage.^[2] The comparator then plays a key role in each subsequent decision by comparing V_{in} to the DAC output.^[16] In the iteration loop, for each of the N bits starting from the MSB, the comparator determines if V_{in} is greater than or equal to the current DAC output; if greater than or equal to, the tested bit is kept as 1 and the next lower bit is set to 1 for the subsequent DAC update (adding the corresponding weight), whereas if less than, the tested bit is reset to 0 and the next lower bit is set to 1 for testing.^[2] This halves the decision range per step, with the SAR storing the bit decisions sequentially from MSB to LSB.^[16] Upon completion after N cycles, the SAR holds the N-bit digital code representing the quantized value of V_{in}, which is then output as the binary approximation scaled to the range $0 to V_{ref}.^[2] A numerical example illustrates this for a 4-bit ADC with V_{ref} = 16 V and V_{in} = 10 V (where each least significant bit corresponds to 1 V). In step 1 (MSB, bit 3), the SAR is 1000, producing DAC = 8 V; since 10 > 8, keep bit 3 = 1 and test bit 2, yielding SAR = 1100 and DAC = 12 V. In step 2, 10 < 12, so set bit 2 = 0 and test bit 1, yielding SAR = 1010 and DAC = 10 V. In step 3, 10 = 10, so keep bit 1 = 1 and test bit 0, yielding SAR = 1011 and DAC = 11 V. In step 4, 10 < 11, so set bit 0 = 0, resulting in final SAR = 1010 (decimal 10, matching V_{in}).^[16]

Mathematical Basis

The successive-approximation register (SAR) ADC employs a binary search algorithm to determine the digital representation of an analog input voltage V_{in} within the reference range [0, V_{ref}]. Initially, the search interval is defined by V_{low} = 0 and V_{high} = V_{ref}. For each of the N bits, starting from the most significant bit (MSB), the digital-to-analog converter (DAC) produces a test voltage V_{DAC} = V_{low} + \frac{V_{high} - V_{low}}{2}, which represents the midpoint of the current interval. The comparator then evaluates whether V_{in} \geq V_{DAC}; if true, the bit is set to 1 and V_{high} is updated to V_{DAC}, otherwise the bit is set to 0 and V_{low} is updated to V_{DAC}. After k iterations, the interval width narrows to \frac{V_{ref}}{2^k}, ensuring the final approximation converges to within one least significant bit (LSB) of the true value.^[9] The quantized digital output D, an N-bit integer, is given by D = \round\left( \frac{V_{in}}{V_{ref}} \cdot 2^N \right), where the rounding operation selects the nearest code transition point. The corresponding analog value is V_{out} = D \cdot \frac{V_{ref}}{2^N}, and the LSB voltage step is defined as \text{LSB} = \frac{V_{ref}}{2^N}. In an ideal SAR ADC, this quantization process yields a perfectly linear transfer function with uniform step sizes.^[17] Under ideal conditions, the integral nonlinearity (INL) and differential nonlinearity (DNL) are both zero, as there are no deviations from the straight-line ideal transfer characteristic or uniform 1-LSB steps. The total conversion time is T = N \cdot T_{clk}, where T_{clk} is the clock period allocated for each bit decision and settling.^[9]^[17] For a uniform input distribution across [0, V_{ref}], the probability of any bit decision resulting in a 1 is 0.5, reflecting the balanced halving of the search space at each step, with bit decisions being statistically independent in the ideal scenario.^[18]

Implementations

Charge-Redistribution Design

The charge-redistribution design is a widely adopted implementation of the successive-approximation register (SAR) analog-to-digital converter (ADC), utilizing a binary-weighted capacitor array to serve as the internal digital-to-analog converter (DAC). This topology features an array of capacitors with values scaled in binary proportions: the most significant bit (MSB) capacitor has capacitance C, the next C/2, and so on down to the least significant bit (LSB) capacitor with C/2^{N-1}, where N is the ADC resolution in bits. The total capacitance of the array is thus C_{\text{total}} = 2^N \cdot C_{\text{unit}}, with C_{\text{unit}} representing the unit capacitance of the LSB element. This configuration enables precise charge storage and manipulation without relying on resistive elements.^[19] The conversion process in this design relies on charge sharing between the analog input and the capacitor array, adapting the successive-approximation algorithm through discrete charge packets on the capacitors. It begins in the sampling phase, where the input voltage V_{\text{in}} charges all capacitors in the array via their bottom plates while the common top plate is typically grounded or referenced. The hold phase isolates the input, preserving the trapped charge Q = C_{\text{total}} \cdot V_{\text{in}}, and connects the bottom plates to ground, resulting in a top-plate voltage V_{\text{top}} = -V_{\text{in}}. For the MSB decision, the bottom plate of the largest capacitor (MSB) is switched to the reference voltage V_{\text{ref}} (while others remain at ground), producing V_{\text{top}} = -V_{\text{in}} + V_{\text{ref}}/2; the comparator then assesses whether V_{\text{top}} exceeds 0 (equivalent to checking if the trial V_{\text{DAC}} = V_{\text{ref}}/2 > V_{\text{in}}). If V_{\text{top}} > 0, the MSB bit is set to 0 and the bottom plate is switched back to ground (V_{\text{DAC}} = 0); otherwise, the bit is 1 and it remains at V_{\text{ref}} (V_{\text{DAC}} = V_{\text{ref}}/2). Subsequent bits proceed iteratively, with charge redistribution updating V_{\text{DAC}} by \pm V_{\text{ref}}/2^k for the k-th bit, converging on the digital code representation of V_{\text{in}}.^[20]^[1] A key advantage of this capacitor-based topology is the elimination of resistors, which simplifies fabrication and enhances compatibility with complementary metal-oxide-semiconductor (CMOS) integrated circuit processes due to the compact size and low power consumption of capacitors. Furthermore, the inherent charge redistribution mechanism supports auto-zeroing during the sampling phase, where residual offsets in the comparator and switches are automatically compensated by sharing charges, thereby improving overall accuracy without additional circuitry.^[19]^[1] Despite these benefits, parasitic capacitances—particularly at the top plate of the array—can degrade capacitor matching by altering effective charge distribution, resulting in integral nonlinearity (INL) errors that may reach up to 0.5 LSB in uncalibrated designs, necessitating techniques like trimming or digital correction for higher resolutions.^[1]

Other Architectural Variants

One notable variant of the successive-approximation register (SAR) ADC employs an R-2R ladder network for the internal digital-to-analog converter (DAC), where precision resistors arranged in a binary-weighted ladder generate the reference voltages needed for bit trials.^[2] This architecture, pioneered in early implementations like Bernard M. Gordon's vacuum-tube SAR ADC, switches equal currents into the resistor network to produce accurate analog outputs, offering simplicity in design and scalability for resolutions up to 11 bits.^[2] However, it consumes higher power due to continuous current flow through the resistors and exhibits increased glitch energy from switching transients, making it less ideal for modern low-power applications compared to capacitor-based alternatives.^[2] Another architectural approach integrates current-steering DACs within the SAR framework, utilizing arrays of matched current sources to generate differential currents that are integrated and compared against the input signal.^[21] This design replaces traditional voltage-based DACs with current-mode operation, often incorporating a regenerative comparator and current sample-and-hold for efficient residue processing.^[22] It excels in high-speed conversions, achieving sampling rates suitable for broadband applications, but remains sensitive to process variations and mismatches in current sources, which can degrade linearity without calibration.^[23] Hybrid pipeline-SAR architectures combine the precision of SAR quantization with pipelined processing to extend speed beyond standalone SAR limits, typically resolving 1.5 to 2 bits per stage through multi-bit sub-ADCs followed by residue amplification.^[24] In this setup, an initial SAR stage performs coarse approximation, passing the residue to subsequent pipeline stages that use dynamic amplifiers or passive transfer for high throughput exceeding 100 MS/s.^[25] The hybrid nature reduces power overhead from full flash stages while maintaining resolution, though inter-stage gain errors require careful calibration to preserve overall accuracy.^[26] Asynchronous SAR variants eliminate a global clock by employing self-timed logic, where each bit decision triggers the next comparison phase upon comparator settling, enabling adaptive timing based on signal conditions.^[27] This clock-free operation minimizes switching activity in low-activity scenarios, yielding significant power savings through reduced dynamic dissipation in the digital control logic. The self-timed handshake protocol enhances efficiency in variable-speed applications but demands robust metastability resolution to avoid timing errors.^[28]

Performance Analysis

Advantages and Limitations

Successive-approximation register (SAR) ADCs offer significant advantages in power efficiency, making them suitable for applications where energy consumption is critical. For instance, a 12-bit SAR ADC can achieve operation at under 1 mW, such as 53 μW at 1 MS/s sampling rate.^[29] This low power profile stems from their simple architecture, which relies on a capacitor-based digital-to-analog converter (DAC) and a comparator without the need for continuous operation of multiple stages. Additionally, SAR ADCs provide a favorable balance between resolution and speed, supporting up to 5 MS/s for resolutions as high as 16 bits, while maintaining high accuracy.^[1] Unlike pipeline ADCs, SAR ADCs exhibit no inherent conversion latency, delivering the output directly after the approximation process, which enhances their utility in real-time systems. Despite these strengths, SAR ADCs have notable limitations related to their sequential operation. The conversion time is inherently proportional to the number of bits (N), requiring at least N clock cycles for an N-bit resolution, which caps their maximum sampling rates compared to parallel architectures.^[1] They are also particularly susceptible to clock jitter, as timing errors accumulate over multiple cycles and degrade signal-to-noise ratio in high-frequency applications.^[30] Furthermore, achieving high resolution demands precise components, including a well-matched capacitor array in the DAC and a low-offset comparator, increasing design complexity and sensitivity to process variations.^[1] Performance comparisons often use the figure of merit (FoM) defined as power divided by (2 raised to the effective number of bits times the sampling frequency), where SAR ADCs demonstrate excellence in medium-speed scenarios with FoM values around 10-50 fJ/conversion-step.^[31] This metric highlights their efficiency for resolutions up to 18 bits and sampling rates below 10 MS/s. SAR ADCs are thus ideal for battery-powered devices like portable sensors and medical instruments, but they are unsuitable for ultra-high-speed requirements exceeding 100 MS/s, where flash or pipeline architectures are preferred.^[1]

Sources of Error in Non-Ideal Systems

In non-ideal successive-approximation register (SAR) ADCs, comparator offset arises from mismatches in the differential input transistors or other circuit imbalances, introducing a fixed voltage error that shifts the decision threshold during bit comparisons. This offset can cause decision errors of up to ±0.5 LSB, potentially leading to incorrect bit settings and overall code inaccuracies across the transfer function. Hysteresis in the comparator, resulting from positive feedback mechanisms to prevent oscillations, exacerbates this by creating a dependency on the previous input state, further distorting thresholds for successive approximations. A common mitigation technique is auto-zeroing, where the comparator inputs are shorted during a dedicated phase to sample and subtract the offset voltage before active comparisons.^[32]^[33] DAC nonlinearity in SAR ADCs primarily stems from integral nonlinearity (INL) and differential nonlinearity (DNL), caused by mismatches in the capacitor array or resistor ladder elements that form the feedback DAC. These mismatches lead to gradient errors across the device due to process variations or layout-induced voltage drops, deviating the DAC output from the ideal straight-line transfer function. INL is quantified as the maximum deviation from the best-fit straight line in LSBs, while DNL measures the variation in step size between adjacent codes, also in LSBs; severe DNL exceeding ±1 LSB can result in missing codes or non-monotonic behavior. Such errors directly propagate to the ADC output, limiting effective resolution and introducing harmonic distortion in digitized signals.^[32] Sample-and-hold (S/H) circuits in SAR ADCs are prone to droop, where the held input voltage decays over the conversion time due to leakage currents through switches or finite capacitor insulation resistance, causing signal attenuation and reduced accuracy for longer conversion periods. Aperture error, arising from timing uncertainty or jitter in the sampling instant, introduces additional noise, particularly for high-frequency inputs, as the error voltage is proportional to the signal's slew rate. Aperture jitter limits the maximum input frequency to f_{in} < \frac{1}{2 \pi t_j 2^{N/2}}, where t_j is the rms aperture jitter, f_s is the sampling rate, and N is the resolution in bits; for example, with t_j = 1 ps, this allows f_{in} up to hundreds of MHz for 12-bit resolution, beyond which SNR degrades below the quantization limit. These effects are especially critical in SAR architectures, where the hold phase spans multiple clock cycles for the approximation algorithm.^[32]^[34] Channel charge injection occurs in the MOS switches of charge-redistribution SAR ADCs when the transistor channel charge, accumulated during the on-state, redistributes to the source or drain upon turn-off, injecting an unwanted charge onto the sampling capacitor. This phenomenon is signal-dependent, varying with the input voltage level due to changes in channel charge density, leading to nonlinear offsets that distort the sampled signal and introduce even-order harmonics. In capacitor-based designs, it primarily affects the accuracy of the redistribution process, causing pedestal errors up to several mV, which degrade INL and DNL performance.^[35]

Applications and Advances

Traditional Applications

Successive-approximation register (SAR) ADCs have long been integral to data acquisition systems, particularly in industrial environments where they interface with sensors measuring parameters such as temperature and pressure. In programmable logic controllers (PLCs), SAR ADCs with 12- to 16-bit resolution enable precise digitization of analog signals from these sensors, supporting reliable monitoring and control of machinery at sampling rates up to 500 kSPS.^[36] For instance, devices like the ADS8688 provide multiplexed 16-bit conversion across eight channels for voltage inputs ranging from ±10.24 V, facilitating efficient data collection in factory automation setups.^[36] In communications equipment, SAR ADCs are employed for baseband signal processing in modems and wireless receivers, where their low power consumption—often below 10 mW—aligns with battery-operated or energy-efficient designs. These ADCs handle intermediate frequency signals in cable modems compliant with DOCSIS 3.0 standards, achieving resolutions of 10 to 12 bits at sampling rates around 100 MSPS while minimizing latency through direct sampling architectures.^[37] Similarly, in Bluetooth low-energy receivers, 9-bit SAR ADCs operate at 20 MSPS with a figure-of-merit as low as 3.5 fJ/conv.-step, enabling ultra-low-power digitization for short-range wireless links. SAR ADCs find widespread use in medical devices, particularly portable ECG monitors that require moderate resolution and low sampling rates to capture bioelectric signals without excessive power draw. These converters typically provide 10- to 14-bit resolution at rates under 100 kS/s, such as adaptive sampling from 64 Hz to 512 Hz in wearable ECG systems, ensuring accurate heart rhythm detection in ambulatory settings. In medical imaging applications like portable ultrasound, 12-bit SAR ADCs support 20 MS/s conversion for echo signal processing, though traditional setups prioritize lower rates below 100 kS/s for power-constrained handheld devices measuring blood flow or tissue interfaces.^[38] For general-purpose instrumentation, SAR ADCs are standard in multimeters and oscilloscopes, offering a balance of accuracy and speed for voltage and waveform measurements. In digital multimeters, they deliver 12- to 16-bit resolution for precise DC and AC readings, outperforming integrating ADCs in multiplexed scenarios by providing faster settling times without sacrificing linearity.^[39] Oscilloscopes utilize SAR ADCs for medium-speed signal capture up to 15 MSPS, enabling real-time visualization of analog inputs in test and debugging applications with minimal pipeline delay.

Recent Developments

In the 2020s, successive-approximation register (SAR) analog-to-digital converters (ADCs) have seen significant advancements in high-speed operation, with designs achieving 16-bit resolution at sampling rates up to 5 MS/s in 180 nm CMOS processes. For instance, a split-sampling SAR ADC incorporating digital calibration, redundancy, asynchronous bit-cycling, and monotonic switching demonstrated low noise and power efficiency while meeting these performance targets, enabling applications in time-critical signal processing.^[40]^[41] These developments build on process scaling to support emerging needs in automotive radar systems, where Texas Instruments released integrated radar sensors like the AWR2544 in 2024, featuring high-performance data conversion for extended sensing ranges beyond 200 meters.^[42] Low-power innovations have focused on noise-assisted and calibration-free techniques to push the figure-of-merit (FoM) below 10 fJ/conv-step, particularly for Internet of Things (IoT) devices. A 10-bit asynchronous SAR ADC utilizing modified switching and noise reduction achieved an FoM of 8 fJ/conv-step at 8 MS/s, optimized for IEEE 802.15.1 sensor networks with a compact 55 nm CMOS implementation.^[43]^[44] Surveys of state-of-the-art designs highlight background calibration and multi-comparator noise scaling as key enablers for sub-10 fJ/conv-step performance without external references, reducing overall system power in battery-constrained environments.^[6]^[45] Emerging applications in quantum computing have driven specialized SAR ADC developments, including cryogenic operation for qubit control interfaces. A cryogenic 8-bit 32 MS/s SAR ADC fabricated to function down to 4.2 K supports readout and control in superconducting quantum systems, addressing the need for low-temperature electronics.^[46] The global market for ADCs and DACs in quantum computing, encompassing such pairs for qubit manipulation, grew to USD 36.8 million in 2024 and is projected to exceed USD 200 million by 2030, fueled by advancements in scalable quantum processors.^[47] In AI edge processing, SAR ADCs enable efficient analog-to-digital conversion in low-power devices, integrating with neural accelerators for real-time sensor data handling in distributed intelligence systems.^[48] Recent switching schemes, such as tri-level and monotonic variants, have enhanced energy efficiency by reducing DAC transitions by up to 93%. A Vcm-based tri-level approach in a 2023 SAR ADC design achieved 93.76% switching energy savings over conventional methods while minimizing capacitor area, ideal for biomedical and IoT applications.^[49] Hybrid monotonic-tri-level schemes further optimize complexity and power, with a 2023 implementation reducing energy by 25% relative to prior tri-level techniques and supporting high-resolution conversion in resource-limited settings.^[50]^[51]

References

[1]
Understanding SAR ADCs: Their Architecture and Comparison with ...
Oct 2, 2001 · This paper will explain how the SAR ADC operates by using a binary search algorithm to converge on the input signal.Sar Adc Architecture · In-Depth Sar Analysis · Sar Adcs Compared With Other...Missing: fundamentals | Show results with:fundamentals
[2]
[PDF] MT-021 ADC Architectures II: Successive Approximation ADCs
A successive approximation ADC uses a comparator to determine bits, storing them in a register. The process continues until all bits are determined. SAR stands ...
[3]
[PDF] SAR & Delta-Sigma ADCs Understanding Basic Operation
In fact, the acronym SAR, stands for Successive Approximation Register. The name refers to the process where CDAC is adjusted in successive approximations ...
[4]
Chapter 14: ADC, Data Acquisition and Control
A 12-bit successive approximation ADC is clocked 12 times. At each clock another bit is determined, starting with the most significant bit.Missing: fundamentals | Show results with:fundamentals
[5]
[PDF] Low-Power SAR ADC Design: Overview and Survey of State-of-the ...
Apr 30, 2023 · A. SAR Principle. The SAR ADC uses successive approximation to find the. digital representation of an analog input. For an input with no.
[6]
[PDF] Data Converter Architectures - ANALOG-DIGITAL CONVERSION
The successive approximation ADC has a very simple structure, low power, and reasonably fast conversion times.
[7]
[PDF] MT-021 ADC Architectures II: Successive Approximation ADCs
In order to process ac signals, SAR ADCs must have an input sample-and-hold (SHA) to keep the signal constant during the conversion cycle. SHA. CONTROL. LOGIC:.Missing: definition | Show results with:definition
[8]
Successive-Approximation ADCs: Ensuring a Valid First Conversion
Successive-approximation ADCs comprise four main subcircuits: the sample-and-hold amplifier (SHA), analog comparator, reference digital-to-analog converter (DAC) ...Missing: key | Show results with:key
[9]
Successive Approximation Register (SAR) ADC - Analog Devices Wiki
Jan 3, 2021 · Sample and hold circuit (S/H) to acquire the input voltage (Vin). · Analog voltage comparator that compares Vin to the output of the internal DAC ...Missing: key components
[10]
US3108266A - Signal conversion apparatus - Google Patents
This invention relates in general to an information translating system of the type which converts analog information to digitally coded information by a ...
[11]
[PDF] ANALOG-DIGITAL CONVERSION - 1. Data Converter History
In 1958, Bernard M. Gordon had filed a patent on the logic to perform the successive approximation algorithm (Reference 19), and in the early 1970s, Advanced ...
[12]
[PDF] AD565, 12-Bit, 200-ns DAC, 1978 CMOS IC DACs of the 1970s As ...
The first complete monolithic ADC was the 10-bit, 25-µs AD571 SAR ADC introduced in 1978 and designed by Paul Brokaw (Reference 16). The AD571 was designed on a.
[13]
https://picture.iczhiku.com/resource/eetop/WyKtZgtKpSetoCvx.pdf
[14]
Recent progress on CMOS successive approximation ADCs
Aug 6, 2016 · The SAR-ADC architecture was proposed in 1975 1, when research on the CMOS ADC architecture had just begun. The flash ADC architecture was also ...Missing: history | Show results with:history
[15]
Understanding the Successive Approximation Register ADC
The SAR ADC is a common analog-to-digital converter for sampling rates under 10 MSPS, using a binary search algorithm to approximate the analog signal.
[16]
INL/DNL Measurements for High-Speed Analog-to-Digital ...
Nov 20, 2001 · For an ideal ADC, in which the differential nonlinearity coincides with DNL = 0LSB, each analog step equals 1LSB (1LSB = VFSR/2N, where VFSR is ...
[17]
[PDF] Binary Access Memory: an Optimized Lookup Table for Successive ...
Unlike true random-access memory, the probability of different codes occurring in a binary successive approximation access pattern is not uniformly distributed.<|control11|><|separator|>
[18]
None
### Charge Redistribution SAR ADC Summary
[19]
https://www.renesas.com/en/document/apn/r14an0001-operation-sar-adc-based-charge-redistribution-rev100
[20]
https://www.ti.com/lit/an/slyt176/slyt176.pdf
[21]
[PDF] Modeling and simulation of 8-bit Current-Mode Successive ... - ijcesen
The current mode SAR ADC consists of current-mode block such as current Sample and Hold, a current comparator, a current steering DAC and SAR logic register [5] ...
[22]
Design of 8-bit Low power & High performance SAR ADC using ...
This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5 + 5 + 6 segmented capacitor array.
[23]
[PDF] A SAR-Assisted Two-Stage Pipeline ADC - Semantic Scholar
This paper proposes a two-stage Pipelined-SAR ADC for high-speed, high ... A SAR-based hybrid design incorporating with a hybrid DAC linearization ...
[24]
A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS ... - MDPI
A topology of three-stage comparator is implemented to achieve high-speed and high-resolution. ... SAR ADC with Alternate Comparators for Enhanced Speed in 32 nm ...
[25]
https://www.mdpi.com/2079-9292/9/2/375
[26]
[PDF] A Study of SAR ADC and Implementation of 10-bit Asynchronous ...
This work is mostly focused on investigation of asynchronous or self-timed operation of SAR logic. ... Chapter 4: Successive Approximation Register. 4.1 ...
[27]
A fully integrated 10-bit 100 MS/s SAR ADC with metastability ...
Comparing with traditional synchronous timing SAR logic, asynchronous timing SAR logic can achieve a faster conversion speed without a high frequency input ...<|control11|><|separator|>
[28]
Design of a Low-Power 12-bit SAR ADC - IEEE Xplore
The ADC has conversion rate of 1 MSps and the signal-to-noise-and-distortion ratio of 52.1 dB with power consumption of 53 microwatt. Digital calibration ...Missing: example | Show results with:example
[29]
Considerations for Design of High Speed High Resolution Low ...
This paper presents the design considerations and possible architectures for implementations of high-speed, high-resolution, and low power SAR ADC for direct RF ...Missing: pipeline | Show results with:pipeline
[30]
Analysis of SAR ADC Performance Enhancement Utilizing ...
Jul 5, 2023 · ... ADC figure-of-merit (FoM). As this scheme allows the use of a high-input-referred-noise but low-power comparator in the SAR ADC, the total ...
[31]
[PDF] ANALOG-DIGITAL CONVERSION
A successive approximation ADC with an internal non-monotonic. DAC will generally produce missing codes but remain monotonic. However it is possible for an ...
[32]
[PDF] Chapter 10 – Digital-Analog and Analog-Digital Converters
Feb 25, 2003 · Voltage-Scaling, Charge-Scaling Successive Approximation ADC - Continued. Autozero Step. Removes the influence of the offset voltage of the.
[33]
[PDF] MT-007 Tutorial - Analog Devices
ADCs are currently available with typical aperture jitter specifications of 60-fs rms (AD9445 14-bits @ 125 MSPS and AD9446 16-bits @ 100 MSPS).
[34]
[PDF] High-Speed Successive Approximation Register (SAR) ADC Design ...
Aug 6, 2019 · 3 Charge injection. During sampling, the electrons are accumulated in the transistor channel and those electrons cannot spread instantaneously, ...
[35]
[PDF] SAR ADCs for PLC Applications - Texas Instruments
Feb 24, 2016 · To support and control next generation machinery, the programmable logic controller (PLC) must be capable of quickly and accurately receiving ...
[36]
[PDF] Parallel-sampling ADC architecture for power-efficient broadband ...
Dec 9, 2014 · SAR ADC with a parallel-sampling frontend stage, which targets wideband direct sampling receivers for DOCSIS 3.0 cable modems [3]. The ...
[37]
A Design of 20MS/s 12-bit Charge Sharing SAR ADC for Ultrasound Diagnostic Medical Devices
- **SAR ADC for Ultrasound Imaging**: The paper presents a design of a 12-bit Charge Sharing Successive Approximation Register (SAR) ADC specifically for ultrasound diagnostic medical devices.
[38]
Design and simulate analog to digital converter and ... - Virtual Labs
This type of equipment uses successive-approximation register (SAR). A digital multimeter (DMM) needs fine resolution and can sacrifice high measurement speeds.
[39]
A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ...
The ADC achieves both high speed and low power by combining several features, namely digital calibration, redundancy, asynchronous bit-cycling, monotonic ...
[40]
A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ...
Huang Q. et al. A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ADC With Eased Driving Burden // IEEE Journal of Solid-State Circuits. 2025. Vol. 60.
[41]
TI debuts new automotive chips at CES, enabling automakers to ...
Jan 8, 2024 · The industry's first single-chip radar sensor designed for satellite architectures can increase vehicle sensing ranges beyond 200 meters and ...
[42]
AWR2944 data sheet, product information and support | TI.com
TI's AWR2944 is a Automotive, second-generation 76-GHz to 81-GHz high-performance SoC for corner and long-range radar. Find parameters, ordering and quality ...
[43]
(PDF) A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power ...
May 20, 2020 · A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications. May 2020. Authors:.
[44]
(PDF) A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power ...
The proposed SAR ADC achieves a FoM of 8 fJ/conversion-step at 8 MS/s. It utilizes a 55 nm CMOS process, occupying an area of 362 µm x 524 µm. A modified ...<|separator|>
[45]
A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ...
This paper presents a multi-comparator SAR ADC featuring noise scaling on the comparators, and is the first reported single channel> 10 ENOB SAR ADC to ...Missing: IoT | Show results with:IoT
[46]
A Cryogenic 8-Bit 32 MS/s SAR ADC Operating down to 4.2 K - MDPI
Mar 16, 2023 · This paper presents a cryogenic 8-bit 32 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) which operates down to 4.2 K.3. Cryogenic Sar Adc · 3.1. Adc Architecture · 3.4. Sar Logic And Capacitor...Missing: growth | Show results with:growth
[47]
ADC & DAC In Quantum Computing Market Size Report 2030
The global ADC & DAC in quantum computing market size was estimated at USD 36,803.3 thousand in 2024 and is projected to reach USD 206,635.0 thousand by 2030, ...
[48]
How analog sensors work in an edge AI digital world
Oct 15, 2025 · And yes, there are so-called digital sensors that contain an integrated ADC, which converts the continuous analog signal into a digital value.Missing: SAR 2020s
[49]
A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient ...
Dec 15, 2023 · A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications.Missing: activity | Show results with:activity
[50]
[PDF] Energy-efficient and high-resolution switching scheme based on ...
Jun 27, 2022 · The proposed scheme in this paper can achieve 25% savings in switching energy compared to the Tri-level switching scheme, and reduce the ...
[51]
A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching ...
Dec 27, 2023 · This paper proposed a hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications. The ...