Fact-checked by Grok 2 weeks ago

Equivalent oxide thickness

Equivalent oxide thickness (EOT) is a fundamental metric in semiconductor physics that quantifies the effective electrical thickness of gate dielectrics in metal-oxide-semiconductor field-effect transistors (MOSFETs) by normalizing their capacitance to that of silicon dioxide (SiO₂). It represents the hypothetical thickness of an SiO₂ layer (with dielectric constant ε_SiO₂ ≈ 3.9) that would produce the same gate capacitance per unit area as the actual dielectric stack, typically comprising a high-k material and an interfacial layer. For a single high-k layer, EOT is calculated as EOT = t_phys × (ε_SiO₂ / ε_high-k), where t_phys is the physical thickness and ε_high-k is the dielectric constant of the high-k material; in practical stacks, it accounts for series capacitances as EOT = EOT_IL + (ε_SiO₂ / ε_high-k) × t_high-k.^[1] This concept is essential for advancing complementary metal-oxide-semiconductor (CMOS) technology, enabling the continued scaling of transistor dimensions while mitigating quantum tunneling leakage currents that plague ultra-thin SiO₂ layers below 2 nm. By employing high-k dielectrics (ε > 9, such as HfO₂ or ZrO₂), device engineers can maintain high gate capacitance with thicker physical layers, improving power efficiency and performance in integrated circuits. EOT scaling directly influences key parameters like drive current, threshold voltage, and subthreshold swing, making it a cornerstone for meeting the demands of Moore's Law in very-large-scale integration (VLSI).^[2] The adoption of EOT as a standard metric emerged in the early 2000s amid the limitations of SiO₂/SiON gate stacks, which suffered excessive leakage at thicknesses approaching 1 nm around the 90 nm technology node. High-k dielectrics were first integrated into dynamic random-access memory (DRAM) capacitors between 2001 and 2003, followed by logic CMOS in 2007 when Intel introduced hafnium-based high-k/metal gate (HKMG) stacks at the 45 nm node, achieving an EOT of approximately 1.0 nm. This transition marked a pivotal shift, allowing EOT reduction from ~1.2 nm (SiON at 65 nm) to sub-1.2 nm regimes, with materials like HfO₂ (ε ≈ 20–25) enabling physical thicknesses of 2–3 nm for equivalent performance.^[2] Despite these advances, EOT scaling faces significant challenges, including the persistent interfacial layer (IL) between the high-k dielectric and silicon channel, which adds ~0.4–0.5 nm to EOT and degrades carrier mobility due to defects and remote scattering. Quantum mechanical effects, thermal stability, and compatibility with high-mobility channels (e.g., Ge or III-V semiconductors) further complicate sub-1 nm EOT targets required for nodes below 5 nm. Recent innovations, such as IL scavenging via lanthanum diffusion and higher-k materials like La₂O₃ (ε > 30), have pushed boundaries, with demonstrations of EOT values as low as 0.42 nm in lab settings as early as 2009.^[3] As of 2025, ongoing research has achieved sub-1 nm EOT in emerging devices, including 0.86 nm with ZrO₂ on monolayer MoS₂ for 2D transistors and 1-nm-scale top-gate dielectrics on transition metal dichalcogenides (TMDs) using CMOS-compatible processes. Superlattice structures like HfO₂-ZrO₂ stacks and novel dielectrics such as MoO₃ have enabled EOT below 1 nm with low leakage, supporting applications in flexible electronics, FinFETs, and gate-all-around (GAA) architectures for beyond-3 nm nodes. These developments underscore EOT's role in sustaining transistor innovation amid physical scaling limits.^[4]^[5]^[6]

Fundamentals

Definition and Importance

Equivalent oxide thickness (EOT) is defined as the hypothetical thickness of a silicon dioxide (SiO₂) layer that would produce the same gate capacitance per unit area as the actual dielectric material used in a metal-oxide-semiconductor field-effect transistor (MOSFET).^[7] This metric normalizes the performance of various gate dielectrics to a standard reference, facilitating direct comparisons across materials.^[1] In MOSFETs, gate capacitance arises from the parallel-plate capacitor formed by the gate electrode, dielectric layer, and channel, governed by the relation C = \epsilon A / d, where C is capacitance, \epsilon is the permittivity of the dielectric, A is the gate area, and d is the physical thickness.^[8] Silicon dioxide, with a relative permittivity \epsilon_r = 3.9, serves as the benchmark because it was the traditional gate dielectric; EOT thus scales the effective thickness of alternative materials relative to SiO₂ to maintain equivalent capacitance.^[8] The importance of EOT lies in its role for continued transistor scaling under Moore's Law, where shrinking dimensions demand higher gate capacitance to control the channel effectively while minimizing power consumption. As SiO₂ thicknesses approach ~1 nm, quantum tunneling causes excessive gate leakage current, rendering further direct scaling impractical and limiting device performance.^[9] EOT enables the adoption of high-κ dielectrics, such as hafnium oxide (HfO₂) with \epsilon_r \approx 25, which achieve the same capacitance with thicker physical layers to suppress tunneling, thereby reducing leakage while supporting aggressive scaling.^[10] In modern semiconductor nodes, such as the 5 nm process, EOT values below 1 nm (e.g., ~0.8 nm) are targeted to sustain these benefits.^[11]

Capacitance Relation

The capacitance of a gate dielectric in a metal-oxide-semiconductor (MOS) structure is modeled using the parallel-plate capacitor approximation, where the oxide capacitance C_{\text{ox}} is given by

C_{\text{ox}} = \frac{\epsilon_0 \epsilon_r A}{t_{\text{phys}}},

with \epsilon_0 as the vacuum permittivity, \epsilon_r as the relative permittivity of the dielectric material, A as the gate area, and t_{\text{phys}} as the physical thickness of the dielectric.^[12]^[13] Equivalent oxide thickness (EOT, denoted t_{\text{EOT}}) is defined to normalize the capacitance of alternative dielectrics to that of silicon dioxide (SiO₂), such that the same capacitance is achieved as if a SiO₂ layer of thickness t_{\text{EOT}} were used:

C_{\text{ox}} = \frac{\epsilon_0 \epsilon_{\text{SiO}_2} A}{t_{\text{EOT}}},

where \epsilon_{\text{SiO}_2} = 3.9 is the relative permittivity of SiO₂.^[12]^[13] Equating the two expressions for C_{\text{ox}} yields the core relation

t_{\text{EOT}} = \left( \frac{\epsilon_{\text{SiO}_2}}{\epsilon_r} \right) t_{\text{phys}}.

This normalization enables direct comparison of high-\kappa dielectrics (where \kappa denotes \epsilon_r > 3.9) to SiO₂, ensuring equivalent capacitive performance at a reduced physical thickness to mitigate quantum tunneling leakage.^[12] The relation assumes a uniform dielectric with constant \epsilon_r, which facilitates scaling in MOS field-effect transistors (MOSFETs) by allowing thicker physical layers for the same effective capacitance.^[12] For instance, hafnium dioxide (HfO₂), a common high-\kappa material with \epsilon_r \approx 25, at a physical thickness of 2 nm yields t_{\text{EOT}} \approx 0.31 nm, equivalent to the capacitance of a 0.31 nm SiO₂ layer.^[12]^[14] Quantum mechanical effects, such as carrier confinement in the semiconductor channel, introduce a charge centroid shift that reduces the effective gate capacitance, effectively increasing the perceived EOT beyond the classical value; these effects are influenced by the dielectric's bandgap, which governs band offsets and confinement energy.^[15]^[16]

Calculation

Basic Formula

The basic formula for equivalent oxide thickness (EOT) in single-layer high-κ dielectrics is given by

t_{\text{EOT}} = \frac{\varepsilon_{\text{SiO}_2}}{\varepsilon_d} \cdot t_{\text{phys}} + t_{\text{IL}},

where \varepsilon_{\text{SiO}_2} \approx 3.9 is the relative permittivity of SiO₂, \varepsilon_d is the relative permittivity of the dielectric material, t_{\text{phys}} is the physical thickness of the dielectric layer, and t_{\text{IL}} accounts for any thin interfacial SiO₂ layer (often negligible, on the order of 0.3–0.5 nm or less in optimized processes).^[8] This expression derives from equating the capacitance of the high-κ stack to that of an equivalent SiO₂ layer under the parallel-plate capacitor model, C = \varepsilon_0 \varepsilon_r A / t, where the EOT represents the SiO₂ thickness yielding the same C.^[8] The formula assumes an ideal parallel-plate geometry with uniform electric field distribution, a constant and isotropic dielectric permittivity \varepsilon_d throughout the layer, and neglects edge or fringe field effects that may arise in finite device geometries.^[17] These assumptions hold well for planar, macroscopic capacitors but simplify real nanoscale structures where field non-uniformities can occur.^[17] Key limitations include the requirement for a precisely known \varepsilon_d, which can vary with deposition conditions, crystallinity, and composition (e.g., 20–25 for ZrO₂ depending on phase).^[18] Additionally, the formula does not inherently account for inaccuracies from poly-Si gate depletion, which effectively increases the apparent EOT by 0.3–0.5 nm due to reduced gate capacitance from carrier depletion in the polysilicon, or from metal gate quantum effects, both of which are typically quantified via separate corrections in device modeling.^[19]^[8] For example, consider a 3 nm physical thickness of ZrO₂ (\varepsilon_d = 20–25) with negligible t_{\text{IL}}. Using \varepsilon_d = 20, first compute the scaling factor: \varepsilon_{\text{SiO}_2} / \varepsilon_d = 3.9 / 20 = 0.195. Then, t_{\text{EOT}} = 0.195 \times 3 = 0.585 nm, approximately 0.6 nm, demonstrating how high-κ materials enable thinner physical layers while maintaining sub-1 nm EOT for improved gate control.^[18]

Extensions for Complex Structures

In real-world semiconductor devices, gate dielectrics often consist of multi-layer stacks to optimize performance, such as combining high-κ materials like HfO₂ with a thin SiO₂ interfacial layer for better interface quality. The equivalent oxide thickness (EOT) for such stacks is calculated by summing the contributions from each layer, weighted by their relative permittivities compared to SiO₂ (ε_SiO₂ = 3.9). The generalized formula is:

t_{\text{EOT}} = \sum_i \frac{\varepsilon_{\text{SiO}_2}}{\varepsilon_i} t_i

where t_i is the physical thickness and \varepsilon_i is the permittivity of the i-th layer.^[20] This approach assumes a series capacitance model and neglects non-ideal effects initially. Non-ideal effects in advanced nodes require further extensions to the EOT formula. Interfacial layers often exhibit fixed charges or electric dipoles at the high-κ/SiO₂ or SiO₂/Si interfaces, which shift the flatband voltage and necessitate corrections in capacitance-voltage (C-V) analysis to accurately extract EOT. These effects can arise from process-induced defects or intentional doping, altering the effective electric field across the stack. Additionally, quantum mechanical effects, such as the shift of the inversion charge centroid away from the semiconductor interface, reduce the effective gate capacitance, adding approximately 0.3 nm to the EOT in ultra-thin regimes (below 2 nm physical thickness). This correction accounts for the wavefunction penetration into the channel, becoming more pronounced as scaling pushes toward sub-1 nm EOT targets. Specific non-ideal contributions include the poly-depletion equivalent thickness (PDE) in polysilicon-gated structures, where band bending in the depleted gate electrode effectively thickens the dielectric by about 0.4 nm at inversion, reducing drive current and capacitance.^[21] Transitioning to metal gates mitigates PDE but introduces work function variations across the stack (typically 0.1–0.5 eV depending on metal composition and interface dipoles), which can indirectly affect EOT extraction by altering band offsets and charge distribution, requiring separate calibration in C-V modeling. As an illustrative example, consider a dual-layer stack of 2 nm HfO₂ (ε ≈ 25) on 1 nm SiO₂. Applying the multi-layer formula yields:

t_{\text{EOT}} = \frac{3.9}{25} \times 2 + 1 \approx 0.31 + 1 = 1.31~\text{nm}.

This demonstrates how high-κ layers enable thinner physical thicknesses while maintaining a target EOT, though quantum and interfacial corrections could increase the effective value by 0.3–0.5 nm in practice.^[20]

Measurement Methods

Electrical Characterization

Electrical characterization of equivalent oxide thickness (EOT) primarily relies on capacitance-voltage (C-V) profiling performed on metal-oxide-semiconductor (MOS) capacitors, which directly measures the effective capacitance of the gate dielectric stack to infer EOT.^[22] In this method, the maximum accumulation capacitance, C_{\text{ox,max}}, is obtained from the high-frequency C-V curve, and EOT is calculated using the relation t_{\text{EOT}} = \frac{\epsilon_{\text{SiO}_2} A}{C_{\text{ox,max}}}, where \epsilon_{\text{SiO}_2} is the permittivity of SiO_2 (approximately $3.45 \times 10^{-13} F/cm) and A is the gate area.^[22] This approach provides an electrical measure of the dielectric's effectiveness, accounting for the total capacitive contribution including any interfacial layers or high-k materials scaled to an equivalent SiO_2 thickness.^[23] The procedure involves fabricating MOS capacitors with the dielectric stack and applying a DC bias sweep while superimposing a small AC signal (typically 10-50 mV at 1 MHz) to measure capacitance. High-frequency C-V curves are preferred to minimize minority carrier response in inversion, ensuring accurate C_{\text{ox,max}} extraction in strong accumulation.^[23] Corrections are essential for quantum mechanical effects, which reduce effective capacitance by shifting carrier centroids into the silicon (adding ~0.3-0.5 nm to EOT), modeled using formulations like van Dort's bandgap widening; series resistance from gate, substrate, and contacts (often 1-5 kΩ) is compensated via equivalent circuit models or multi-frequency measurements.^[23] To validate results, linearity checks are performed by fabricating capacitors with varying oxide thicknesses and plotting EOT against physical thickness, confirming a constant intercept for interfacial contributions.^[22] Instruments such as the Keithley 4200-SCS Parameter Analyzer with CVU option are commonly used for precise automated sweeps and data acquisition, supporting frequencies up to 5 MHz and bias ranges suitable for ultrathin dielectrics.^[24] This method achieves accuracy of ±0.1 nm for EOT values down to ~1 nm, limited by noise, area uniformity, and correction precision.^[25] However, for sub-1 nm EOT regimes, challenges arise from exponential gate leakage currents due to direct tunneling, which distort C-V curves and require simultaneous current-voltage (I-V) modeling for correction.^[23] A representative example from 45 nm technology node devices shows C_{\text{ox}} = 3.45 \, \mu\text{F/cm}^2 yielding t_{\text{EOT}} \approx 1.0 nm, enabling gate lengths around 35 nm while maintaining control over short-channel effects.^[26] Recent advancements as of 2025 include a rapid capacitance measurement method using an in-plane electrode structure for atomically thin high-k films like ZrO₂ in 2D transistors. This approach employs a two-frequency model and equivalent circuit to eliminate series resistance and parasitic effects, allowing direct extraction of dielectric constants and EOT without frequency dispersion. Key steps involve fabricating capacitors on SiO₂ substrates with aluminum electrodes, depositing ZrO₂ via atomic layer deposition (3–5 nm thick) followed by atomic layer etching, and measuring capacitance after calibration with an impedance standard. It offers advantages over traditional MOS C-V methods by simplifying fabrication (no bottom contacts needed), enabling mass measurements, and providing faster feedback for ultrathin films, with reported dielectric constants of 31 for etched ZrO₂ (yielding sub-1 nm EOT) compared to 15.3 for as-deposited films.^[27]

Spectroscopic Techniques

Spectroscopic ellipsometry serves as a primary non-electrical technique for assessing equivalent oxide thickness (EOT) in high-k dielectrics by determining the refractive index n and extinction coefficient k, from which the relative permittivity \epsilon_r is approximated as \epsilon_r \approx n^2 - k^2 in the optical frequency range.^[28] This optical \epsilon_r is then combined with the physical thickness t_\mathrm{phys}, often measured via transmission electron microscopy (TEM), to compute EOT using the relation t_\mathrm{EOT} = t_\mathrm{phys} \times 3.9 / \epsilon_r, where 3.9 is the permittivity of SiO_2.^[29] The method offers sub-nanometer resolution, typically around 0.1 nm for ultrathin films, enabling precise characterization before device fabrication due to its non-destructive nature.^[30] However, limitations arise in distinguishing amorphous from crystalline phases, as the latter may exhibit anisotropic optical properties requiring advanced modeling, and the optical \epsilon_r can deviate from the static value used in EOT for device performance.^[31] For example, in atomic layer deposition (ALD) of HfO_2, spectroscopic ellipsometry typically yields \epsilon_r \approx 20, and when paired with TEM-measured t_\mathrm{phys} = 2.5 nm, results in t_\mathrm{EOT} \approx 0.5 nm, demonstrating effective scaling for gate dielectrics.^[32] Complementary spectroscopic methods include X-ray reflectometry (XRR), which probes film density, roughness, and thickness through interference fringes, providing t_\mathrm{phys} data to support EOT estimation when combined with permittivity measurements from ellipsometry.^[33] Atomic force microscopy (AFM) aids in surface profiling to quantify roughness, which indirectly influences effective permittivity in high-k stacks.^[34] Secondary ion mass spectrometry (SIMS) analyzes layer composition and interfacial impurities, helping refine \epsilon_r models by identifying variations in material stoichiometry that affect dielectric properties.^[34] These techniques collectively enable material-level validation of EOT prior to electrical testing.

Applications in Devices

Gate Dielectrics in MOSFETs

In metal-oxide-semiconductor field-effect transistors (MOSFETs), the equivalent oxide thickness (EOT) plays a critical role in scaling device dimensions while maintaining effective gate control over the channel. Reducing EOT enhances the gate capacitance, which strengthens electrostatic control and suppresses short-channel effects such as drain-induced barrier lowering and threshold voltage roll-off, allowing for shorter channel lengths without significant performance degradation.^[35] This scaling capability is essential for advancing technology nodes, with industry roadmaps targeting EOT values below 0.7 nm to support 3 nm nodes and beyond, enabling continued transistor density increases while preserving subthreshold swing and on-state drive.^[36] Lower EOT directly improves key performance metrics in MOSFETs, including transconductance (g_m), which is proportional to gate capacitance and thus rises with EOT reduction, leading to higher drive currents and faster switching speeds. Additionally, thinner EOT mitigates threshold voltage (V_{th}) variability arising from work-function fluctuations or random dopant effects, as the stronger gate coupling averages out local nonuniformities across the channel. However, this comes with trade-offs: gate leakage current density (J_g) increases exponentially with decreasing EOT due to enhanced quantum tunneling through the thinner effective barrier, often following a relation J_g \propto \exp(-t_{EOT}), necessitating careful material selection to balance leakage and performance.^[37]^[38]^[39] In production MOSFETs like FinFETs, optimized high-κ/metal gate stacks have achieved EOT around 0.8 nm at advanced nodes such as 14 nm and below, improving gate control in three-dimensional channels and supporting higher drive currents in bulk and partially depleted silicon-on-insulator devices.^[26]^[40]^[41] The impact of EOT on drive current (I_{on}) is particularly evident in performance benchmarks, where reductions in EOT correlate with substantial gains in on-state current. For instance, simulations and experimental data show that a 0.1 nm decrease in EOT can boost I_{on} by approximately 10-15% in scaled MOSFETs, primarily through increased inversion charge density and enhanced transconductance, as illustrated in typical EOT-I_{on} trends for high-κ gate stacks. This relationship underscores EOT's leverage in optimizing speed-power trade-offs, though it must be balanced against reliability concerns like time-dependent dielectric breakdown at ultra-thin limits.^[42] Beyond logic transistors, EOT scaling is crucial in dynamic random-access memory (DRAM) capacitors, where high-k materials enable larger capacitance in scaled geometries without excessive leakage, as first demonstrated in production between 2001 and 2003.^[2]

Emerging Nanoscale Devices

In gate-all-around (GAA) transistors, equivalent oxide thickness (EOT) plays a critical role in enhancing multi-gate electrostatic control, enabling superior short-channel effect suppression and improved subthreshold swing compared to planar structures.^[43] Achieving EOT values below 0.5 nm is a key target for GAA devices, particularly when integrating 2D dielectrics such as hexagonal boron nitride (h-BN), which provides atomically smooth interfaces and low defect densities to minimize leakage while maintaining high capacitance.^[44] Beyond traditional architectures, ferroelectric dielectrics like HfZrO enable negative capacitance effects that effectively reduce EOT by amplifying the internal electric field in the gate stack, allowing steeper subthreshold slopes below the 60 mV/dec Boltzmann limit.^[45] In tunnel field-effect transistors (TFETs), low EOT values enhance gate-induced band bending, optimizing band alignment at the source-channel junction to boost band-to-band tunneling probability and on-current density.^[46] Projections for the 2 nm technology node and beyond (2025+) anticipate EOT scaling to approximately 0.4 nm through stacked high-k configurations, such as HfO₂/HfZrO multilayers, to support continued dimensional shrinkage.^[47] However, realizing such ultrathin EOT introduces challenges in maintaining atomic-scale uniformity, including interface trap density control and defect mitigation to prevent reliability degradation.^[48] A representative example is in MoS₂-based field-effect transistors, where h-BN as a gate dielectric or in encapsulation with high-k stacks has enabled sub-0.5 nm EOT, resulting in a mobility enhancement of over 50% due to reduced scattering and improved gate modulation.^[44]

Historical Development

Pre-High-k Era

Silicon dioxide (SiO₂) served as the dominant gate dielectric material in metal-oxide-semiconductor field-effect transistors (MOSFETs) from the 1960s through the early 2000s, enabling the exponential scaling of transistor dimensions in accordance with Moore's Law.^[49] The first practical MOSFET, demonstrated in 1960 by Mohamed Atalla and Dawon Kahng at Bell Labs, utilized thermally grown SiO₂ as the insulator, with initial thicknesses around 100 nm that provided excellent electrical isolation and interface properties with silicon.^[49] Over subsequent decades, aggressive scaling reduced the physical thickness of SiO₂ to maintain gate capacitance for improved performance and density, reaching approximately 1.8 nm by the 130 nm technology node in 2001, where the equivalent oxide thickness (EOT) closely approximated the physical thickness due to the material's relative permittivity (ε_r) of 3.9, and further scaled to 1.2 nm by the 90 nm node in 2004.^[50]^[51] This scaling trajectory, driven by the need to control short-channel effects and boost drive currents in CMOS devices, encountered fundamental physical limits as thicknesses approached atomic scales. Below 1.5 nm, direct tunneling through the SiO₂ barrier became dominant, resulting in significant gate leakage currents, exceeding 10 A/cm² at typical operating voltages around 1 V, which compromised power efficiency and standby leakage in integrated circuits.^[52] Reliability concerns further intensified, including soft breakdown phenomena where localized defects led to progressive degradation under stress, limiting the operational lifetime of devices to below required 10-year benchmarks for thicknesses under 1.5–2 nm.^[51] The 90 nm node, introduced in 2004, marked the effective end of pure SiO₂ usage in high-performance logic, as tunneling and reliability issues rendered further pure SiO₂ scaling untenable without alternative approaches.^[50] To extend SiO₂-based dielectrics modestly beyond these limits, nitridation was introduced in the late 1990s and early 2000s, forming silicon oxynitride (SiON) films that incorporated nitrogen at the Si-SiO₂ interface or throughout the layer. This modification increased the effective dielectric constant to approximately 4.5, depending on nitrogen concentration, allowing a 10–20% reduction in EOT for equivalent physical thicknesses compared to pure SiO₂, thereby mitigating tunneling leakage while preserving capacitance.^[53] SiON's higher permittivity stemmed from the partial replacement of oxygen with nitrogen, which also enhanced resistance to boron penetration in p-channel devices and improved overall thermal stability during processing.^[49] By the 90 nm node, heavily nitrided SiON became standard, representing a transitional strategy that delayed the full adoption of high-k materials while addressing the immediate scaling challenges of SiO₂.^[49]

High-k Integration Milestones

The integration of high-k dielectrics began gaining traction in the early 2000s as a means to scale gate oxides beyond the physical limits of SiO₂ while maintaining low leakage currents. High-k dielectrics were first commercially adopted in dynamic random-access memory (DRAM) capacitors around 2001–2003. A pivotal early demonstration came in 2001 when researchers at IBM showcased HfO₂ as a promising high-k material, achieving effective electrical properties suitable for gate dielectrics through atomic layer deposition (ALD), which highlighted its potential dielectric constant of approximately 25 compared to SiO₂'s 3.9. This work laid the groundwork for replacing traditional SiO₂ with materials offering higher permittivity to enable thinner equivalent oxide thickness (EOT) without excessive tunneling. By 2007, Intel advanced this to production scale in their 45 nm node, employing HfSiON as the high-k dielectric with an EOT of 1.0 nm, integrated alongside metal gates to deliver enhanced performance and reduced gate leakage in high-volume CMOS manufacturing.^[54]^[55] Subsequent milestones focused on architectural innovations and further EOT scaling to support denser transistors. In 2011, Intel's introduction of 22 nm tri-gate (FinFET) technology incorporated advanced high-k/metal gate stacks, achieving an EOT of approximately 0.9 nm, which improved channel control, boosted drive currents by up to 20% at low voltages, and reduced leakage compared to planar designs. This tri-gate structure, with the high-k dielectric wrapping three sides of the silicon fin, marked a significant step in 3D transistor scaling. By 2017, Intel's 10 nm node refined this approach with second-generation high-k materials and metal gates, attaining an EOT around 0.7 nm, enabling 2.7 times higher transistor density over prior nodes while maintaining power efficiency through optimized FinFET dimensions and cobalt interconnects. In 2022, Samsung rolled out its 3 nm gate-all-around (GAA) nanosheet process, while TSMC employed FinFET for its 3 nm node, leveraging high-k dielectrics to reach EOT values near 0.5 nm, which enhanced electrostatic integrity in multi-wire channels and supported 16-23% area reductions over 5 nm nodes.^[56]^[48] Key challenges in high-k integration included ensuring thermal stability during high-temperature processing and minimizing interface traps that degrade mobility and reliability. Early high-k materials like HfO₂ suffered from crystallization at temperatures above 500°C, leading to increased leakage; this was addressed through nitrogen incorporation (e.g., HfSiON) and ALD techniques that provided conformal, uniform films as thin as 1-2 nm with controlled stoichiometry. Interface traps at the high-k/SiO₂ interlayer, often exceeding 10^12 cm^-2 eV^-1, were mitigated via optimized interfacial layers and post-deposition anneals, reducing defect densities to below 10^11 cm^-2 eV^-1 and preserving carrier mobilities above 80% of universal values. ALD emerged as the dominant deposition method for its precision in achieving sub-nm uniformity and scalability across complex 3D structures like fins and nanosheets.^[57] Looking toward 2025 and beyond, projections for the 1.4 nm node emphasize exotic high-k materials with relative permittivities (ε_r) exceeding 30, such as La₂O₃ (ε_r ≈ 27), to achieve EOT below 0.4 nm while combating quantum tunneling. These advancements aim to support continued scaling in GAA and emerging stacked nanosheet designs, with ALD variants enabling integration of ultrathin layers (0.5-1 nm physical thickness). Post-2022 developments have also spotlighted 2D high-k dielectrics, including van der Waals materials like GdOCl and layered oxides, which offer trap densities under 10^11 cm^-2 eV^-1 and EOT as low as 0.5 nm in 2D channel devices, addressing interface issues in sub-3 nm regimes.^[58]^[59]^[60]^[61]

References

[1]
Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial ...
Current status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of high-κ gate dielectrics via higher-κ (>20) materials and interfacial ...
[2]
Emerging Applications for High K Materials in VLSI Technology - NIH
Thus the EOT is the thickness of SiO2 that would give an equivalent capacitance in accumulation to the device being measured, and is generally accepted as the “ ...
[3]
Controllable growth of MoO3 dielectrics with sub-1 nm equivalent ...
Jul 22, 2025 · The key challenge lies in developing an ultra-thin high-κ dielectric with damage-free interface and sub-1 nm equivalent oxide thickness (EOT) ...
[4]
https://www.nature.com/articles/s41467-025-61972-y
[5]
A clean van der Waals interface between the high-k dielectric ...
Oct 6, 2025 · ... equivalent oxide thickness of 0.86 nm and subthreshold swing values of 80 mV dec−1. The clean interface between ZrO2 and monolayer MoS2 ...
[6]
Gate stack technology for nanoscale devices - ScienceDirect.com
Recently, however, the thickness of the gate oxide has scaled more slowly than the historical pace. An equivalent oxide thickness (EOT) of ∼1 nm has been ...
[7]
High dielectric constant oxides
Here 3.9 is the static dielectric constant of SiO2. The ob- jective is to develop high K oxides which allow scaling to continue to ever lower values of EOT. The ...
[8]
[PDF] The relentless march of the MOSFET gate oxide thickness to zero
In what follows, we show that gate leakage current due to direct tunneling through the gate oxide will render SiO2 thicknesses less than 1.3 nm impractical. [1] ...
[9]
Hafnium-Based High-k Gate Dielectrics - ResearchGate
The dielectric constant, k for Hf O 2 is 25 which is around 6 times greater than that of commonly used SiO 2 [14] . For better performance of GFETs, high ...
[10]
ASAP5: A predictive PDK for the 5 nm node - ScienceDirect.com
A 0.6 nm thick native SiO2 layer separates it from the Si channel. This results in a 0.78 nm equivalent oxide thickness (EOT), which is approximately the EOT ...
[11]
High-κ gate dielectrics: Current status and materials properties ...
May 15, 2001 · High-κ gate dielectrics: Current status and materials properties considerations Available. G. D. Wilk;.
[12]
https://pubs.aip.org/aip/jap/article/89/10/5243/291412/High-gate-dielectrics-Current-status-and-materials
[13]
[PDF] K K HfO2 Gate Dielectrics
HfO2 has a high dielectric constant (25) and a large band gap (5.68eV). Its capacitance density is 11.6 fF/m2, and leakage current is 3.09 10-6A/cm2 at -1.5V.
[14]
https://www.electrochem.org/dl/ma/201/pdfs/0354.pdf
[15]
Fundamental understanding of quantum confinement effect on gate ...
Dec 17, 2024 · Our findings reveal that the QCE reduces both the carrier density at the channel interface and the electric field in the gate oxide, thereby ...
[16]
https://pubs.aip.org/aip/jap/article/136/23/235701/3326486/Fundamental-understanding-of-quantum-confinement
[17]
Structure and Dielectric Property of High-k ZrO2 Films Grown ... - NIH
May 7, 2019 · The relative permittivity measured at 10 kHz was 20–24 in the films deposited at 275–325 °C [20]. Kukli et al. reported that ZrO2 films were ...
[18]
challenges of electrical measurements of advanced gate dielectrics ...
The EOT must be determined from C-V measurements using a fitting or extraction algorithm that includes quantum mechanical effects, polysilicon depletion, etc.
[19]
https://pubs.aip.org/aip/acp/article-pdf/683/1/771/12053229/771_1_online.pdf
[20]
[PDF] Nanoscale CMOS Modeling - UC Berkeley EECS
Mar 3, 2008 · at inversion by ≈ 0.4nm which is significant for scaled transistors. ... in MG-FETs such as the poly-depletion effect (PDE) and the quantum ...
[21]
[PDF] MOS Capacitor
FIGURE 5–21 Measured Vfb of three capacitors with different oxide thicknesses. SOLUTION: (5.7.1). Equation (5.7.1) suggests that Vfb at Tox = 0 ...
[22]
https://www.chu.berkeley.edu/wp-content/uploads/2020/01/Chenming-Hu_ch5-1.pdf
[23]
C-V Testing for Semiconductor Components and Devices - Tektronix
This application note discusses how to use a Keithley Model 4200-SCS Parameter Analyzer equipped with the Model 4200-CVU Integrated CV Option to make CV ...Missing: EOT | Show results with:EOT
[24]
[PDF] Interface Characterization of Metal-Gate MOS-Structures
Jun 17, 2002 · determined with an accuracy of 0.1 nm. Thickness uniformity is ... 2.6: Minimum oxide thickness of an SOS-capacitor, which can be determined with ...
[25]
[PDF] A 45nm Logic Technology with High-k + Metal Gate Transistors ...
• 35 nm min. gate length. • 160 nm contacted gate pitch. • 1.0 nm EOT Hi-K. • Dual workfunction metal gate electrodes. • 3RD generation of strained silicon ...
[26]
[PDF] Optical dielectric properties of HfO2-based films
Thus, the real dielectric permittivity εr can be esti- mated by the value of n by εr % n2. We thus estimate the refractive indices in the measured wavelength ...
[27]
Comparison of the effective oxide thickness determined by ...
Ellipsometric results may be inaccurate for the measured thickness of ultrathin oxide films on silicon because of the apparent refractive index changes with ...Missing: equivalent | Show results with:equivalent
[28]
Refractive Index and Thickness Analysis of Natural Silicon Dioxide ...
Oct 1, 2006 · Moreover, the ellipsometric technique has been the most sensitive to oxide thickness as thin as 2 nm or less. When films are very thin, the ...
[29]
What are the limitations of Ellipsometry for dielectric constant ...
Feb 3, 2022 · The difference is related to frequency range you consider. Ellipsometry and refractive index most often relates to optics, obviously, and thus ...
[30]
Non-linear dielectric constant increase with Ti composition in high-k ...
The as-deposited films show a linear increase of dielec- tric constant from 20 (HfO2) to 40 (TiO2) as a function of Ti content in the film. On the other hands, ...
[31]
[PDF] High-k Dielectric Stacks for Integration into an Advanced CMOS ...
gate insulator cannot meet the time to breakdown requirements for the 45nm technology node which requires an EOT of 1.4nm. The predictions made by. 9. Page 25 ...
[32]
Correlation of interfacial and dielectric characteristics in atomic layer ...
Sep 5, 2023 · The combined results from XRR, GIXRF, SIMS, and AFM studies clearly indicates that the structural and interface properties of ATA NL-4 s are ...
[33]
Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0 ...
The high-k gate dielectric can reduce leakage current through a thick physical dimension while keeping an equivalent oxide thickness (EOT). Recently, using ...Missing: definition | Show results with:definition
[34]
Recent Experimental Breakthroughs on 2D Transistors ...
Apr 12, 2024 · The IRDS requires a CET of 1–0.9 nm (summary of the EOT (= 3.9tox/εox, ≈0.5 nm) for a technology node of 3 nm and afterward. A high-κ ...
[35]
Boosting transconductance in indium gallium arsenide finFETs
Sep 2, 2016 · In particular, transconductance increased with reduced gate length, while EOT reduction gave increased transconductance, threshold voltage ...
[36]
Impact of Equivalent Oxide Thickness on Threshold Voltage ...
Using 3-D technology computer aided design simulation, we investigated the impact of equivalent oxide thickness (EOT) on threshold voltage (VTH) variation ...
[37]
[PDF] High-k Oxides on Si: MOSFET Gate Dielectrics - Sci-Hub BOX
Scalability of high-k materials is often evaluated with a metrics called equivalent oxide thickness (EOT), which represents the theoretical thickness of SiO2 ...
[38]
Ultrathin EOT high- κ/metal gate devices for future technologies
Aug 7, 2025 · ... Besides that, HfO 2 dielectric-based FET technology enable down scaling of EOT to 0.8 nm in recent device [9]. Nevertheless, even if EOT ...
[39]
Analog Performance and its Variability in Sub-10 nm Fin-Width ...
Dec 6, 2019 · 1. These FinFETs have an EOT of ∼0.8nm. The final gate stack is fabricated by Replacement Metal. Gate (RMG) technology with effective ...
[40]
Limits of Gate Dielectrics Scaling - ScienceDirect.com
This chapter discusses limits of gate dielectric scaling for advanced metal oxide semiconductor field effect transistor (MOSFET).Chapter 5 - Limits Of Gate... · 5.5. Hafnium-Based Ternary... · 5.7. Ab Initio Modeling
[41]
Integrated 2D multi-fin field-effect transistors | Nature Communications
Apr 29, 2024 · A single-crystalline native dielectric for two-dimensional semiconductors with an equivalent oxide thickness below 0.5 nm. Nat. Electron. 5 ...
[42]
Ferroelectric HfZrO x -based MoS 2 negative capacitance transistor ...
Mar 7, 2018 · A negative capacitance field-effect transistor (NCFET) built with hafnium-based oxide is one of the most promising candidates for low power-density devices.
[43]
InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec ...
Dec 14, 2016 · InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54 mV/dec SS is achieved at 100 pA/μm.
[44]
[PDF] Design-technology Co-optimization for Sub-2 nm ... - DSpace@MIT
Mar 27, 2025 · The performance of MCTs can be boosted by gate stack electrostatic doping and EOT scaling using high-k dielectric of HZO. However, the ...<|separator|>
[45]
Two dimensional semiconducting materials for ultimately scaled ...
Oct 21, 2022 · Here, we review state-of-the-art techniques to achieve ultra-scaled 2D transistors with novel configurations through the scaling of channel, gate, and contact ...Missing: targets | Show results with:targets
[46]
[PDF] MOSFET DEVICE SCALING: A (BIASED) HISTORY OF GATE STACKS
We briefly describe some of the early problems that needed to be solved to allow the use of SiO2 and its implementation for device scaling. Improved SiO2.
[47]
[PDF] Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to ...
This paper will present results on the 0.8nm SiO2 and very high-performance PMOS and NMOS transistors with high-K/metal-gate for high-performance logic ...
[48]
[PDF] Part One Scaling and Challenge of Si-based CMOS - Wiley-VCH
Jun 20, 2012 · Several independent works showed the inconvenience of fabricated CMOSFET devices with SiO2 gate oxides thinner than about 1.0–1.2 nm because ...
[49]
[PDF] High-k Gate Dielectrics - The Electrochemical Society
In the 70 nm technology node, the required gate oxide thickness is about 0.7 nm, which is only two atomic layers of silicon oxide and is the ultimate limit of ...Missing: equivalent review
[50]
[PDF] gate Dielectric Process technology for the sub-1 nm equivalent ...
The introduction of nitrogen in SiO2 to form SiON increases the effective dielectric constant, κ. The higher effective dielectric constant leads to a lower ...Missing: quantum | Show results with:quantum
[51]
[PDF] Advanced Metal Gate/High-K Dielectric Stacks for High ... - Intel
The resulting metal gate/high-K dielectric stacks have equivalent oxide thickness (EOT) of 1.0nm with negligible gate oxide leakage, and channel mobilities that ...Missing: 2007 HfSiON
[52]
[PDF] A 45nm Logic Technology with High-k+Metal Gate Transistors ...
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon,. 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging.
[53]
[PDF] A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High ...
This 22nm SoC platform uses 3-D Tri-Gate technology for low power, high performance, and high density, with low standby power and high voltage transistors.Missing: 2011 | Show results with:2011
[54]
Challenges of high-k gate dielectrics for future MOS devices
The ultra-thin HfO2/SiO2 gate stack high-k dielectrics were deposited by atomic layer deposition. The physical and structural properties of the HfO2/SiO2 films ...
[55]
2022 IRDS Beyond CMOS
Mar 26, 2020 · Integrated high k dielectrics with EOT <0.5nm and low leakage. Integrated contact structures that have ultralow contact resistivity ...
[56]
(PDF) Advanced CMOS gate stack: Present research progress
Aug 7, 2025 · This paper reviews the progress and efforts made in the recent years for high-k dielectrics, which can be potentially integrated into 22 nm (and ...<|separator|>
[57]
Single-crystalline High-κ GdOCl dielectric for two-dimensional field ...
Nov 2, 2024 · Two-dimensional (2D) dielectrics, integrated with high-mobility semiconductors, show great promise to overcome the scaling limits in ...Missing: post- milestones
[58]
High-κ Wide-Gap Layered Dielectric for Two-Dimensional van der ...
Apr 1, 2024 · Our work demonstrates the versatile realization and functionality of 2D systems with wide-gap and high-κ van der Waals dielectric environments.Missing: GAA | Show results with:GAA