5 nm process
The 5 nm process is an advanced node in semiconductor manufacturing that scales transistor features to approximately 5 nanometers using fin field-effect transistor (FinFET) architecture and extreme ultraviolet (EUV) lithography, achieving up to 1.8 times the logic density of the preceding 7 nm node while delivering 15% higher performance or 30% lower power consumption at the same speed.[1] Developed primarily by leading foundries Taiwan Semiconductor Manufacturing Company (TSMC) and Samsung Electronics, the 5 nm process entered volume production in 2020 with TSMC's N5 variant, marking the first widespread adoption of EUV for multiple layers to enable precise patterning at this scale.[1] Samsung followed with mass production of its SF5 process in 2020, offering a 25% increase in logic density, 10% performance uplift, or 20% power reduction compared to its 7 nm technology.[2] Both implementations incorporate high-mobility channel materials, such as silicon-germanium (SiGe) for p-type FinFETs in TSMC's case, to enhance carrier mobility and overall efficiency.[3] Key variants of the process include TSMC's N5P, which provides an additional 5% performance improvement or 10% power savings over N5, and N4, a refined 5 nm-class node with further density gains for cost-sensitive applications.[4] Samsung's SF5 is optimized for high-performance computing (HPC) and automotive-grade chips, featuring tight process controls to support functional safety standards like ISO 26262.[5] These advancements have enabled transistor densities exceeding 170 million per square millimeter, facilitating the integration of over 100 million transistors in a typical smartphone system-on-chip (SoC).[6] The 5 nm process powers a wide range of applications, including mobile devices for 5G and AI processing, high-end servers for data centers, and automotive systems for advanced driver-assistance features.[7] Notable deployments include mobile SoCs for smartphones and wearables, as well as solid-state drive controllers, underscoring its role in driving energy-efficient computing amid growing demands for AI and edge processing.[8][9] By 2025, the node remains a cornerstone for performance-critical designs, bridging the transition to even smaller nodes like 3 nm while addressing challenges in yield and cost through ongoing optimizations.[10]Technology Fundamentals
Node Definition and Metrics
The 5 nm process node represents a generation of semiconductor manufacturing technology characterized primarily as a marketing designation rather than a literal measurement of physical dimensions, such as gate length, which has long ceased to align directly with node names. Instead, it approximates advancements in transistor density and key feature sizes, including a minimum metal pitch (MMP) of approximately 28-36 nm and a contacted poly pitch (CPP) of 48-60 nm, enabling tighter integration of logic elements while adhering to scaling rules defined by industry roadmaps like the International Roadmap for Devices and Systems (IRDS).[11][12][13] Key performance metrics for the 5 nm node emphasize improvements in density, power efficiency, and speed, with standard cell transistor density reaching up to 170 million transistors per square millimeter (MTr/mm²), a metric that reflects optimized logic area scaling for high-volume production.[13] Compared to the preceding 7 nm node, which achieves around 100 MTr/mm² in similar benchmarks, the 5 nm process delivers approximately 1.7-1.8× higher density, allowing for more complex circuits within the same die area.[11][14] This scaling is quantified through standard logic area metrics, where the 5 nm node reduces cell area by about 40-50% relative to 7 nm while maintaining functionality. In terms of power and performance, the 5 nm node provides 15-30% better power efficiency and 10-15% higher speed at iso-power compared to 7 nm, as measured in representative high-performance computing workloads, enabling applications like mobile SoCs and AI accelerators to balance thermal constraints with computational demands. These gains stem from refinements in FinFET transistor architecture, which enhances electrostatic control and reduces leakage currents to sustain Moore's Law scaling at this node, serving as a critical precursor to gate-all-around FET (GAAFET) structures in subsequent generations.[15] Extreme ultraviolet (EUV) lithography plays an enabling role by patterning these finer features with higher precision.[11]Architectural Innovations
The adoption of extreme ultraviolet (EUV) lithography in the 5 nm process enabled single-patterning for critical layers, significantly reducing the multi-patterning complexity that was prevalent in the 7 nm node and simplifying fabrication steps while improving pattern fidelity.[16] This shift allowed for tighter pitches without the overlay errors associated with multiple exposures, contributing to higher throughput and lower costs in production.[16] Refinements in FinFET architecture at the 5 nm node focused on optimizing fin dimensions, including fin heights of approximately 50-60 nm, widths around 6-8 nm, and pitches scaled to 27 nm or below, to enhance electrostatic control and boost drive current by up to 15-20% compared to prior nodes. These adjustments minimized short-channel effects and improved gate-to-channel coupling, enabling better performance in high-density logic circuits while maintaining low leakage.[17] Interconnect improvements in the 5 nm process incorporated cobalt liners for copper lines, which reduced resistance by mitigating grain boundary scattering in narrow features below 20 nm pitch, and advanced low-k dielectrics with effective permittivity values around 2.5-2.7 to lower inter-layer capacitance.[18] These enhancements addressed RC delay challenges, improving signal integrity and overall chip speed by 10-15% in dense metallization schemes.[18] Power delivery network enhancements at the 5 nm node included denser local power routing and reduced via resistance through selective metallization, serving as precursors to full backside power delivery by minimizing IR drop and enabling more efficient voltage distribution in multi-core designs.[19] For high-volume manufacturing, the 5 nm process targeted defect densities below 0.1 defects/cm², achieving mature yields exceeding 90% through improved lithography and metrology controls.[20]Historical Development
Early Research and Announcements
Research into the 5 nm semiconductor process originated in the late 2010s as part of broader efforts to extend Moore's Law amid diminishing returns from prior nodes. In January 2016, TSMC outlined its technology roadmap, projecting the 5 nm process to enter production by 2020 as a full-node advancement over its 7 nm technology, with development already in the full stage by the end of that year.[21][22] Similarly, in May 2017, Samsung announced its foundry roadmap, positioning 5 nm as a key node following 6 nm, with initial variants like 5LPE emphasizing low-power enhancements through EUV integration.[23] Key collaborations accelerated feasibility studies, particularly through Imec's contributions to EUV lithography and gate-all-around (GAA) transistor development. Imec's work on EUV patterning and process co-optimization enabled early demonstrations of 5 nm scaling potential, including GAA prototypes that addressed FinFET limitations in channel control and leakage. By 2017, Imec introduced extensions to GAA architectures, such as forksheet transistors, validating their viability for sub-5 nm nodes through joint efforts with industry partners.[24][25] Milestones in 2018-2019 highlighted competitive dynamics, influenced by Intel's repeated delays in 10 nm volume production, which extended into 2019 due to yield challenges and allowed foundries like TSMC and Samsung to advance their announcements without immediate pressure. In October 2018, TSMC taped out its first 7 nm EUV designs and scheduled 5 nm tape-outs for the first half of 2019, followed by risk production initiation in April 2019. Samsung completed 5 nm EUV development by April 2019, enabling customer tool access and underscoring rapid progress in low-power FinFET scaling.[26][27][28][2] Academic contributions from IEEE conferences emphasized scaling limits, with the 2017 International Roadmap for Devices and Systems (IRDS) report detailing challenges in sub-5 nm feature control, such as quantum effects and interconnect variability. A 2017 IEEE paper on CMOS trends further analyzed transistor innovations needed to sustain density gains at 5 nm, prioritizing high-mobility channels and 3D integration. These works, presented at events like IEDM, informed industry roadmaps by quantifying trade-offs in power, performance, and area.[29][30]Commercial Production Timeline
TSMC initiated risk production for its 5 nm N5 process in April 2019, achieving high-volume manufacturing ramp-up by the second quarter of 2020 and full qualification by the fourth quarter of the same year.[31] Samsung began volume production of its 5LPE process in the second quarter of 2020, with shipments of initial 5 nm system-on-chips commencing in the third quarter.[32][33] In 2021, TSMC introduced the N5P variant, an enhanced version of N5 offering approximately 5% higher performance or 10% lower power consumption at iso-speed, alongside density improvements to support expanding customer demands.[34][12] Production ramps for 5 nm processes accelerated through 2021 and 2022 despite supply chain challenges from COVID-19 lockdowns and material shortages, which temporarily constrained global semiconductor output.[35][36] Yield rates for TSMC's 5 nm process improved rapidly from around 50% at the start of mass production in early 2020 to over 80% within months, reaching mature levels above 80% by 2022 as process optimizations took hold.[37][38] By 2023, 5 nm capacity utilization approached full levels, with TSMC reporting 100% utilization for its 5 nm and advanced nodes in 2024 amid surging demand.[39][40] By 2025, Semiconductor Manufacturing International Corporation (SMIC) completed development of its 5 nm process without extreme ultraviolet (EUV) lithography, though with yields about one-third of TSMC's equivalent and costs 40-50% higher.[41][42][43] Bookings for TSMC's 5 nm production extended into 2026, driven primarily by artificial intelligence applications requiring high-performance computing chips.[44][45]Manufacturing Approaches
TSMC Processes
TSMC's N5 process represents a pivotal advancement in semiconductor fabrication, employing extreme ultraviolet (EUV) lithography for over 10 critical layers to enable precise patterning of features such as cuts, contacts, vias, and metal lines, thereby reducing the need for multiple immersion lithography exposures.[13] This approach incorporates single-patterning EUV techniques for tight pitches in the backend-of-line (BEOL) interconnects, supplemented by multiple patterning where necessary to achieve the required resolution for high-density logic and memory structures.[6] Additionally, the N5 flow integrates high-mobility channels using silicon-germanium (SiGe) as the p-type FinFET channel material, enhancing carrier mobility and drive current for improved performance in mobile system-on-chips (SoCs) and high-performance computing (HPC) applications.[3] The N5P variant builds on the N5 foundation with targeted enhancements, with comparable transistor density to N5 through layout optimizations that maximize EUV utilization in select layers while maintaining backward compatibility for intellectual property (IP) reuse.[46] These optimizations include refined design rules for standard cells and SRAM bit cells, allowing for more efficient packing without altering the core FinFET architecture or requiring extensive redesigns.[47] Alongside density gains, N5P offers approximately 5% higher performance or 10% lower power at iso-power compared to N5, further leveraging the high-mobility channel integration for balanced power and speed trade-offs.[46] TSMC's fabrication infrastructure for the 5 nm family relies on 300 mm silicon wafers processed in advanced cleanroom environments across its Taiwan-based GigaFabs, such as Fab 18, which supports high-volume production of N5 and related nodes.[48] Critical to maintaining yield and precision is advanced metrology for overlay control, achieving accuracy below 2 nm to align multiple EUV-exposed layers and minimize defects in multi-patterned regions.[15] This sub-2 nm overlay capability is enabled by high-resolution optical and e-beam metrology tools integrated into the process flow, ensuring alignment tolerances meet the stringent requirements of FinFET scaling. The cost structure for N5 production reflects the increased complexity of EUV integration; as reported in 2020, wafer pricing was approximately 80% higher than for the 7 nm node (around $17,000 per 300 mm wafer versus $9,500), primarily due to EUV tool depreciation, higher consumables, and extended process times.[49] By 2025, N5 prices have stabilized around $18,000–$20,000 per wafer, with per-transistor costs remaining competitive owing to the 1.8× density scaling over 7 nm, though overall fabrication expenses rose by 20-30% attributable to EUV-specific operations like source mask optimization and resist processing.[50][51] Despite these elevations, TSMC anticipates 3-5% hikes for sub-5 nm nodes like N3 and N2 starting in 2026 to offset capacity expansions.[52] In terms of production scale, TSMC's 5 nm capacity across Taiwan facilities exceeded 100,000 wafers per month by 2025, concentrated in facilities like Fab 18 dedicated to advanced nodes, supporting the ramp-up for major clients in mobile and AI sectors.[53] This expansion, part of a broader GigaFab network, has enabled over 200,000 wafers per month across 5 nm and finer nodes collectively, underscoring TSMC's dominance in EUV-enabled manufacturing.[54]Samsung and Other Foundry Methods
Samsung's 5 nm process, designated as SF5, is a FinFET-based technology that entered mass production in 2021 and utilizes extreme ultraviolet (EUV) lithography for critical logic layers to achieve higher density and efficiency. While EUV is employed for key patterning steps, deep ultraviolet (DUV) lithography is used for select non-critical layers to optimize cost and throughput. This approach enables up to a 25% increase in logic density compared to Samsung's prior 7 nm node, with 10% higher performance or 20% lower power consumption.[2][55][56] In parallel, Samsung developed the 5LPE (5 nm Low Power Early) variant, which builds on innovations from the 7LPP process to emphasize ultra-low power benefits and area scaling, supporting applications in mobile and high-performance computing. The SF5 node serves as a foundational platform, facilitating a smoother transition to gate-all-around (GAA) architectures in subsequent generations like Samsung's 3 nm process. Unlike some competitors, Samsung places greater emphasis on 3D stacking integration, such as its X-Cube technology, which enables silicon-proven 3D IC designs for 5 nm nodes to enhance heterogeneous integration and performance in multi-die systems.[57][58][59] Semiconductor Manufacturing International Corporation (SMIC), China's leading foundry, has pursued a 5 nm process without access to EUV tools due to U.S. sanctions, relying instead on deep ultraviolet (DUV) lithography combined with self-aligned quadruple patterning (SAQP) and multi-patterning techniques. This non-EUV approach aims to achieve comparable feature sizes through increased patterning complexity, with development targeted for completion and initial mass production by 2025 to support domestic Chinese chip designs, particularly for Huawei's Kirin processors. Despite higher costs and potential yield challenges from the multi-patterning, this effort underscores SMIC's push for semiconductor self-sufficiency amid geopolitical restrictions.[60][42][61] GlobalFoundries maintains limited involvement in 5 nm production, focusing instead on partnerships and mature nodes rather than standalone advanced manufacturing at this scale. Early collaborations, such as with IBM and Samsung in 2017 for 5 nm research, did not lead to commercial 5 nm fabs; by 2025, the company prioritizes specialty technologies like 12 nm and below for automotive and RF applications, securing orders through alliances with firms like AMD for less advanced processes.[62][63][64] Intel's role in 5 nm-equivalent processes is primarily internal, with its Intel 4 node—deployed starting in 2023 for products like Meteor Lake—offering transistor densities and performance comparable to industry 5 nm standards, though it remains a FinFET-based technology without RibbonFET implementation. This node supports Intel's high-volume internal fabrication for CPUs and GPUs, with limited external foundry offerings at this level to prioritize ecosystem development for future nodes.[65][66][67]Process Variants
5 nm Specific Nodes
The 5 nm process includes several specialized node variants from major foundries, each tailored to balance power, performance, and area (PPA) requirements for diverse applications such as mobile and high-performance computing. The following table summarizes key specifications for select 5 nm variants:| Foundry/Node | Transistor Density (MTr/mm²) | Performance/Power vs Prior Node | Key Specs |
|---|---|---|---|
| TSMC N5 | ~171 | 15% perf or 30% power reduction vs N7 | Poly pitch ~48-51 nm, metal pitch ~30 nm[13] |
| TSMC N5P | ~171 | 10% perf or 22% power savings vs N5 | Backward compatible with N5[46] |
| Samsung 5LPE | ~135 | 10% perf or 20% power reduction vs 7 nm | Energy efficiency focus[68] |
| Samsung 5LPP | ~135 | Similar to 5LPE, optimized for low power | Multi-patterning enhancements[69] |
| SMIC N+3 | ~125 | Comparable to 5 nm-class vs SMIC 7 nm | DUV-based, lower density than peers[70] |