Fact-checked by Grok 2 weeks ago

Gate capacitance

Gate capacitance refers to the electrical capacitance between the gate electrode and the underlying semiconductor channel in a metal-oxide-semiconductor field-effect transistor (MOSFET), primarily determined by the thin insulating oxide layer that separates them. This capacitance, often denoted as C_g or C_{ox}, is calculated as C_g = C_{ox} \cdot W \cdot L, where C_{ox} = \epsilon_{ox} / t_{ox} is the oxide capacitance per unit area, \epsilon_{ox} is the permittivity of the oxide, t_{ox} is the oxide thickness, W is the channel width, and L is the channel length. In MOSFET operation, gate capacitance enables control of the channel conductivity through applied voltage, forming the basis for amplification and switching functions in integrated circuits. The total gate capacitance comprises several components that vary with bias conditions and operating regions of the transistor. In the cutoff region, it includes gate-to-body capacitance (C_{GB} = C_{ox} \cdot W \cdot L_{eff}) and overlap capacitances (C_{GSO} and C_{GDO}). During linear operation, the channel capacitance splits roughly equally between gate-to-source (C_{GS}) and gate-to-drain (C_{GD}), each approximately \frac{1}{2} C_{ox} \cdot W \cdot L_{eff}. In saturation, C_{GS} dominates as \frac{2}{3} C_{ox} \cdot W \cdot L_{eff} + C_{ox} \cdot W \cdot x_d, where x_d is the overlap length, while C_{GD} is minimized, reducing the that amplifies effective input capacitance in amplifiers. These voltage-dependent behaviors are characterized through capacitance-voltage (C-V) measurements, where the MOS structure exhibits accumulation (high capacitance ≈ C_{ox}), depletion (decreasing to a minimum), and inversion (recovering to ≈ C_{ox}) regimes. Gate capacitance plays a critical role in the performance of CMOS circuits by influencing switching speed, dynamic power dissipation, and overall efficiency. It contributes significantly to the total load capacitance (C_L) in logic gates, where delay scales linearly with C_L according to models like \tau_D \approx R \cdot C_L, with R being the effective resistance of the pull-up or pull-down network. Higher gate capacitance increases the energy required to charge and discharge the gate during transitions, elevating dynamic power consumption proportional to C V^2 f, where V is supply voltage and f is frequency. In nanoscale devices, reducing gate capacitance through thinner oxides or high-k dielectrics enables faster operation and lower power, though it introduces challenges like increased gate leakage. Accurate modeling of these capacitances is essential for circuit simulation and optimization in VLSI design.

Fundamentals

Definition and Basic Concept

Gate capacitance refers to the between the and the underlying in field-effect transistors (FETs), primarily arising from the gate insulator layer that separates the gate from the channel region. This capacitance enables electrostatic control of the charge carriers in the , forming the basis for modulating the transistor's conductivity. In metal-oxide- field-effect transistors (MOSFETs), it is modeled as the equivalent at the gate terminal, representing the ability to store charge in response to applied voltage. The foundational model for gate capacitance is the simple parallel-plate capacitor approximation, where the gate electrode and the surface act as the two plates, with the serving as the . The total gate capacitance C_g is quantified by the formula C_g = \frac{\epsilon A}{t_{ox}}, where \epsilon is the of the , A is the effective gate area, and t_{ox} is the thickness of the (or ) layer. This model provides the starting point for understanding how voltage applied to the induces charge in the , controlling current flow between and . The is often expressed in farads (F) for the total or normalized as capacitance per unit area in F/cm² to facilitate comparisons across different geometries. The concept of gate capacitance emerged in the context of development during the late 1950s and early 1960s at Bell Laboratories, where researchers and fabricated the first working silicon devices in 1960. Their work built upon earlier studies of capacitors, which demonstrated stable silicon-silicon dioxide interfaces through techniques pioneered by Atalla. This historical advancement established gate capacitance as a critical parameter for reliable FET operation, paving the way for scaling.

Physical Origin in Semiconductors

Gate capacitance in semiconductors arises from the electrostatic interaction at the metal-insulator-semiconductor (MIS) interface, where an applied gate voltage modulates the charge distribution within the semiconductor substrate. In a typical MOS structure, the semiconductor (often p-type silicon) responds to the voltage by forming distinct layers near the insulator-semiconductor boundary. For negative gate voltages relative to the flat-band condition, an accumulation layer forms, where majority carriers (holes) are attracted to the interface, increasing their concentration exponentially and enabling efficient charge storage akin to a parallel-plate capacitor. As the voltage becomes positive, a depletion layer develops, repelling majority carriers and creating a region of exposed, ionized dopants that widens with increasing voltage, reducing the effective charge storage capacity. At sufficiently positive voltages, an inversion layer emerges, where minority carriers (electrons) accumulate at the surface, bending the energy bands to favor their inducement and restoring high capacitance levels. These layers result in variable charge storage, fundamentally distinguishing MOS capacitance from fixed-value capacitors. The initial capacitance is influenced by the work function difference between the material and the , which determines the flat-band voltage and aligns the across the structure. The , defined as the energy required to remove an from the to vacuum, varies with material properties; for instance, n+-polysilicon gates exhibit a of approximately 4.05 , while p-type silicon's is higher due to its doping. This difference, denoted as φ_ms, shifts the energy bands even at zero bias, setting the baseline for charge inducement. alignment ensures in the bulk but leads to potential barriers at the interface, modulated by the insulator's properties. These factors establish the starting point for voltage-induced changes, with seminal demonstrations of stable Si-SiO₂ interfaces enabling reliable capacitance control. Quantum mechanical effects further shape charge inducement through the semiconductor's bandgap and , which dictate available energy levels for carriers. The bandgap energy (∼1.12 eV for ) limits carrier excitation, while the —higher in the conduction band for electrons—governs how efficiently minority carriers populate the inversion layer. Under bias, occurs qualitatively at the : in accumulation or inversion, bands curve toward the to increase carrier density near the surface; in depletion, they curve away, creating a that depletes carriers. This bending, driven by the surface potential ψ_s, reflects the electric field's penetration into the , altering local carrier concentrations without uniform distribution. Unlike ideal capacitors with uniform charge sheets, the non-uniform charge profile in the —peaking sharply near the and decaying exponentially—necessitates defining as the differential quantity dQ/dV, representing the incremental charge response to a small voltage change and capturing the structure's voltage-dependent behavior.

Components in Transistors

Gate Oxide Capacitance

The gate oxide , denoted as C_{ox}, represents the primary capacitive element between the gate electrode and the channel in a metal-oxide-semiconductor field-effect transistor (). It arises from the insulating layer, typically (SiO_2) in early devices, and is calculated using the parallel-plate formula: C_{ox} = \frac{\epsilon_{ox} A}{t_{ox}} where \epsilon_{ox} is the of the , A is the gate area, and t_{ox} is the physical thickness of the oxide layer. For SiO_2, \epsilon_{ox} = 3.9 \epsilon_0, with \epsilon_0 = 8.85 \times 10^{-12} F/m being the vacuum . This directly controls the amount of charge induced in the semiconductor channel by the gate voltage, thereby modulating the transistor's conductivity and enabling its switching operation. In the evolution of MOSFET technology, SiO_2 served as the gate dielectric from the 1960s through the 1990s due to its excellent electrical properties and compatibility with processing. However, as device progressed into the sub-100 regime in the early , the need for thinner oxides to maintain high C_{ox} led to increased quantum mechanical tunneling currents and reliability degradation. To address this, high-k s—materials with relative permittivities greater than that of SiO_2—were introduced, with hafnium oxide (HfO_2) emerging as a leading candidate around 2007 for its high (k \approx 20-25) and thermal stability. This transition allowed for physically thicker layers that preserved while reducing leakage, as implemented in Intel's node. To compare the capacitive performance of high-k materials with traditional SiO_2, the (EOT) is used, defined as: \text{EOT} = t_{\text{phys}} \times \frac{\epsilon_{\text{SiO}_2}}{\epsilon_{\text{high-k}}} where t_{\text{phys}} is the physical thickness of the high-k layer and \epsilon_{\text{SiO}_2} / \epsilon_0 = 3.9. This metric expresses the effective thickness as if the dielectric were SiO_2, enabling direct assessments; for instance, a 3 nm HfO_2 layer can yield an EOT of approximately 0.5 nm (using k \approx 24). High-k integration often involves interfacial layers to mitigate defects, but achieving sub-1 nm EOT remains challenging for continued in production devices, though research has demonstrated values as low as 0.67 nm in specialized structures as of 2025. Despite these advances, ultra-thin oxides below 2 nm, whether SiO_2 or high-k equivalents, suffer from significant direct tunneling currents that increase leakage and degrade reliability. These currents, dominated by injection through the barrier, lead to issues such as stress-induced leakage current (SILC) and time-dependent (TDDB), limiting operational lifetime under high-field conditions. Studies on 1.4-2 nm oxides have shown that while tunneling can be modeled, it imposes limits on further without materials or architectures.

Overlap and Fringing Capacitances

In metal-oxide-semiconductor field-effect transistors (MOSFETs), overlap capacitances arise from the physical extension of the gate electrode beyond the channel edges into the source and drain regions, creating parallel-plate capacitive coupling. This extrinsic component, denoted as C_{ol}, is given by C_{ol} = \epsilon_{ox} \cdot W \cdot L_{ov} / t_{ox}, where \epsilon_{ox} is the permittivity of the gate oxide, W is the channel width, L_{ov} is the overlap length on each side, and t_{ox} is the oxide thickness. These capacitances contribute significantly to the total gate-to-source (C_{gs}) and gate-to-drain (C_{gd}) capacitances, particularly in short-channel devices where L_{ov} becomes comparable to the effective channel length. Fringing capacitances, another parasitic element, originate from lines that curve around the edges rather than passing directly through the , primarily at the sidewalls and between the and / extensions. These fields are not confined to the flat area and are modeled as a geometry-dependent term often on the order of 0.2–0.5 /μm of width, though more precise formulations employ techniques to account for the non-uniform field distribution. In advanced models like BSIM3, fringing capacitance is bias-independent for the outer component and calculated as C_F = \frac{\epsilon_{ox}}{\pi} \ln\left(\frac{t_g + t_{ox}}{t_{ox}}\right) \cdot W, where t_g is the height, highlighting its dependence on vertical dimensions. Modern fabrication processes incorporate gate sidewall spacers—typically silicon nitride or low-k dielectrics deposited after gate formation—to define lightly doped drain (LDD) regions, which reduce the overlap length L_{ov} by controlling dopant implantation and thus minimizing short-channel effects. However, thicker or higher-k spacers can enhance fringing fields at the gate edges, partially offsetting the overlap reduction and increasing the overall parasitic capacitance. This trade-off is critical in sub-100 nm nodes, where spacers enable reliable scaling but demand optimized materials to balance capacitance and reliability. The total gate capacitance integrates these parasitics with the intrinsic oxide capacitance as C_{g,total} = C_{ox} + 2C_{ol} + C_{fringe}, where C_{ox} is the channel-area component; as dimensions scale, the relative contribution of $2C_{ol} + C_{fringe} grows, potentially comprising 20–50% of C_{g,total} in nanoscale devices and limiting switching speeds.

Dependence on Operating Conditions

Bias Voltage Effects

In metal-oxide-semiconductor (MOS) structures, the gate capacitance exhibits distinct variations with applied bias voltage, as characterized by capacitance-voltage (C-V) measurements. For a p-type substrate, when the gate voltage V_g is sufficiently negative relative to the flat-band voltage V_{fb}, the surface enters accumulation, where majority carriers (holes) accumulate at the oxide-semiconductor interface, resulting in a capacitance C_{acc} approximately equal to the oxide capacitance C_{ox} = \epsilon_{ox} / t_{ox}. As V_g increases toward positive values, the device transitions to depletion, where the capacitance decreases to a minimum due to the widening depletion region, forming a series combination with C_{ox}: C_{dep} = \frac{C_{ox} C_{d}}{C_{ox} + C_{d}}, with the depletion capacitance C_{d} = \epsilon_{si} / W_d. The depletion width W_d under bias is given by W_d = \sqrt{ \frac{2 \epsilon_{si} \phi_s }{q N_a} }, where \phi_s is the surface potential that increases with V_g, \epsilon_{si} is the permittivity of silicon, q is the elementary charge, and N_a is the acceptor doping concentration; this widening continues until the onset of inversion near the threshold voltage V_{th}, where minority carriers (electrons) begin to form an inversion layer, marking the transition point for capacitance recovery. Beyond V_{th}, in strong inversion, the inversion layer shields the depletion region, restoring the capacitance to approximately C_{inv} \approx C_{ox}. The threshold voltage V_{th} thus defines the key transition, influencing the bias range over which capacitance varies significantly, with V_{th} = V_{fb} + 2\phi_f + \frac{\sqrt{4 \epsilon_{si} q N_a \phi_f }}{C_{ox}} for ideal p-type MOS capacitors, where \phi_f is the Fermi potential. In the weak inversion regime, between depletion and strong inversion (typically V_{fb} + \phi_s < V_g < V_{th}), partial formation leads to a gradual increase in as minority carrier density rises exponentially with gate overdrive, resulting in a logarithmic-like rise toward C_{ox} due to the sub-exponential response of inversion charge to . This region is critical for understanding low-power device behavior, where the capacitance reflects the onset of diffusion-dominated minority carrier response. Hysteresis in C-V curves arises from charge trapping at the oxide-semiconductor or in near- oxide s, causing a shift in the curve during forward and reverse voltage sweeps; this is quantified by the flat-band voltage shift \Delta V_{fb}, which measures the voltage difference between upward and downward sweeps at constant , often on the order of 10-100 mV for devices with trap densities D_{it} exceeding $10^{11} cm^{-2} eV^{-1}. traps, with energy levels within the bandgap, capture and emit carriers in response to changes, leading to slower response times and observable , particularly under stress es that fill traps.

Frequency and Temperature Influences

In metal-oxide-semiconductor () structures, the gate capacitance exhibits significant frequency dependence, particularly in the inversion regime where minority carriers play a key role in charge response. At low frequencies, typically below 1 kHz, the minority carriers can fully respond to the () signal, allowing the gate capacitance to approach the oxide capacitance value, C_{\text{low-f}} \approx C_{\text{ox}}. This quasi-static behavior ensures that the inversion layer charge adjusts rapidly enough to maintain equilibrium. At higher frequencies, exceeding 1 MHz, the finite response time of minority carriers prevents them from following the signal, resulting in a reduced gate capacitance, C_{\text{high-f}} < C_{\text{ox}}. In this case, the measured capacitance reflects the series combination of the oxide capacitance and the depletion capacitance, as the inversion charge lags behind. The transition from low- to high-frequency regimes occurs around a characteristic \omega_c \approx 1/\tau, where \tau represents the minority , typically on the order of microseconds in . This frequency-dependent behavior is critical for understanding dynamic device operation beyond static conditions. High-frequency capacitance measurements are further complicated by series resistance effects, such as those from contacts, bulk material, and probe parasitics, which introduce additional impedance and cause an underestimation of the true value. These resistances lead to a phase shift in the signal, effectively rolling off the apparent , especially in structures with high leakage or thin oxides. Correction techniques, including multi-frequency analysis or conductance methods, are often required to mitigate this artifact and extract accurate parameters. Temperature variations influence gate capacitance primarily through changes in the intrinsic carrier concentration n_i, which affects the width in the . As increases, n_i rises exponentially, narrowing the depletion width and altering the effective ; however, in practice for devices, the overall gate capacitance exhibits only a weak dependence, typically showing a slight decrease due to combined impacts on carrier statistics and properties. This effect is more pronounced in the depletion and weak inversion regimes. In radio-frequency (RF) applications, the high-frequency imposes key limitations on performance, reducing the unity-current-gain f_T = g_m / (2\pi C_g) and thereby constraining maximum gain. Additionally, the frequency-dependent contributes to elevated figures in RF amplifiers, as induced gate correlates with gate-drain and gate-source components, degrading signal-to-noise ratios at gigahertz frequencies. These effects necessitate careful modeling for RF , particularly in scaled technologies.

Measurement and Modeling

Experimental Techniques

One primary experimental technique for characterizing capacitance in MOSFETs is capacitance-voltage (C-V) profiling, which involves applying a sweep across the gate while superimposing a small signal to measure the resulting . This method typically uses parameter analyzers such as the 4155 or its successor, the B1500A, to apply the bias sweep and AC perturbation, with signal amplitudes of 10-50 mV and frequencies ranging from 1 kHz to 1 MHz. The resulting C versus V plot enables extraction of key parameters including capacitance C_{ox}, V_{th}, and indicators of integrity such as flat-band voltage shifts. To isolate intrinsic gate capacitance from extrinsic components like overlap and fringing capacitances, the split-C-V method is employed by fabricating transistors with varying gate lengths and measuring total gate capacitance as a function of gate length. By plotting the measured capacitance against gate length and extrapolating to zero length, the intrinsic capacitance is obtained, while the slope reveals extrinsic contributions. This approach is particularly useful for submicron devices, where extrinsic effects dominate short-channel behavior. Accurate extraction faces challenges from parasitic probe capacitances and gate leakage currents, especially in thin-oxide devices. Parasitic capacitances from probes and cabling, often on the order of picofarads, are subtracted by performing open-circuit measurements prior to device testing and deducting the baseline from the total measured capacitance. For gate leakage correction in ultra-thin oxides, the conductance method is applied, where the parallel conductance G_p is measured as a function of angular frequency \omega, and the leakage is quantified via the peak value of G_p / \omega to adjust the apparent capacitance without significant distortion. For high-frequency characterization up to the GHz range, non-destructive microwave C-V techniques utilize vector network analyzers to probe under RF conditions, mitigating issues like series resistance effects that plague low-frequency methods in advanced nodes. These approaches enable evaluation of frequency-dependent behaviors in operational regimes, such as inversion layer dynamics.

Analytical and Simulation Models

Analytical models for gate capacitance in MOSFETs range from simple approximations suitable for basic digital circuit simulations to more sophisticated formulations that account for bias, frequency, and geometry effects. The Meyer model, introduced in 1971, treats gate capacitances as piecewise linear functions of terminal voltages, dividing operation into , linear, and saturation regions with fixed values such as C_{gb} = C_{ox} in and C_{gs} = C_{ox}/2, C_{gd} = C_{ox}/2 in . This approach assumes constant or voltage-stepped capacitances, enabling efficient simulations in tools like but lacking detailed physical dependencies, which can lead to charge non-conservation issues in transient analyses. Advanced compact models, such as those in the BSIM family, provide bias-dependent descriptions of total gate C_g, incorporating intrinsic channel capacitances and extrinsic overlap components. In BSIM4, the capacitance model (controlled by parameter capMod, default 2) uses a charge-thickness approach for smooth transitions across accumulation, depletion, and inversion, with effective oxide C_{oxeff} = C_{oxe} / (1 + C_{oxe} \cdot X_{DC} / \epsilon_{si}), where X_{DC} adjusts for charge layer thickness based on surface potential. Bias effects are captured through voltage terms like V_{gsteff,CV}, while overlap capacitances include gate-source/drain contributions modulated by parameters such as CKAPPAS, e.g., Q_{s,overlap} = W_{active} \cdot [CGSO + CGSL \cdot (1 + (V_{gs,overlap} - CKAPPAS)^4)^{-1/2}]. Frequency dependence is addressed via non-quasi-static (NQS) extensions in BSIM, though static models predominate for DC predictions. These models enable accurate prediction of partial depletion scenarios, where C_g reduces from C_{ox} due to incomplete channel inversion. Numerical simulations employ technology computer-aided design (TCAD) tools like Synopsys Sentaurus and Silvaco Atlas to compute gate capacitance by solving the Poisson equation \nabla \cdot (\epsilon \nabla \phi) = -\rho alongside drift-diffusion or hydrodynamic transport equations using finite element or finite volume methods. Capacitance is derived from charge-voltage characteristics (C = dQ/dV) or small-signal AC analysis, which perturbs voltages to extract admittance matrices and decompose into real (conductance) and imaginary (capacitance) parts. These approaches capture 2D/3D effects like fringing fields, validating against experimental CV curves for devices down to 10 nm scales. Variability in gate capacitance arises from process fluctuations, particularly oxide thickness non-uniformity, modeled statistically via methods that sample distributions such as for t_{ox} with standard deviation \sigma_{t_{ox}} \approx 3\% of the mean, propagating to capacitance variations through C_{ox} = \epsilon_{ox}/t_{ox}. These simulations quantify impacts on device matching and yield in scaled technologies. Validation of analytical and simulation models against measurements shows good agreement for nodes above 10 , but discrepancies emerge in sub-10 regimes due to unmodeled quantum effects like confinement and tunneling, necessitating corrections such as density-gradient models or Schrödinger-Poisson solvers to adjust effective by 10-20%. For instance, quantum models reduce predicted C_g in inversion by accounting for charge shifts away from the interface.

Applications and Implications

Role in Device Performance

Gate capacitance plays a pivotal role in determining the switching speed of metal-oxide-semiconductor field-effect transistors (MOSFETs), as it directly affects the intrinsic delay and . The intrinsic delay, defined as \tau = C_g V_{dd} / I_{on}, where C_g is the total gate capacitance, V_{dd} is the supply voltage, and I_{on} is the on-state drive current, quantifies the time required to charge or discharge the gate during switching; higher C_g increases \tau, thereby slowing device operation. Similarly, the unity-gain frequency f_T, given by f_T = g_m / (2\pi C_{gg}), where g_m is the and C_{gg} is the total gate capacitance, represents the frequency at which the current drops to ; an elevated C_g reduces f_T, limiting high-frequency in RF applications. These relationships underscore the need to minimize C_g while maximizing I_{on} and g_m for faster transistors. In terms of power consumption, gate capacitance is a dominant factor in dynamic power dissipation within complementary metal-oxide-semiconductor (CMOS) circuits. The dynamic power P_{dyn} \propto C_g V_{dd}^2 f, where f is the operating frequency, arises primarily from the energy required to charge and discharge the gate capacitance during switching transitions; thus, reducing C_g is essential for achieving low-power designs, particularly in battery-constrained systems like mobile processors. This proportionality highlights capacitance as a key metric in power optimization, where even modest reductions in C_g can yield significant energy savings without compromising functionality. For , gate capacitance influences characteristics and , impacting in amplifiers and mixers. It contributes to input-referred by coupling thermal and sources from the channel to the gate terminal, where larger C_g can amplify the effective noise voltage at the input. Additionally, the voltage-dependent variation in gate capacitance leads to distortion, as nonlinear capacitance modulates signals and generates harmonics or intermodulation products, degrading metrics like the in RF front-ends. Advanced architectures such as FinFETs and gate-all-around (GAA) structures leverage 3D geometry to enhance drive current through boosting, effectively increasing the oxide C_{ox} by wrapping the gate around multiple surfaces of the channel. This multi-faceted gating improves electrostatic control, raising the effective C_g per footprint area and thereby boosting I_{on} for better performance at scaled nodes below 10 nm.

Impact on and

In , gate capacitance imposes significant trade-offs in layout strategies to optimize performance and power efficiency. Parasitic capacitances associated with the gate, such as input capacitance (C_iss), influence layout rules that mandate minimum spacing between metal wires, typically exceeding 1 μm in high-voltage applications, to mitigate and reduce overall switching losses. For instance, side-by-side metal layouts can improve the figure-of-merit R_ds(on)·C_iss by up to 9.2% compared to layer-to-layer configurations by minimizing fringe effects on gate capacitance. In switched-capacitor circuits, where physical sizes are constrained by process limitations, capacitance multipliers leverage the gate-to-channel capacitance of MOSFETs to emulate larger effective capacitances, enabling compact implementations of filters and converters without excessive area overhead. As nodes scale below 5 nm, traditional reductions in gate capacitance (C_g) face fundamental challenges, stalling progress aligned with due to increasing parasitic components from tighter pitches. High-k/metal stacks, initially introduced to enable (EOT) scaling to ~0.9 nm at the 32 nm node, have reached physical limits, with further thinning exacerbating quantum tunneling and variability. To sustain performance in this regime, designers increasingly rely on the EKV model, a charge-based compact framework that accurately captures subthreshold operation for ultra-low-power circuits, allowing optimization of drive current despite diminished C_g scaling. Gate capacitance also drives reliability considerations in , particularly through time-dependent (TDDB) in thin gate oxides, where high accelerate defect generation and reduce device lifetime. TDDB lifetime models, such as the 1/E model, typically express \tau_{TDDB} \propto e^{\gamma / E_{ox}}, where E_{ox} = V_g / t_{ox} is the oxide , reflecting the field's in anode injection and creation. This necessitates voltage and conservative scaling of operating V_g to achieve 10-year lifetimes, impacting overall circuit margins and power budgets. Looking ahead, capacitance engineering in emerging devices addresses scaling limits by exploring 2D materials like MoS_2 for transistors, where quantum capacitance effects enable tunable channel control and reduced short-channel variability. Negative capacitance field-effect transistors (NCFETs), incorporating ferroelectric layers such as HfO_2 or P(VDF-TrFE), amplify effective gate capacitance beyond classical limits by stabilizing the negative dP/dE region in the ferroelectric, resulting in sub-60 mV/dec subthreshold swings and enhanced energy efficiency. In MoS_2-based NCFETs, this approach has demonstrated swings as low as 24.2 mV/dec, paving the way for low-power logic beyond silicon CMOS.