Open collector
An open collector is an output configuration in electronic circuits, commonly used in logic gates, buffers, and drivers, where the collector terminal of an NPN bipolar junction transistor is left unconnected within the device, enabling the output to sink current to ground (logic low) but not source current, thus requiring an external pull-up resistor to produce a logic high state.[1] This design functions like a single-pole single-throw (SPST) switch to ground, with the transistor turning off for a high output (pulled up by the resistor to the supply voltage) and turning on for a low output (pulling the line to near ground potential).[1] Open collector outputs are particularly advantageous for level shifting between different voltage domains, as the pull-up resistor can connect to a supply higher than the device's own voltage (e.g., up to 36 V in some comparators), and for implementing wired-OR or wired-AND logic by connecting multiple outputs in parallel without conflict, since all can only pull low.[1] They are widely applied in system error buses, memory address drivers, LED driving, relay control, and interfacing incompatible circuits, such as connecting low-voltage logic to high-current loads like solenoids or lamps.[1][2] A key limitation is the need for an external pull-up resistor (typically 100–10,000 Ω), which affects rise time based on capacitive loading, and the inability to source current, distinguishing it from push-pull outputs.[1] In modern contexts, the term is sometimes used interchangeably with open drain for MOSFET-based equivalents, though open collector specifically refers to bipolar transistor implementations.[3]Core Concepts
Definition and Operation
An open collector is a transistor output configuration, typically employing an NPN bipolar junction transistor (BJT), in which the collector terminal remains unconnected internally to any load resistor or supply, enabling an external pull-up resistor to establish the high logic level. This design allows the output to interface with various voltage levels and loads beyond the internal circuit's capabilities.[2] The basic circuit features an NPN transistor with its emitter tied to ground, the base controlled by a logic input signal that biases it above approximately 0.7 V to turn it on, and the collector serving as the output pin, to which an external pull-up resistor (typically in the range of hundreds to thousands of ohms) connects to the positive supply voltage, Vcc. When the input signal turns the transistor off, the output floats and is pulled high by the resistor to near Vcc; when on, the transistor saturates, sinking current through the load to ground and driving the output low, with the collector-emitter saturation voltage (V_CE(sat)) around 0.2 V and current limited by the transistor's rating, such as up to 40 mA in TTL implementations.[2][4] This configuration originated in early transistor-transistor logic (TTL) families, notably the 7400 series developed by Texas Instruments and introduced in October 1966, where open collector outputs facilitated wired-OR logic and flexible interfacing in digital systems.[5]Schematic Symbol
The standard IEEE/ANSI symbol for an open collector output, as defined in IEEE Std 91-1984, depicts an NPN transistor configuration using a qualifying symbol attached to the output pin of a logic gate or buffer. This symbol consists of a diamond shape representing the transistor, with a horizontal bar below it to indicate sink (low-side) behavior when active, and the collector terminal left unconnected internally to emphasize the open nature. An arrow at the emitter points toward ground, and the symbol is often accompanied by a textual note such as "open collector" or "OC" for clarity.[6][7] Variations exist across notation standards; in European conventions per IEC 60617, the symbol explicitly shows the NPN transistor with the collector pin left open as a straight line extending from the device without internal connection to the supply, distinguishing it from fully connected configurations. Some schematic diagrams include an external pull-up resistor connected to the open collector terminal for visualization, though this is not part of the core symbol itself.[8] This symbol differs from the standard totem-pole (push-pull) output representation, which illustrates both an upper PNP transistor (for sourcing) and a lower NPN transistor (for sinking) stacked vertically within the output stage, highlighting the bidirectional drive capability without an open terminal.[6]Related Configurations
Open Emitter
The open emitter configuration utilizes a PNP bipolar junction transistor (BJT) as a variant of the open collector, with the emitter connected to the positive supply voltage (Vcc) and the collector serving as the open output terminal. This arrangement enables the transistor to source current to an external load when activated, in contrast to the current-sinking behavior of a standard NPN open collector. An external pull-down resistor connected from the output to ground is essential to establish the low logic level when the transistor is inactive, preventing the output from floating indefinitely.[9][10] In operation, the PNP transistor is turned off when the base-emitter junction is reverse-biased (base voltage higher than emitter minus approximately 0.7 V), allowing the pull-down resistor to draw the collector output low toward ground. To activate the transistor, the base is driven low relative to the emitter, saturating the device and connecting the collector to Vcc through a low-resistance path (typically 0.2 V drop), thereby sourcing current to the load and pulling the output high. Current sourcing in this setup is generally limited compared to sinking capabilities in NPN open collectors, often constrained by the PNP's lower gain and higher saturation voltage, typically limited to 50 mA or less for common integrated devices.[11][2][12][13] This configuration is rare in contemporary electronics, primarily appearing in older complementary logic systems or high-side switching scenarios where sourcing current directly from the supply rail is advantageous for driving loads referenced to ground.[14] A basic circuit example features the PNP transistor's emitter tied to Vcc (e.g., +5 V), the collector as the output pin connected to the load (such as an LED or relay) in series with a pull-down resistor (e.g., 10 kΩ) to ground, and the base driven by a logic signal or resistor network that pulls low (e.g., to 0 V) to turn on the transistor and source current through the load.[11][15]Open Drain
The open drain configuration employs an NMOS transistor as the output stage, with the drain terminal connected to the output pin, the source tied to ground, and the gate controlled by the internal logic signal, necessitating an external pull-up resistor to achieve the logic high state.[16] This setup became prevalent in CMOS integrated circuits starting in the early 1980s, mirroring the sinking behavior of open collector outputs but using field-effect transistors instead of bipolar junction transistors.[17] In operation, a high gate voltage turns on the NMOS, shunting the output to ground for a logic low state, while a low gate voltage turns it off, allowing the output to float and be pulled high by the external resistor.[16] Many open drain outputs exhibit voltage tolerance exceeding the device's supply rail, permitting pull-up to higher levels such as 5 V when operating from a 3.3 V supply, which facilitates level shifting without additional circuitry.[18] Compared to bipolar junction transistor-based open collector outputs, open drain configurations in CMOS offer lower static power dissipation due to the absence of continuous base current and are more suitable for low-voltage applications owing to the voltage-driven nature of MOSFETs.[19] The adoption of open drain outputs marked a key transition from TTL logic families, which relied on open collector bipolar designs, to CMOS equivalents like the 74HC series introduced in 1983, providing comparable speed with significantly reduced power consumption and compatibility via TTL-level inputs in variants like 74HCT.[17][20]Open Source
The open source configuration utilizes a p-channel MOSFET (PMOS) where the source terminal serves as the output pin, with the drain internally connected to the positive supply voltage (VDD), enabling high-side switching. This setup allows the output to connect to VDD when the transistor is active, sourcing current to an external load. An external pull-down resistor is required to define the low logic state when the PMOS is off, as the output then enters a high-impedance (floating) condition. In operation, applying a low voltage to the gate (relative to the source) turns the PMOS on, conducting current from VDD through the channel to the output, effectively pulling it high for active-high signaling. When the gate voltage rises sufficiently (typically near VDD), the transistor turns off, isolating the output from VDD and allowing the pull-down resistor to bring the line low. This mirrors the sourcing behavior of an open emitter configuration in PNP bipolar junction transistors. The design supports wired-OR logic in multi-device systems, where any active device can drive the bus high while inactive devices remain passive. Open source outputs are less prevalent than open drain counterparts due to the inherently lower hole mobility in PMOS devices compared to electron mobility in NMOS, resulting in higher on-resistance and slower switching speeds—typically 2 to 3 times worse. However, PMOS-based open source configurations can provide superior voltage handling capabilities in certain integrated circuits, particularly for high-side applications where body diode characteristics aid in reverse current blocking.[21] In circuit examples, open source outputs appear in specialized bus systems requiring high-side drive, such as the Serial Encoder Interface (SEI) bus, where active-high signaling uses an open-source output pulled down externally to ground for reliable multi-drop communication.[22]Comparison of Configurations
Summary Overview
Open collector and its related configurations—open emitter, open drain, and open source—represent output stages in integrated circuits where a specific transistor terminal remains unconnected internally, enabling external resistors to define the logic high state while the transistor actively drives the low or high state.[2] These configurations originated with bipolar junction transistor (BJT)-based transistor-transistor logic (TTL) in the 1960s, which popularized open collector outputs for their ability to interface with higher voltages and enable wired-AND logic.[23] Over time, as complementary metal-oxide-semiconductor (CMOS) technology advanced in the 1970s and beyond, MOSFET-based variants like open drain became prevalent in modern low-power integrated circuits due to reduced static power consumption and scalability.[24] In terms of electrical ratings, open collector outputs in TTL typically sink up to 40 mA of current while tolerating voltages up to 30 V, exceeding the standard 5 V supply to support interfacing with diverse systems.[4] Similar capabilities apply to open drain in CMOS, though ratings vary by device, often handling higher voltages in low-power applications without the base current requirements of BJTs.[1] The following table summarizes the key configurations for quick reference:| Configuration | Transistor Type | Active Behavior | Typical Logic Families |
|---|---|---|---|
| Open Collector | BJT (NPN) | Sink (pulls output low) | TTL |
| Open Emitter | BJT (NPN) | Source (pulls output high) | ECL (Emitter Coupled Logic) |
| Open Drain | MOSFET (NMOS) | Sink (pulls output low) | CMOS, NMOS |
| Open Source | MOSFET (PMOS) | Source (pulls output high) | PMOS, CMOS |