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Quantum volume

Quantum volume is a metric that quantifies the performance of near-term quantum computers by measuring the largest size of random square circuits—equal in width (number of qubits) and depth (number of gate layers)—that a device can execute with sufficient fidelity to produce the expected output distribution. Introduced by IBM researchers in 2019, it serves as an architecture-neutral benchmark for noisy intermediate-scale quantum (NISQ) devices, capturing the interplay of qubit count, gate error rates, circuit connectivity, and compilation efficiency in a single value, V_Q = 2^k, where k is the maximum integer for which such a circuit succeeds. To compute quantum volume, experiments generate ensembles of random circuits using the QuantumVolume library in Qiskit, consisting of m qubits, d layers of random two-qubit unitaries (with m/2 gates per layer), and single-qubit depth-3 circuits between layers, followed by random permutations to simulate full connectivity. Success is determined by the heavy output probability (HOP), the fraction of output bitstrings with the highest ideal probabilities; a circuit passes if the average HOP exceeds 2/3 over at least 100 trials, with statistical confidence above 97.7% (using a z-score of 2). The value of k is then min(m, d(m)), maximized over possible m, providing a pragmatic measure of usable quantum computation volume despite imperfect hardware.^[1] Since its proposal, quantum volume has become a key industry standard for tracking progress, with IBM's early systems achieving V_Q = 16 in 2019 and subsequent advancements pushing boundaries—such as Quantinuum's H2 system reaching V_Q = 2^{25} = 33,554,432 in September 2025—highlighting improvements in error mitigation and scaling. While it emphasizes practical NISQ capabilities, limitations include reliance on classical simulation for validation and assumptions of balanced width-depth scaling, prompting extensions like volumetric benchmarks for broader testing. This metric underscores the path from current noisy devices toward fault-tolerant quantum computing, influencing hardware design and algorithmic development across major players like IBM and Quantinuum.^[2]^[3]

Overview

Purpose and Significance

Quantum volume (QV) is defined as a single-number metric that quantifies the largest size of a square quantum circuit—characterized by equal width n (number of qubits) and depth d (number of layers of quantum operations)—that a quantum computer can execute successfully with high fidelity, such that the average heavy output probability (HOP)—the fraction of the most probable output bitstrings—exceeds 2/3 over multiple trials with high statistical confidence.^[4] This metric encapsulates multiple hardware aspects, including qubit count, gate fidelity, connectivity, and measurement errors, providing a holistic assessment rather than isolated figures of merit.^[4] The primary purpose of quantum volume is to facilitate fair and standardized comparisons across diverse noisy intermediate-scale quantum (NISQ) devices, moving beyond simplistic metrics like raw qubit numbers that fail to capture overall system performance.^[4] By incorporating factors such as two-qubit gate errors, readout errors, and crosstalk, QV evaluates how effectively a device can handle realistic workloads in the NISQ era, where noise limits computation without full error correction.^[4] Introduced in 2019 by IBM researchers amid the rapid proliferation of NISQ hardware, it addressed the need for a benchmark that reflects the compounded effects of hardware imperfections on computational utility.^[4] The significance of quantum volume lies in its role as a bridge between raw hardware capabilities and the execution of practical NISQ algorithms, such as the variational quantum eigensolver (VQE) for molecular simulations and the quantum approximate optimization algorithm (QAOA) for combinatorial problems.^[5] A higher QV indicates greater potential for running deeper and wider circuits required by these hybrid quantum-classical methods, thereby signaling progress toward useful quantum advantage in applications like chemistry and optimization.^[5] This metric thus guides hardware development priorities, emphasizing balanced improvements in fidelity and scalability over mere qubit scaling.^[4]

Relation to Quantum Computing Performance

Quantum volume serves as a key metric for assessing the overall usability of a quantum computer in executing quantum algorithms, particularly by quantifying the largest size of random square circuits that can be run with acceptable fidelity. This directly correlates with algorithm feasibility, as higher quantum volumes enable more complex computations before errors dominate. For example, a quantum volume of $2^{10} = [1024](/page/1024) allows for the reliable execution of circuits comprising 10 qubits and up to 10 layers of two-qubit gates, which is adequate for basic simulations in quantum chemistry, such as approximating molecular ground states via variational quantum eigensolvers (VQE).^[6]^[7] In the noisy intermediate-scale quantum (NISQ) era, quantum volume facilitates benchmarking for practical applications where circuit depth is severely limited by noise accumulation. It evaluates system performance in tasks like ground state energy calculations for small molecules or combinatorial optimization problems, providing a standardized way to gauge whether a device can support hybrid quantum-classical workflows without excessive post-processing overhead.^[7] By capturing the interplay of circuit width, depth, and error thresholds, quantum volume highlights the practical utility of NISQ hardware for these error-prone yet valuable computations.^[6] Achieving higher quantum volumes involves inherent trade-offs between scaling the number of qubits and maintaining high coherence times and gate fidelities. For instance, expanding qubit counts without parallel improvements in error mitigation techniques can diminish the effective quantum volume, as increased connectivity and crosstalk exacerbate noise in deeper circuits.^[6] This balance underscores the need for holistic hardware-software co-design to push beyond current limitations.^[7] Broader implications of quantum volume extend to forecasting pathways toward quantum advantage, where it acts as an indicator of a system's readiness for demonstrating computational superiority in hybrid setups. Companies such as IBM leverage quantum volume milestones to guide investment and roadmap planning, targeting enhanced fidelity for fault-tolerant scaling in applications spanning materials science and optimization.^[7] Similarly, metrics like quantum volume inform strategic decisions at firms like Quantinuum, aligning hardware advancements with the pursuit of scalable, advantage-yielding quantum processors.^[8]

Formulation

Original Definition

Quantum volume was originally proposed in 2018 by N. Moll and colleagues as a single-number metric to assess the capability of noisy intermediate-scale quantum (NISQ) devices in executing useful quantum circuits.^[9] The metric aims to quantify the largest "useful" volume of quantum circuits—defined as the product of circuit width and depth—that a device can reliably execute before errors dominate and render the computation ineffective, thereby highlighting key limitations in NISQ-era hardware. The formulation assumes square circuits where width equals depth, employs random two-qubit gates drawn from a uniform distribution over all possible pairs of qubits (assuming full connectivity), and defines success theoretically as maintaining output fidelity above 2/3 before errors dominate, based on error propagation models.^[9] Under these conditions, the core equation for quantum volume V_Q is given by

V_Q = \max_{n < N} \left[ \min \left( n, \frac{1}{n \varepsilon_{\text{eff}}(n)} \right) \right]^2,

where N is the total number of physical qubits available on the device, n is the circuit width (and depth), and \varepsilon_{\text{eff}}(n) represents the effective error rate per two-qubit gate in n-qubit circuits, incorporating both gate errors and readout inaccuracies. The derivation stems from error propagation models in random circuits, where the effective depth d achievable before the output fidelity drops below the 2/3 threshold is approximated as d \approx 1 / (n \varepsilon_{\text{eff}}(n)), accounting for the accumulation of errors across O(n^2 d) two-qubit gates in an n \times d circuit. Quantum volume then emerges as the square of the minimum between this effective depth and the width n, maximized over feasible n < N, providing a volume-like measure that balances qubit count against error susceptibility. This original definition laid the groundwork for benchmarking NISQ systems, though subsequent refinements by hardware providers like IBM adapted it for practical scalability.

IBM's Redefinition

In 2019, IBM researchers refined the quantum volume metric to better capture the performance of near-term quantum devices, as detailed in the work by Cross et al.^[10] The updated formulation expresses quantum volume on a logarithmic scale, defined as \log_2 V_Q = \arg\max_{n \leq N} \min [n, d(n)], where N is the number of available qubits, n is the number of qubits used in the circuit, and d(n) represents the maximum circuit depth achievable for n-qubit circuits with a success probability exceeding $2/3 in the heavy output generation task.^[10] This yields V_Q = 2^k, where k is the integer value of the logarithm, emphasizing exponential growth in computational capability. A primary change in this redefinition is the adoption of the logarithmic scale, which aligns quantum volume directly with the complexity of classical simulation: simulating a quantum volume V_Q = 2^k requires approximately k^3 2^k operations on a classical computer.^[10] This linkage provides a concrete benchmark for when quantum advantage becomes feasible, moving beyond the original metric's simpler product of width and depth.^[10] The protocol integrates randomized model circuits composed of single-qubit rotation gates and two-qubit entangling gates, designed to stress-test the full system including compilation and execution.^[10] If the hardware lacks full qubit connectivity, the benchmark emulates it through additional swap gates, ensuring the metric reflects realistic algorithmic performance rather than topology limitations.^[10] This redefinition enhances comparability across devices by focusing on verifiable sampling success rates, mitigating the original metric's sensitivity to minor error fluctuations and promoting scalable benchmarking for evolving quantum hardware.^[10]

Measurement Process

Circuit Depth and Width

In the Quantum Volume benchmark, circuits are constructed as square architectures with width n (number of qubits) and depth d(n) (number of layers), where the goal is to balance width and depth.^[6] Each layer consists of a random permutation of the qubit labels followed by random two-qubit unitaries sampled from the Haar measure on SU(4), applied to n/2 disjoint pairs of qubits to create interactions.^[6] In implementations such as the Qiskit library, single-qubit gates (e.g., random rotations) may be inserted between two-qubit layers to increase circuit realism, with depth-3 single-qubit circuits between layers.^[1] These gates are selected randomly to generate diverse, representative circuits that probe the system's capabilities without favoring specific algorithms.^[6] The width n represents the number of qubits engaged in the circuit and is maximized up to the total available qubits N on the device, though hardware connectivity often imposes limits by necessitating additional operations.^[6] In devices without all-to-all connectivity, such as linear or grid topologies, swap gates must be inserted to route qubits for required two-qubit interactions, which increases the effective circuit depth and overhead.^[6] This connectivity constraint can reduce the feasible width, as swaps consume coherence time and amplify error accumulation.^[6] The random permutations before each layer help average over possible pairings, mitigating some connectivity issues. Circuit depth d(n) is defined as the maximum number of layers executable while maintaining sufficient fidelity for success, scaling upward with improved qubit coherence times but diminishing as n grows due to cumulative errors across more qubits and gates.^[6] For non-ideal topologies, the insertion of swaps further erodes achievable depth by extending the total gate count per layer.^[6] For example, on devices with limited connectivity like linear topologies, realizing full width requires multiple swaps to enable distant interactions, often capping d(n) below n and thus limiting the overall benchmark.^[6] IBM's Quantum Volume metric incorporates this interplay by taking $2^{\min[n, d(n)]}, emphasizing balanced performance in both dimensions.^[6]

Error Rates and Sampling Requirements

The effective error rate \epsilon_\text{eff} in quantum volume circuits quantifies the cumulative impact of gate and measurement errors on overall performance. It incorporates the average per-gate error rates, with typical two-qubit gate errors \epsilon_{2qg} \approx 0.5\%–$1\%, single-qubit gate errors \epsilon_{1qg} < 0.1\%, and readout errors \epsilon_\text{read} \approx 1\%–$5\%. For typical circuit models and topologies, the effective rate scales approximately as \epsilon_\text{eff}(n) \approx (a \sqrt{n} + b) \epsilon_{2qg}, where a \approx 1.29 and b \approx -0.78 for a square grid, reflecting routing overhead from connectivity.^[6] A key success criterion for validating quantum volume circuits is the fidelity threshold based on heavy output generation. The heavy outputs are the bitstrings with ideal probabilities greater than or equal to the median probability in the output distribution (roughly the most probable half of the $2^n bitstrings). The circuit is considered successful if the heavy output probability (HOP)—the measured probability of obtaining one of these heavy outputs—exceeds $2/3. This threshold robustly accounts for depolarizing noise, ensuring that the device's output distribution remains distinguishable from a fully mixed state.^[6] The sampling protocol estimates this heavy output probability with sufficient statistical confidence by executing ensembles of at least 100 randomized circuits, with each circuit run a number of shots scaling as $2^{n+2} to $2^{n+4} (e.g., 200–5000 total shots depending on n). Heavy output generation (HOG) enables this verification efficiently, avoiding the computational overhead of full quantum state tomography while confirming that the circuit preserves the intended non-uniform probability distribution. Success requires the average HOP > 2/3 with >97.7% confidence (z-score >2).^[6] Error mitigation techniques, such as readout error correction, can enhance the effective achievable depth d(n) by reducing measurement infidelity, thereby allowing slightly larger circuits to pass the fidelity threshold. However, quantum volume assessments demand unmitigated hardware performance to accurately gauge intrinsic device quality without post-processing aids.^[6] Practical scalability is limited by error accumulation; for a two-qubit gate error rate \epsilon_{2qg} = 0.01, the maximum n \approx 20 before errors dominate, even assuming low single-qubit and readout errors. This bound arises from the approximate relation d(n) \approx 1/(n \epsilon_\text{eff}), beyond which circuit fidelity drops below the required threshold.^[6]

Historical Achievements

Early Milestones (2018–2022)

The Quantum Volume (QV) metric, introduced by IBM in 2019, enabled the first systematic benchmarking of near-term quantum hardware, with early demonstrations relying on small-scale superconducting qubit systems. In 2018, IBM retrospectively calculated a QV of 8 (2^3) for its conceptual benchmarks on simulated 3-qubit circuits, reflecting initial explorations of circuit depth and fidelity limits.^[11] On physical hardware, early 5-qubit devices like the IBM Q experience achieved QV values of 2 to 4, constrained by high error rates and limited connectivity in these prototype superconducting transmon qubits.^[11] By 2019, advancements in gate fidelity and calibration allowed IBM's 20-qubit Johannesburg processor to reach a QV of 16 (2^4), marking the first hardware demonstration under the formalized metric and highlighting improvements in two-qubit gate performance.^[12] This milestone coincided with IBM's redefinition of QV to incorporate practical sampling thresholds, facilitating more reliable benchmarks on noisy intermediate-scale quantum (NISQ) devices. In January 2020, IBM's 28-qubit Raleigh system, featuring an enhanced hexagonal lattice for better qubit connectivity, attained a QV of 32 (2^5), doubling the previous year's record through optimized error mitigation and faster execution times.^[13] Later that year, upgrades to the 27-qubit Falcon processor pushed QV to 64, demonstrating scalable circuit execution up to moderate depths.^[14] Meanwhile, Google's 53-qubit Sycamore processor, while achieving quantum supremacy in random circuit sampling tasks, did not formally report QV but explored analogous fidelity and depth metrics in its superconducting architecture. IBM continued its progress in 2021 with the 27-qubit Montreal (Falcon r5) system reaching a QV of 128 (2^7), enabled by refinements in dynamical decoupling and readout error correction that extended coherent circuit depths.^[15] In March 2021, Quantinuum's H1 system, a trapped-ion precursor to later H-series models, demonstrated a QV of 512 on its 20-qubit configuration, showcasing all-to-all connectivity advantages over fixed superconducting layouts.^[16] Rigetti Computing's 80-qubit Aspen-M processor, a multi-chip superconducting design, emphasized modular scaling despite challenges in inter-chip coherence.^[17] In 2022, IBM's Falcon r10 processor achieved a QV of 512 (2^9), driven by heavy-hex lattice topology and improved single-qubit gate fidelities exceeding 99.9%.^[18] IBM also unveiled its 127-qubit Eagle processor, advancing scale but with QV performance aligned to ongoing Falcon improvements.^[19] Throughout this period, superconducting qubits dominated early QV achievements due to their rapid fabrication cycles and integration with cryogenic infrastructure, with IBM leading demonstrations on platforms accessible via the cloud. However, QV growth trailed exponential increases in qubit counts—such as from 20 to 127 qubits—primarily because error rates scaled unfavorably with system size, limiting effective circuit volumes to below 2^{10} despite architectural innovations.^[20]

Recent Advances (2023–2025)

In 2023, Quantinuum's H1-1 system, featuring 20 qubits, achieved a Quantum Volume of 524,288 (2^{19}) in June, marking a significant leap in trapped-ion quantum computing performance.^[21] Meanwhile, IBM's Prague processor reached a Quantum Volume of 512 (2^9), highlighting continued refinements in superconducting systems.^[22] By 2024, Quantinuum advanced further to a Quantum Volume of 1,048,576 (2^{20}), driven by enhancements in gate fidelity and error mitigation techniques.^[23] IonQ's Aria system, with 25 qubits, reported 25 algorithmic qubits (#AQ 25), underscoring competitive strides in trapped-ion architectures for reliable circuit execution.^[24] In 2025, Quantinuum's H2-1 processor, scaling to 56 qubits, attained a Quantum Volume of 8,388,608 (2^{23}) in May, demonstrating exponential progress through improved coherence times.^[8] IBM's Heron processor, with 133 qubits, focused on modular scaling for quantum-centric supercomputing.^[25] By September, Quantinuum's H2-2 variant, also at 56 qubits, set a new record with a Quantum Volume of 33,554,432 (2^{25}), enabled by reducing two-qubit gate error rates to below 0.1%.^[3] As of November 2025, no systems have surpassed the H2-2 record, with industry attention increasingly shifting toward utility-scale demonstrations beyond Quantum Volume metrics, though H2-2 remains the benchmark leader.^[26] This period reflects a notable shift, where trapped-ion platforms like those from Quantinuum and IonQ have outperformed superconducting approaches, such as IBM's, primarily due to superior qubit coherence and lower error accumulation in deeper circuits.^[26]

Extensions and Alternatives

Volumetric Benchmarks

Volumetric benchmarks extend the quantum volume metric to rectangular quantum circuits, where the number of qubits n (width) and circuit depth d are uncoupled, enabling a more nuanced evaluation of hardware performance across diverse circuit shapes.^[2] This generalization addresses the limitations of the square-circuit assumption in standard quantum volume by allowing the exploration of trade-offs between spatial and temporal resources, which is crucial for mapping practical algorithms that may require either broad parallelism or extended sequential operations.^[2] The methodology involves executing test suites of random or structured circuits \mathcal{C}(n, d) for various pairs of n and d, assessing success based on criteria such as ideal outcome probabilities exceeding 2/3 after error mitigation.^[2] Feasible (n, d) pairs are plotted in a two-dimensional space, with the "volumetric frontier" defined as the Pareto envelope of points representing the boundary of reliable performance; points below this frontier indicate regions where the device fails to meet the success threshold.^[2] Unlike the single scalar value of quantum volume, this frontier provides a visual and quantitative profile, where an effective volume can be approximated as n \times d along frontier points to gauge overall capacity without reducing to a solitary metric.^[2] These benchmarks reveal hardware-specific strengths, such as superior performance in high-depth, low-width regimes for time-series analysis algorithms or high-width, low-depth setups for quantum simulation tasks, aiding in optimal algorithm-to-hardware mapping.^[2] For instance, a device achieving a quantum volume of $2^{10} might support rectangular circuits like n=20, d=2 for wide simulations or n=5, d=20 for deeper computations, informing practical deployments.^[2] Since 2023, companies like Quantinuum have incorporated volumetric benchmarks in their evaluations to demonstrate beyond-square capabilities, integrating them with traditional quantum volume for comprehensive hardware profiling.^[27]

Comparisons to Other Metrics

Quantum volume (QV) differs from simple qubit counts by incorporating error rates and circuit depth, thereby penalizing systems with high noise levels; for instance, a device with 100 low-fidelity qubits might yield a lower QV than one with 20 high-fidelity qubits, emphasizing quality over mere scale.^[6] This approach addresses the limitations of raw qubit metrics, which can mislead assessments of practical utility in noisy intermediate-scale quantum (NISQ) devices.^[28] In contrast to randomized benchmarking (RB), which quantifies average gate fidelity—such as 99.9% for two-qubit gates—without evaluating full-circuit performance, QV integrates RB-derived error rates (like effective error per gate, ε_eff) into a broader assessment of scalable circuit execution.^[6]^[29] While RB provides a foundational measure of gate reliability, it lacks insight into system-wide factors like connectivity and crosstalk that QV captures holistically. CLOPS (Circuit Layer Operations Per Second) focuses on execution throughput for deep circuits, measuring how rapidly a processor handles layers of quantum operations, whereas QV prioritizes circuit quality and fidelity over speed.^[28] These metrics are complementary: QV assesses the complexity of reliable circuits, while CLOPS evaluates runtime feasibility, together informing overall system utility for practical applications.^[30] QED-C benchmarks, introduced in 2023 and expanded through 2025, establish cross-platform standards by computing medians over ensembles of submissions for tasks like Hamiltonian simulation, incorporating QV as one of its core metrics for device comparability.^[31]^[32] Unlike the device-specific nature of QV, QED-C emphasizes standardized, application-oriented evaluations, blending QV-like volumetric elements with broader algorithmic tests to enable fair inter-vendor comparisons.^[33] QV has notable limitations in comparisons to other metrics, as it overlooks runtime overheads, cryogenic cooling requirements, and integration challenges, focusing solely on circuit executability rather than operational efficiency.^[34] It is particularly suited to NISQ-era evaluations but less relevant for fault-tolerant quantum computing, where metrics like logical qubit fidelity become paramount for error-corrected operations.^[35] By 2025, hybrid benchmarking combining QV, RB, and CLOPS has become standard practice, providing a multifaceted view of quantum hardware performance. For example, Quantinuum's System Model H2 achieved a QV of 2^{25} (33,554,432) alongside top-tier RB scores, including 99.921% two-qubit gate fidelity, demonstrating alignment between volumetric scale and gate-level reliability.^[36]^[8]

Limitations

Conceptual Shortcomings

The quantum volume metric is predicated on the assumption that Haar-random quantum circuits provide a representative benchmark for overall system performance, yet this overlooks the distinct error profiles and structures of practical algorithms. Random circuits, drawn from a uniform distribution over SU(4) unitaries, tend to be more sensitive to noise than structured algorithms like the quantum approximate optimization algorithm (QAOA), potentially overestimating a device's utility for real-world applications that tolerate errors differently.^[37]^[38] A key conceptual bias in quantum volume arises from its emphasis on square circuits, where the number of qubits equals the number of gate layers, which does not align with the rectangular shapes required by many quantum algorithms that demand greater depth relative to width. While extensions like volumetric benchmarks address some rectangular needs, the core quantum volume remains a single-point measure that inadequately represents these diverse circuit geometries.^[38] The metric also inadequately models qubit connectivity, incorporating only partial adjustments for swap overhead due to hardware topology, while assuming an idealized all-to-all connectivity that is rarely achieved in practice. This oversight can lead to inflated estimates of performance on devices with sparse or fixed connectivity graphs.^[38] Scalability poses another theoretical limitation, as the logarithmic scale of quantum volume (log₂ QV = k) advances slowly with hardware improvements and fails to indicate transitions toward fault-tolerant regimes or the integration of hybrid error-correction schemes. It remains tied to noisy intermediate-scale quantum (NISQ) assumptions, without capturing the qualitative shifts needed for scalable, error-corrected computing.^[39] Interpretability is hindered by the exponential formulation, where values like 2^{25} convey scale but obscure practical implications, such as whether the system can execute meaningful algorithms without extensive error mitigation. Community analyses often recommend quoting log₂ QV for clarity, underscoring its abstract nature.^[38] Post-2020 literature has critiqued quantum volume for NISQ benchmarking, viewing it as a useful starting point for hardware comparison but insufficient as a comprehensive measure due to its hardware-centric focus and limited relevance to software or application-specific performance.^[39]^[38]

Practical Challenges

Achieving and verifying quantum volume involves substantial verification overhead, as the heavy hexagon sampling protocol requires thousands of shots per circuit configuration (n, d) to estimate heavy output probabilities with sufficient statistical confidence, typically demanding at least 1,000 shots to achieve 95% reliability in distinguishing non-uniform distributions. This process becomes time-intensive, with complete benchmarking for a single quantum volume value often spanning hours to days on accessible hardware, exacerbated by queue delays on cloud platforms and the need for multiple circuit subsets. Statistical noise poses an additional risk, potentially invalidating entire runs if the signal-to-noise ratio is low, necessitating repeated executions to ensure robust results.^[40]^[41]^[42] Hardware variability further complicates quantum volume measurements, as the metric is highly sensitive to environmental factors like cryogenic drifts, where coherence times in superconducting qubits can fluctuate suddenly over hours or days despite stable millikelvin temperatures, degrading circuit fidelity. Crosstalk between adjacent qubits introduces correlated errors that propagate through random circuits, amplifying deviations from ideal outputs. For example, 2025 achievements on stable trapped-ion systems, such as Quantinuum's H2 processor, outperformed fluctuating superconducting architectures by maintaining consistent performance under these conditions.^[43]^[44]^[8] Reproducibility across devices remains a key barrier, stemming from vendor-specific protocols that differ in gate implementations and qubit connectivity; IBM's superconducting QPUs, for instance, rely on transmon-based two-qubit gates, while Quantinuum's ion traps use native all-to-all connectivity, leading to discrepancies in quantum volume outcomes even for comparable hardware scales. The absence of standardized software for optimizing swaps and routing in diverse topologies fuels debates over fair comparisons, as seen in multi-vendor benchmarking studies evaluating up to 156 qubits.^[45] Conducting full quantum volume assessments demands extensive cloud access, particularly on platforms like IBM Quantum, where benchmarking consumes significant quantum execution time under pay-as-you-go or subscription models, with costs accruing per job and limiting availability for non-premium users such as academic groups. This resource intensity restricts widespread replication, as queue priorities favor enterprise access over exploratory runs.^[46] As of 2025, quantum volume continues to serve as a key benchmark for tracking hardware progress, with records such as Quantinuum's H2 system achieving 2^{25} = 33,554,432 in September 2025, though there is growing interest in application-specific benchmarks and scalable alternatives that better capture practical utility beyond exhaustive QV evaluations.^[47]^[8]^[3] Mitigation efforts include emerging automated tools like the Benchpress suite, which streamline circuit generation and execution for quantum volume tests, reducing manual overhead and improving consistency. However, challenges persist at scales beyond 100 qubits, where amplified noise and verification demands continue to hinder reliable benchmarking.^[48]

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Our analysis highlighted the shortcomings of hardware-oriented metrics, such as Quantum Volume (QV) and CLOPS, and examined how COSMIC-based approaches can ...
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Benchmarking quantum computers - Nature Reviews Physics
### Critiques of Quantum Volume from the Review Paper
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https://pmc.ncbi.nlm.nih.gov/articles/PMC9601621/
[38]
Automated Quantum Volume Test - IOPscience
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[39]
Increasing the Measured Effective Quantum Volume with Zero Noise ...
Jun 28, 2023 · ZNE is an error mitigation technique that estimates the noiseless expectation value using circuit folding to amplify errors by known scale factors.
[40]
Materials challenges and opportunities for quantum computing ...
Apr 16, 2021 · The coherence times can drift or change suddenly over hours and days, even while the device is held at cryogenic temperatures (89, 95, 126, 127) ...Missing: variability | Show results with:variability
[41]
Detecting crosstalk errors in quantum information processors
Sep 11, 2020 · In this paper, we introduce a comprehensive framework for crosstalk errors and a protocol for detecting and localizing them.Missing: variability cryogenic
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Evaluating the performance of quantum processing units at large width and depth
### Summary of Benchmarking and Reproducibility Issues from arXiv:2502.06471
[43]
Manage cost on the Pay-As-You-Go Plan - IBM Quantum Platform
How to manage costs of running jobs on QPUs when using the Pay-As-You-Go Plan on IBM Quantum Platform.
[44]
Researchers Propose Scalable Alternative to Quantum Volume ...
Feb 11, 2025 · Researchers propose a modified Quantum Volume test that eliminates the need for classical simulations, addressing scalability challenges.Missing: shift specific
[45]
Benchmarking the performance of quantum computing software for ...
Apr 18, 2025 · We present Benchpress, a benchmarking suite for evaluating the performance and range of functionality of multiple quantum computing software development kits.