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Scratchpad memory

Scratchpad memory (SPM), also known as scratchpad RAM or local store, is a high-speed on-chip static random-access memory (SRAM) that is explicitly managed by software, allowing programmers or compilers to directly allocate and access data without hardware intervention.^[1] Unlike caches, which rely on automatic hardware mechanisms for data eviction and coherence, SPM operates in a distinct address space with fixed access latencies, enabling predictable performance in time-critical applications.^[2] Gaining prominence as a viable alternative to caches in embedded systems during the early 2000s, SPM addresses the limitations of cache overheads by eliminating complex tag comparison and miss detection circuitry.^[1] It provides significant efficiency gains, including average energy reduction of 40% and area savings of 34% compared to equivalent cache configurations, making it ideal for power-constrained devices such as mobile phones, digital signal processors, and wireless communication systems.^[1] In modern architectures, SPM remains prominent in multicore processors and specialized accelerators, particularly for deep neural networks, where explicit data management facilitates reuse buffers and minimizes off-chip memory accesses, achieving performance improvements of up to three orders of magnitude over traditional CPU-based processing.^[3] Its software-controlled nature supports compiler optimizations and dynamic allocation techniques, enhancing applicability in real-time and domain-specific computing environments, including recent advancements in neural processing units and GPU architectures as of 2025.^[2]^[4]

Fundamentals

Definition and Characteristics

Scratchpad memory is a high-speed, software-managed on-chip static random access memory (SRAM) that serves as temporary storage for data and instructions directly accessible by the processor core.^[5] Unlike caches, it lacks automatic hardware mechanisms for data placement and eviction, requiring explicit programmer or compiler control to load and unload content.^[6] This design positions scratchpad memory within the memory hierarchy between processor registers and main memory, facilitating low-latency access to critical program elements in embedded and resource-constrained systems.^[5] Key characteristics of scratchpad memory include its fixed capacity, typically ranging from 1 KB to 512 KB, which supports direct addressing without the need for tag arrays or associativity logic found in caches.^[5] Access times are highly predictable, as there are no miss penalties or coherence overheads; every valid address within the scratchpad yields a deterministic hit latency, often comparable to or better than L1 cache access due to simplified circuitry.^[7] This predictability stems from the absence of hardware-managed replacement policies, making it particularly suitable for real-time applications where timing guarantees are essential.^[6] In distinction from general-purpose memory structures, scratchpad memory focuses on minimizing latency for frequently accessed data in power- and area-limited environments, such as embedded processors, by integrating seamlessly as a software-controlled buffer.^[5] Its basic operational principle involves explicit data movement via software instructions or direct memory access (DMA), ensuring that only selected program segments reside on-chip at any time and enabling fully deterministic execution without the variability introduced by cache misses.^[6]

Historical Development

The concept of scratchpad memory originated in the late 1950s and early 1960s as a form of fast, modifiable on-chip storage to support control functions in early computing systems. Honeywell pioneered its use with the H-800 system, announced in 1958 and first installed in 1960, which incorporated a 256-word core-based scratchpad for multiprogram control, enabling efficient task switching without relying solely on slower main memory.^[8] By 1965, Honeywell's Series 200 minicomputers integrated scratchpad memories of varying sizes (up to 64 locations) as control storage, offering access speeds 2 to 6 times faster than main memory to enhance throughput in business applications.^[8] A significant milestone came in 1966 with the Honeywell Model 4200 minicomputer, which utilized the TMC3162, a 16-bit bipolar TTL scratchpad memory developed by Transitron and second-sourced by multiple manufacturers including Fairchild, Sylvania, and Texas Instruments; this marked one of the first commercial semiconductor implementations of scratchpad for high-speed needs.^[9] The 1980s saw widespread proliferation of scratchpad memory in digital signal processors (DSPs) for real-time applications, driven by the need for deterministic performance in embedded systems. Texas Instruments' TMS320 series, launched in 1983, incorporated on-chip scratchpad RAM as auxiliary storage for temporary data, complementing program and data memories to enable high-speed filtering and processing without external memory delays.^[10] This design choice in the TMS32010 and subsequent models facilitated efficient algorithmic implementations in telecommunications and audio processing, establishing scratchpad as a staple in DSP architectures. During the 1990s and 2000s, scratchpad memory expanded into embedded and multicore systems, particularly with the rise of power-constrained devices. A key example is the IBM Cell Broadband Engine, designed starting in 2001 through the STI alliance (IBM, Sony, Toshiba), which featured 256 KB of local store per Synergistic Processing Unit (SPU) as explicitly managed scratchpad memory to support parallel workloads in gaming and scientific computing.^[11] This architecture, first shipped in Sony's PlayStation 3 in 2006, demonstrated scratchpad's efficacy in reducing memory latency for vector operations across multiple cores. Post-2010 developments have integrated scratchpad into graphics processing units (GPUs) and explored hybrid designs for improved energy efficiency. NVIDIA's GPU architectures, such as those in the Kepler series from 2012 onward, treat shared memory as a configurable scratchpad, allowing programmers to allocate on-chip SRAM explicitly for thread-block data sharing, enhancing performance in parallel compute tasks.^[12] Concurrent research has focused on hybrid cache-scratchpad systems, where portions of cache are dynamically repurposed as software-managed scratchpad to minimize energy consumption; for instance, adaptive schemes remap high-demand blocks to scratchpad, achieving up to 25% energy savings in embedded processors while maintaining hit rates.^[13]

Design and Operation

Software Management Techniques

Software management techniques for scratchpad memory (SPM) primarily involve explicit, compiler-directed, and dynamic strategies to allocate data and code, ensuring efficient use of this software-controlled on-chip storage. Explicit allocation requires programmers or compilers to specify placements using language directives, such as pragmas in C (e.g., #pragma scratchpad), or runtime application programming interfaces (APIs) that map variables or functions to SPM regions. This approach allows precise control over data placement based on access patterns, often formulated as an optimization problem solved via integer linear programming (ILP) to minimize access times by assigning global and stack variables to SPM while respecting capacity constraints. For instance, the ILP model uses binary variables to decide allocations, incorporating profile-guided access frequencies, and achieves up to 44% runtime reduction through distributed stack management in embedded systems.^[14] Compiler-based techniques leverage static analysis to automate SPM allocation, analyzing variable lifetimes, access frequencies, and interferences to map frequently accessed ("hot") data to SPM for performance gains. These methods profile program execution to identify liveness intervals and prioritize placements that reduce energy consumption, such as assigning basic blocks or functions to SPM banks, yielding up to 22% energy savings in embedded applications. Graph coloring extends this by modeling allocation as an interference graph where nodes represent data objects and edges denote overlapping lifetimes; colors correspond to SPM "registers" of fixed sizes, resolved via standard coloring algorithms adapted from register allocation to handle conflicts and ensure non-overlapping assignments. This technique partitions SPM into alignment-based units, splits live ranges at loop boundaries for better fit, and improves runtime by optimizing for smaller SPM sizes, as demonstrated in benchmarks like "untoast" where it enhances utilization without manual intervention.^[2]^[2]^[15] Dynamic allocation methods enable runtime adaptation, particularly in multitasking environments, using compiler-inserted code or operating system (OS) support to load and evict data based on heuristics like access costs and future usage predictions. These approaches construct a data-program relationship graph to timestamp memory objects and greedily select transfers from off-chip memory to SPM at program points, avoiding runtime overheads like caching tags while maintaining predictability. In pointer-based applications, runtime SPM management can reduce execution time by 11-38% (average 31%) and DRAM accesses by 61% compared to static methods, with optimizations for dead data exclusion further lowering energy by up to 31%. OS-level support may involve adaptive loading via system calls, ensuring portability across varying workloads.^[16]^[16] Tools and frameworks facilitate these techniques through integrated compiler passes and simulators. Compiler frameworks like LLVM incorporate SPM allocation passes that perform static analysis and graph-based optimizations during code generation, enabling seamless integration with build systems for hybrid memory management. For energy profiling, simulation tools such as CACTI model SPM access energies and leakage, providing estimates for design space exploration; it computes capacitances and power based on technology parameters, supporting evaluations that confirm SPM's 20-30% lower energy than caches for equivalent sizes. Additionally, methods handling compile-time-unknown SPM sizes use binary search or OS queries within compiler flows to generate portable binaries, maintaining near-optimal allocations across hardware variants.^[17]^[18]^[19] ===== END CLEANED SECTION =====

Performance Aspects

Advantages

Scratchpad memory provides deterministic access times, as data allocation is managed explicitly by software at compile time or runtime, eliminating the variability introduced by cache misses and hit/miss resolution hardware. This fixed latency is particularly beneficial for real-time systems, where worst-case execution time (WCET) guarantees are essential; techniques for WCET-centric allocation can reduce execution times by 5-80% compared to cache-based approaches by ensuring predictable memory behavior.^[20] In terms of energy efficiency, scratchpad memory consumes significantly less power than traditional caches due to the absence of tag lookups, comparators, and cache coherence mechanisms, with studies reporting average energy savings of 40% per access in embedded systems—for instance, 1.53 nJ for a 2 KB scratchpad versus 4.57 nJ for an equivalent cache. These savings arise from the simpler access path and reduced overhead, making scratchpad memory ideal for power-constrained environments like battery-operated devices.^[19] The hardware design of scratchpad memory is simplified, omitting complex caching logic such as tag arrays and replacement policies, which reduces die area by approximately 34% (e.g., 102,852 transistors for a 2 KB scratchpad versus 142,224 for a cache) and allows more silicon to be allocated to compute units. This streamlined architecture also contributes to overall system performance improvements of up to 18% in CPU cycles for embedded benchmarks.^[19] For bandwidth optimization, scratchpad memory enables high-throughput access to local data in parallel architectures, as direct addressing and DMA support facilitate efficient data movement without contention from global memory hierarchies; bandwidth-aware tiling techniques can achieve up to 4x performance gains by balancing space utilization and transfer rates in multi-core systems.^[21]

Disadvantages

Scratchpad memory imposes significant programmer overhead due to its requirement for explicit software management of data placement and movement, unlike hardware-managed caches that operate transparently. This manual or compiler-assisted allocation process increases development complexity and time, as developers must analyze access patterns and insert code for loading and evicting data, which can be error-prone and non-portable across different memory configurations.^[14]^[16] The limited capacity of scratchpad memory, often constrained to small sizes such as a few kilobytes in embedded systems, necessitates frequent data swapping between the scratchpad and slower off-chip memory for larger workloads, introducing performance overhead and reducing overall efficiency. This size restriction relegates less frequently accessed data to DRAM, exacerbating latency in applications with extensive datasets.^[22] Lack of transparency in scratchpad memory arises from the absence of automatic mechanisms like prefetching or eviction policies found in caches, placing the full burden of optimization on software and risking suboptimal utilization if tuning is inadequate. Without hardware support for coherence or hit/miss detection, programmers must explicitly handle all data transfers, which can lead to inefficiencies in unpredictable access patterns.^[23] Scalability issues in multicore environments stem from scratchpad memory's challenges in maintaining data coherency across cores, as it lacks built-in hardware protocols and requires additional software layers for synchronization, complicating management as core counts increase. This results in potential incoherence between local scratchpad copies and shared global memory, hindering efficient scaling in parallel workloads.^[24]

Comparisons

With Cache Memory

Scratchpad memory and cache memory represent two distinct approaches to on-chip memory management in processor architectures. While caches are hardware-managed with automatic data placement and eviction policies such as least recently used (LRU), scratchpad memory requires explicit software control for data allocation and deallocation, often handled by the compiler or programmer.^[5] This software-centric paradigm in scratchpad memory allows for precise optimization of memory usage tailored to application needs, whereas caches rely on hardware heuristics that may not align perfectly with specific workloads.^[25] In terms of access predictability, scratchpad memory provides guaranteed hit times since all allocated data resides directly in the memory without the need for tag comparisons or associative lookups, eliminating the risk of cache misses and related pollution effects where irrelevant data evicts useful content.^[5] Caches, by contrast, introduce variability in access latency due to potential misses, compulsory loads, and conflicts, which can lead to unpredictable execution times, particularly in real-time systems.^[26] Locked caches, a variant where specific lines are pinned to avoid eviction, improve predictability over standard caches but still incur overhead from hardware management and potential mapping conflicts.^[26] Regarding power consumption and area efficiency, scratchpad memory exhibits lower overhead because it lacks the tag arrays, comparators, and replacement logic required for caches, resulting in reduced energy per access—for instance, approximately 36% less energy for certain benchmarks like quicksort compared to equivalent caches.^[5] Caches demand significantly more silicon area, with direct-mapped or set-associative designs requiring up to five times the transistors of a scratchpad for the same capacity (e.g., 75,000 vs. 15,000 transistors for 128 bytes), and with caches consuming significantly more power, up to 67% more on average due to these additional circuits based on 40% energy savings for equivalent scratchpad configurations.^[1]^[25] This makes scratchpad memory particularly advantageous in resource-constrained environments where minimizing static power and die space is critical.^[5] Scratchpad memory is ideally suited for embedded applications with predictable, computationally intensive tasks such as multimedia processing or digital signal processing, where software can statically map frequently accessed data to ensure consistent performance.^[25] In contrast, caches excel in general-purpose computing scenarios characterized by irregular access patterns, such as desktop or server workloads, where hardware automation handles dynamic data locality without extensive programming intervention.^[5] These differences highlight scratchpad's role in optimizing for determinism and efficiency in specialized domains over the flexibility of caches.^[26]

With Other On-Chip Memories

Scratchpad memory differs from register files primarily in capacity and access characteristics. Register files typically provide limited storage, often on the order of 128 to 512 bytes per core (equivalent to 32-128 32-bit registers), serving as the fastest on-chip storage for immediate operand access.^[12] In contrast, scratchpad memory offers much larger capacities, ranging from 4 KB to 64 KB or more, enabling storage of larger data structures or temporary arrays that exceed register file limits.^[5] However, register files achieve near-zero latency access integrated directly into the execution pipeline, while scratchpad accesses incur 1-2 cycles due to their memory-like addressing and load/store operations.^[27]^[28] Compared to the local store in the IBM Cell processor, scratchpad memory shares the trait of being fully software-managed, requiring explicit data placement and transfers to avoid off-chip accesses. Both structures provide predictable, low-latency on-chip storage without hardware caching overheads. However, the Cell's local store is tightly integrated with its Synergistic Processing Elements (SPEs), limited to 256 KB per SPE and relying exclusively on DMA for data movement between main memory and the local store, emphasizing streaming workloads.^[29] General-purpose scratchpad memory, by contrast, supports broader applicability across processor architectures, often allowing direct load/store instructions without mandatory DMA, though it lacks the Cell's specialized vector processing optimizations.^[30] Scratchpad memory also contrasts with shared L2 caches in terms of access scope and overheads. As a private per-core structure, scratchpad provides dedicated, low-latency access (typically 1-2 cycles) without contention from other cores, making it suitable for localized data reuse.^[24] Shared L2 caches, however, serve multiple cores with higher average latencies (often 10-20 cycles) due to bank conflicts and directory-based coherency protocols, which introduce additional traffic for maintaining data consistency across cores.^[24] This eliminates coherency overheads in scratchpad designs but requires compiler or programmer intervention for data management. Emerging hybrid approaches integrate scratchpad memory with caching mechanisms to balance predictability and automation. For instance, designs like Stash enable software-managed scratchpad regions that are globally addressable like caches, supporting implicit data movement and lazy writebacks to reduce programming effort while preserving low-latency benefits. These hybrids have demonstrated up to 12% performance gains and 32% energy savings over pure cache or scratchpad systems in GPU workloads.^[31] More recent designs, such as COMPAD (2023) and M3D-MDA (2025), further integrate scratchpad and cache elements for improved energy efficiency in heterogeneous systems.^[32]^[33]

Applications

In Digital Signal Processors

Scratchpad memory found early adoption in digital signal processors (DSPs) during the 1980s, particularly in the Texas Instruments TMS320 series, where on-chip RAM served as a fast scratchpad for storing filter coefficients and data buffers in audio and video processing applications. For instance, the TMS32010 and TMS32020 utilized their limited on-chip data RAM—144 words for the TMS32010 and up to 544 words for the TMS32020—to hold coefficients for finite impulse response (FIR) filters (e.g., length-80 bandpass filters at 10 kHz sampling) and buffers for intermediate results in real-time tasks like echo cancellation and speech coding.^[10] These implementations enabled efficient processing of audio signals, such as 128-tap digital voice echo cancellers compliant with CCITT G.165 standards and linear predictive coding (LPC) vocoders at 8 kHz sampling, by keeping critical data on-chip to minimize external memory accesses.^[10] In DSP architectures, scratchpad memory is often integrated with dual-access ports to support simultaneous read and write operations, which is essential for real-time signal processing tasks requiring high data throughput. The Texas Instruments TMS320C54x family, for example, features Dual-Access RAM (DARAM) blocks that allow two independent accesses per instruction cycle, facilitating parallel instruction fetch and data manipulation without conflicts in applications like filtering and buffering.^[34] This design extends to later iterations, such as the TMS320C4x, where on-chip dual-access RAM enables efficient handling of operands in DSP algorithms, including matrix-vector multiplications and lattice filters, by organizing data into independent blocks for concurrent operations.^[35] The use of scratchpad memory in DSPs significantly enhances performance by enabling low-power, high-throughput operations, such as fast Fourier transform (FFT) computations, while avoiding stalls from slower dynamic random-access memory (DRAM). In the TMS320VC5505 DSP, for instance, on-chip scratchpad allocation for FFT data and twiddle factors supports 1024-point complex FFTs with active power consumption below 0.15 mW/MHz, allowing real-time processing in power-constrained environments like portable audio devices without external DRAM dependencies.^[36] This approach reduces energy overhead and latency, as demonstrated in early TMS32020 implementations where a 256-point complex FFT completed in 4.375 ms at 5 MHz entirely using on-chip RAM, prioritizing deterministic access over cache unpredictability.^[10] A notable example of scratchpad integration in modern DSPs is found in Analog Devices Blackfin processors, such as the ADSP-BF54x series, which include configurable 4K-byte scratchpad SRAM blocks within the Level 1 (L1) memory hierarchy for optimized data storage in signal processing. These blocks operate at full core clock speed and can be allocated for stack, local variables, or temporary buffers in real-time tasks, with configuration options via the L1 Data Memory Controller to ensure non-cacheable, low-latency access excluded from direct memory access (DMA) channels.^[37] In Blackfin architectures, the scratchpad supports efficient execution of DSP operations like multiply-accumulate instructions and circular buffering through data address generators, enhancing throughput for applications in audio and video signal handling.^[38] Recent advances (as of 2025) have extended scratchpad memory optimizations to modern DSP applications, including AI-enhanced signal processing on embedded processors. For example, heterogeneous SRAM-based scratchpad designs have been proposed to balance reliability and energy efficiency in low-voltage DSP tasks, achieving up to 2x improvements in fault tolerance for applications like video decoding.^[39]

In Embedded and Multicore Systems

Scratchpad memory (SPM) serves as a compelling on-chip storage solution in embedded systems, particularly for computationally intensive applications where power and area efficiency are paramount. Unlike caches, which rely on hardware-managed automatic replacement policies, SPM requires explicit software control for data and code placement, enabling designers to optimize for specific workloads. This approach has been shown to reduce energy consumption by an average of 40% compared to cache-based systems, primarily due to the absence of complex tag comparisons and associative lookups. Additionally, SPM offers a 46% reduction in area-time product, making it suitable for resource-constrained embedded devices such as microcontrollers and digital signal processors.^[5] In real-time embedded systems, SPM's deterministic access times enhance timing predictability, which is crucial for meeting hard deadlines without the variability introduced by cache misses or evictions. This predictability stems from SPM's fixed latency for all valid addresses, avoiding the non-deterministic behavior of caches in contended scenarios. Power savings further support its adoption, as SPM eliminates the energy overhead of cache coherence protocols, allowing for simpler hardware implementations that consume less dynamic power during accesses. For instance, dynamic SPM units have been proposed to adaptively manage memory allocation at runtime, balancing predictability with flexibility in evolving real-time tasks.^[40] Transitioning to multicore embedded systems, SPM extends its benefits to parallel architectures by facilitating efficient data sharing and locality management across cores, often in hybrid hierarchies combining SPM with caches or main memory. Runtime-guided management techniques leverage task dependencies to allocate data to SPM, overlapping transfers with computation and using locality-aware scheduling to minimize inter-core data movement. This results in performance improvements of up to 16% in 32-core configurations, alongside reductions in on-chip network traffic by 31% and power consumption by 22%, making SPM ideal for power-sensitive multicore SoCs in automotive and IoT applications.^[41] Shared SPM designs with ownership mechanisms enable time-predictable inter-core communication in multicore systems, where cores temporarily own portions of the SPM via time-division multiplexing to avoid contention. Such architectures ensure bounded worst-case execution times, critical for safety-critical embedded multicore platforms. Complementing this, scratchpad-centric operating systems (OS) for multicore environments arbitrate shared resources at the OS level, separating application logic from I/O operations temporally to achieve contention-free execution. These OS designs deliver up to 2.1× performance gains over traditional cache-based approaches while maintaining predictability for hard real-time tasks on commercial-off-the-shelf multicore hardware.^[42]^[43] In multicore embedded contexts, SPM also supports advanced features like data duplication and replication for fault tolerance, mitigating multi-bit upsets in radiation-prone environments without significant overhead. Optimal data allocation algorithms further enhance efficiency by solving placement problems in polynomial time for exclusive data copies across cores, reducing memory conflicts in concurrent software. Overall, these applications underscore SPM's role in enabling scalable, low-power multicore embedded systems where predictability and energy efficiency outweigh the management complexity.^[44]^[45] As of 2025, recent advances in embedded multicore systems include interactive dynamic SPM management strategies that improve allocation for multi-threaded applications, achieving up to 30% energy savings through compiler-directed transfers in heterogeneous many-core architectures. Additionally, integration of non-volatile memory (NVM) with SPM has enhanced energy efficiency and persistence in IoT and automotive multicore SoCs.^[46]^[47]^[48]

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