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SerDes

SerDes, short for Serializer/Deserializer, is a pair of functional blocks that converts parallel digital data into a serial stream for high-speed transmission and reconstructs it back into parallel form at the receiver, enabling efficient chip-to-chip and system-level communication with reduced pin counts and improved signal integrity.^[1] This technology forms a critical part of the physical layer (PHY) in communication protocols, incorporating components such as clock data recovery, impedance matching, encoding/decoding, and equalization to handle data rates from gigabits to hundreds of gigabits per second while minimizing power consumption and electromagnetic interference.^[1]^[2] Key to modern high-performance computing, SerDes supports standards including PCIe, Ethernet (up to 800 Gbps aggregate, with SerDes lane speeds up to 224 Gbps and 448 Gbps under development as of 2025), USB, MIPI, and optical interfaces, facilitating applications in data centers, artificial intelligence accelerators, automotive systems, telecommunications (e.g., 5G), and consumer electronics like smartphones and gaming devices.^[1]^[2]^[3] Advances in SerDes design, such as PAM4 modulation, continuous-time linear equalizers (CTLE), decision feedback equalizers (DFE), and multi-channel configurations, enable operation over long distances with low latency and robust performance against signal degradation.^[2]^[4] By compressing wide parallel buses into fewer differential serial lines, SerDes reduces I/O complexity, package size, and overall system costs compared to traditional parallel interfaces.^[1]^[4]

Overview and Fundamentals

Definition and Purpose

SerDes, an acronym for Serializer/Deserializer, consists of a pair of functional blocks or integrated circuits that convert parallel data streams from a source device into a high-speed serial data stream for transmission over a differential link, and then deserialize the received serial data back into parallel form at the receiver.^[5] This bidirectional conversion facilitates reliable data transfer in environments where parallel buses would be impractical due to signal skew and complexity.^[6] The primary purpose of SerDes is to enable efficient, high-bandwidth data communication over constrained physical channels, such as a single or few differential pairs, thereby reducing pin counts on integrated circuits and simplifying printed circuit board (PCB) routing in system designs.^[5] By minimizing the number of interconnects required, SerDes lowers overall system cost and complexity while supporting scalable data throughput in applications like networking and storage.^[6] SerDes technology emerged in the 1990s, initially for backplane interconnects in telecommunications and computing systems, and served as a foundational element in the advancement of standards like Gigabit Ethernet by enabling gigabit-per-second serial links.^[7] Key benefits include achieving data rates up to 224 Gbps (PAM4) in modern implementations as of 2025, lower power dissipation per bit relative to parallel bus architectures, and extended reach over channels with impairments through equalization techniques.^[7] A basic understanding of digital communication principles, including bit streams and clock domains, provides the necessary foundation for grasping SerDes operation.^[5]

Basic Principles of Operation

The serializer in a SerDes system accepts parallel input data, typically in the form of a wide word such as a 32-bit bus operating at a relatively low clock frequency, and converts it into a high-speed serial bit stream transmitted over a single differential pair. This process involves multiplexing the parallel bits into a serial sequence using a parallel-in, serial-out shift register or similar architecture, where the serial output rate is multiplied by the number of parallel bits to achieve the desired bandwidth efficiency. A phase-aligned clock is generated internally, often through a phase-locked loop (PLL), to synchronize the serialization and ensure bit timing accuracy during transmission.^[8]^[9] At the receiving end, the deserializer recovers the incoming serial bit stream and reconstructs it into parallel output data matching the original word width and clock domain. This recovery relies on clock data recovery (CDR) circuitry, which extracts the embedded clock signal from the serial data transitions to sample incoming bits accurately, followed by bit-to-symbol alignment to group bits into the correct parallel format. The deserializer employs a serial-in, parallel-out shift register to demultiplex the stream, compensating for any minor timing variations through buffering mechanisms.^[8]^[10] The overall data path in a SerDes forms a logical block diagram comprising key elements: a multiplexer (mux) in the serializer for parallel-to-serial conversion, a demultiplexer (demux) in the deserializer for the reverse, transmit FIFO buffers to handle input data staging and prevent overflow, and elastic buffers in the receiver to accommodate clock domain differences and rate matching between transmitter and receiver domains. These components ensure seamless data flow across the channel, with the elastic buffer absorbing jitter or frequency offsets up to a tolerance of several parts per million. The rate multiplication factor, denoted as N, is defined as the ratio of the parallel data width to the number of serial lanes (typically 1 for single-lane operation), such that the serial bit rate equals N times the parallel bus rate; for instance, a 10:1 configuration yields a 10 Gbps serial stream from a 1 Gbps parallel interface.^[8]^[9]^[10] Basic error handling in SerDes focuses on detecting bit-level discrepancies to maintain link integrity, employing simple mechanisms such as parity bits appended to parallel words for odd/even error detection or cyclic redundancy check (CRC) polynomials computed over data blocks to identify transmission errors without correcting them. These methods provide initial validation before more advanced protocol-level recovery, ensuring that corrupted bits are flagged for retransmission if needed.^[8]^[10]

Clocking and Synchronization Methods

Source Synchronous Clocking

Source synchronous clocking is a timing method in Serializer/Deserializer (SerDes) systems where the transmitter generates and forwards a dedicated clock signal alongside the serialized data over separate transmission lines, typically differential pairs, allowing the receiver to directly sample the data using this clock without needing complex recovery mechanisms.^[10] This approach ensures that the clock and data signals originate from the same source, maintaining relative timing integrity during transmission.^[11] The primary advantages of source synchronous clocking include its simplicity and low latency, as it eliminates the need for a clock and data recovery (CDR) circuit at the receiver, reducing both power consumption and design complexity.^[10] It is particularly suitable for short-reach applications, such as board-level interconnects under 1 meter, where signal integrity can be preserved without advanced equalization.^[10] In these scenarios, the method supports reliable data rates up to several gigabits per second while minimizing overhead from clock extraction processes.^[11] Implementation typically involves double data rate (DDR) clocking, where the forwarded clock toggles on every bit transition to sample data on both rising and falling edges, achieving higher effective throughput.^[10] Edge alignment at the receiver is achieved using delay-locked loops (DLLs) to compensate for minor phase differences between the clock and data arrivals, ensuring precise sampling windows.^[10] This requires careful PCB design with matched-length traces for clock and data lanes to preserve synchronization.^[10] However, source synchronous clocking is limited by its vulnerability to skew between the clock and data signals, which can arise from variations in trace lengths, dielectric properties, or environmental factors, potentially degrading bit error rates.^[10] To mitigate this, stringent routing constraints must be enforced, limiting its scalability for longer distances or higher speeds where inter-lane skew becomes unmanageable.^[10]

Embedded Clocking

Embedded clocking in SerDes refers to a synchronization technique where the clock signal is not transmitted separately but is instead recovered directly from the transitions in the serial data stream at the receiver. This approach relies on clock data recovery (CDR) circuits to extract both the clock timing and the data, ensuring proper sampling without a dedicated clock lane. CDR mechanisms typically employ phase-locked loops (PLLs) or delay-locked loops (DLLs) that align the recovered clock to the incoming data's phase and frequency. In PLL-based CDRs, a phase detector compares the data edges to the clock, generating an error signal that adjusts a voltage-controlled oscillator (VCO) to minimize phase differences. Delay line-based implementations, often using phase interpolators, fine-tune clock phases without a VCO, offering lower power for certain applications.^[12]^[13]^[14] Two primary CDR architectures are linear and bang-bang types. Linear CDRs, such as those using Hogge phase detectors, provide proportional phase error information (sign and magnitude) to drive the loop, enabling precise tracking but requiring careful linearization to avoid distortion. Bang-bang CDRs, employing binary phase detectors like the Alexander topology, output only early/late decisions, resulting in high-gain, nonlinear operation that simplifies design and reduces components like charge pumps. These architectures handle embedded clock recovery by processing the data stream post-equalization, where the clock is distilled from edge transitions. To manage low-transition-density data, which can degrade recovery due to insufficient phase information, brief encoding schemes introduce controlled transitions, though the core focus remains on the CDR hardware. Dual-loop configurations, combining a global frequency loop with local phase adjustment, further enhance performance in multi-lane SerDes.^[15]^[13]^[14] The advantages of embedded clocking include eliminating the need for a separate clock lane, which reduces pin count and PCB routing complexity, while supporting data rates exceeding 10 Gbps over distances up to 10 meters or more when combined with equalization to counteract channel losses. For instance, in industrial SerDes, this enables reliable transmission over 15 meters of CAT-5 cable at 1.05 Gbps, scalable to higher speeds with advanced equalization. However, challenges arise from jitter accumulation, where phase noise builds up in the high-pass filtered CDR loop, potentially reaching 0.01 UI rms in stringent applications, and prolonged acquisition times for initial lock, especially with frequency offsets. Bang-bang designs mitigate some jitter through slewing but introduce dithering. Operations differ in continuous mode, which maintains ongoing tracking for steady streams, versus burst mode, suited for intermittent data but requiring faster relock. This method is standard in modern high-speed SerDes, such as those for 100G Ethernet, where the clock is embedded in the serial bit stream for efficient long-reach links.^[5]^[12]^[15]^[16]

Data Encoding and Serialization Techniques

Encoding Schemes for Transmission

Encoding schemes in SerDes systems are critical for reliable high-speed serial transmission, addressing challenges inherent to serial links such as clock recovery and signal integrity. These schemes primarily maintain DC balance by ensuring roughly equal numbers of 0s and 1s in the bit stream, which minimizes baseline wander in AC-coupled channels and reduces low-frequency electromagnetic interference (EMI). They also guarantee sufficient transition density—typically at least every five bits—to enable effective clock and data recovery (CDR) at the receiver by providing edges for phase-locked loops or delay-locked loops to track the clock. Additionally, encoding facilitates error detection by defining invalid code patterns that signal transmission faults.^[17]^[18]^[19] A foundational encoding method is 8b/10b, developed by A. X. Widmer and P. A. Franaszek at IBM in 1983 for use in high-speed backplane applications. This scheme independently encodes the 5 most significant bits (5b/6b block) and 3 least significant bits (3b/4b block) of an 8-bit data word into a 10-bit symbol, introducing a 25% overhead to achieve these goals without external randomization. The encoding enforces running disparity (RD), defined as the difference between the number of 1s and 0s in the cumulative stream, which the transmitter alternates between +1 and -1 by selecting from two possible symbols for each data word—one with positive disparity and one with negative. For control characters (K-codes), specific symbols like the K28.5 comma (0011111010 or 1100000101, depending on RD) are selected to aid receiver alignment and synchronization. This disparity control ensures no more than five consecutive identical bits, providing robust transition density for CDR while allowing detection of up to 16% of single-bit errors through invalid combinations.^[19]^[19]^[19] As SerDes data rates exceeded 10 Gbps, the overhead of 8b/10b became inefficient, leading to the adoption of larger block codes like 64b/66b in standards such as IEEE 802.3 Clause 49 for 10 Gigabit Ethernet, proposed by R. Walker and others in 2000. In 64b/66b, 64 bits of scrambled data are prefixed with a 2-bit sync header (either 01 for data blocks or 10 for control blocks), yielding only 3.125% overhead. The sync header indicates block type and aids alignment, while a self-synchronizing scrambler (polynomial x^{58} + x^{39} + 1) randomizes the payload to maintain DC balance and ensure at least 4 transitions per block on average, supporting CDR without fixed disparity rules. Control information is embedded in an 8-bit block type field, with the remaining 56 bits for ordered sets or data. This scheme trades some complexity for efficiency, requiring scrambler hardware but enabling higher throughput in applications like optical and backplane Ethernet.^[20]^[20]^[20] 128b/130b encoding, introduced in the PCI Express Base Specification Revision 3.0 in 2010 for 8 GT/s links, extends the block code approach and is used in ultra-high-speed SerDes at 25 Gbps and beyond, including with PAM4 modulation in later standards like PCIe 5.0. It prepends a 2-bit sync header (10 for data, 01 for control) to 128 bits of scrambled data, reducing overhead to about 1.54% and doubling the payload size of 64b/66b for better efficiency in multi-lane systems. Scrambling uses a 23-tap self-synchronizing linear feedback shift register with polynomial x^{23} + x^{21} + x^{16} + x^{8} + x^{5} + x^{2} + 1 to achieve DC balance and transition density suitable for reduced eye openings in high-speed links.^[21]^[22] This encoding supports error detection via block sync violations and is optimized for low-latency applications like PCIe Gen3 at 8 GT/s. The evolution from fixed-width schemes like 8b/10b to scalable block codes such as 64b/66b and 128b/130b reflects the demands of increasing bandwidth, transitioning from disparity-based control in lower-speed links to scrambler-assisted methods that minimize overhead while preserving DC balance and CDR compatibility. More recent advancements include 256b/257b encoding in IEEE 802.3ck for 100G to 800G Ethernet (as of 2023), which further reduces overhead to approximately 0.78% using a 1-bit sync header and scrambler for PAM4 signaling at up to 112 Gbps per lane. Additionally, PCI Express 6.0 (released 2022) introduces FLIT-based encoding for 64 GT/s PAM4 links, eliminating traditional block coding overhead in favor of flow control units with integrated forward error correction (FEC) to achieve higher efficiency and reliability in data center and AI applications as of November 2025.^[23]^[24] This progression has significantly reduced EMI in dense SerDes deployments by limiting spectral content at low frequencies, as balanced streams avoid long runs of identical bits that could radiate efficiently. While 8b/10b offers simplicity and inherent robustness without scramblers, its higher overhead limits scalability; conversely, block codes like 64b/66b and 128b/130b provide superior efficiency for 10G+ rates but introduce dependency on scramblers for balance, potentially complicating implementation in noise-sensitive environments.^[21]^[18]^[18]

Bit-Interleaved SerDes

Bit-interleaved SerDes architectures aggregate data from N parallel input streams—typically low-speed serial or parallel buses—into M high-speed serial output lanes, where M < N, by distributing individual bits across the lanes using multiplexing techniques such as round-robin or Gray-coded schemes to ensure even load balancing and minimize skew.^[25] This contrasts with parallel SerDes by focusing on bit-level granularity rather than word or byte alignment, enabling efficient scaling for multi-lane systems.^[17] In operation, the transmitter serializer employs a bit multiplexer to interleave incoming bits from the N inputs in a sequential manner onto the M output lanes, with each lane undergoing independent serialization, encoding, and transmission.^[26] At the receiver, per-lane clock and data recovery (CDR) circuits extract the serial bit streams, followed by de-interleaving logic that reconstructs the original parallel streams; lane deskew is managed using periodic alignment markers or training sequences to compensate for propagation delays across lanes.^[27] This design offers key advantages, including higher aggregate bandwidth achieved through parallelization of lower-speed SerDes lanes, which reduces the required speed and power per lane compared to a single high-speed equivalent, while enabling fault tolerance via dynamic lane swapping to isolate and bypass defective lanes.^[28] Additionally, bit-level interleaving minimizes buffering requirements at the receiver, lowering latency during deskew compared to symbol-based methods.^[26] Implementations incorporate a gearbox for rate adaptation, such as a 40:4 configuration that interleaves 40 parallel input bits across 4 serial lanes to match protocol rates, with independent equalization (e.g., feed-forward or decision-feedback) applied to each lane to counteract channel losses and crosstalk.^[25] Encoding schemes, like 8b/10b or 64b/66b, may be applied post-interleaving to ensure DC balance and clock recovery on the interleaved bit streams.^[26] A representative example is found in 400G Ethernet systems, where bit interleaving aggregates data across 4x100G lanes to achieve the full 400 Gb/s rate, providing scalability over symbol-interleaved (byte-wise) alternatives by allowing finer-grained distribution and better tolerance to lane mismatches.^[27]

Standardization and Protocols

Key Industry Standards

The IEEE 802.3 working group has defined several SerDes-based physical layer specifications for Ethernet backplane and copper applications, evolving to support higher speeds and advanced modulation. For instance, the 10GBASE-KR standard, part of IEEE 802.3ap-2007, operates at a line rate of 10.3125 Gbps per lane using 64b/66b encoding to achieve an effective 10 Gbps data rate over copper backplanes up to 1 meter.^[29] More recent advancements include the 400 Gigabit Ethernet specification in IEEE 802.3bs-2017, which employs four or eight lanes of PAM4 signaling at 53.125 Gbaud per lane (yielding 106.25 Gbps per lane) for aggregate rates up to 400 Gbps, enabling longer reach in data center environments. PCI Express (PCIe), governed by the PCI-SIG, has progressed through multiple generations, each specifying SerDes parameters including signaling rates, encoding, and forward error correction (FEC) to ensure reliable high-speed interconnects. The first generation (PCIe 1.0) uses 8b/10b encoding at 2.5 GT/s per lane. PCIe 2.0 uses 8b/10b encoding at 5 GT/s per lane. PCIe 3.0 to 5.0 use 128b/130b encoding at 8 GT/s, 16 GT/s, and 32 GT/s per lane, respectively. PCIe 6.0, finalized in 2022, achieves 64 GT/s per lane using PAM4 modulation and FLIT-based encoding with integrated low-latency FEC (e.g., Reed-Solomon), supporting lane configurations from x1 to x16 for bandwidths up to 256 GB/s bidirectional.^[24] Other prominent standards include the Optical Internetworking Forum's (OIF) Common Electrical I/O (CEI) specifications, which define SerDes interfaces for optical and electrical interconnects up to 112 Gbps per lane using PAM4, as outlined in OIF-CEI-112G for applications like chip-to-module and backplane links. More recent OIF efforts include the CEI-224G specification (2024) for 224 Gbps per lane and the CEI-448G framework (November 2025) targeting 448 Gbps per lane, supporting advanced chip-to-module and backplane applications with PAM4 and enhanced equalization.^[30] USB4, specified by the USB Implementers Forum, supports SerDes operation up to 40 Gbps (Version 1.0) or 80 Gbps (Version 2.0, released 2022) aggregate, using two lanes at 20 Gbps or 40 Gbps each with PAM3 modulation for versatile peripheral connectivity.^[31] For storage interfaces, the Serial Attached SCSI (SAS) standard from INCITS (up to SAS-4 at 22.5 Gbps per lane with 128b/130b encoding) and Serial ATA (SATA) at 6 Gbps (SATA 3.0 with 8b/10b encoding) rely on SerDes for point-to-point data transfer in enterprise and consumer drives. Compliance with these standards requires rigorous testing of SerDes electrical characteristics to ensure interoperability and signal integrity. Key metrics include eye diagram measurements, which assess signal amplitude and timing margins (e.g., minimum eye height and width in IEEE 802.3 and PCIe specs), and jitter budgets that allocate deterministic and random jitter components (typically targeting total jitter under 0.7 UI at 10^-12 BER for high-speed links). Interoperability testing, often conducted via automated suites from PCI-SIG or IEEE conformance programs, verifies transmitter/receiver compliance across multi-vendor ecosystems.

Evolution of SerDes Specifications

The origins of Serializer/Deserializer (SerDes) technology trace back to the 1990s, when it emerged as a critical component in high-speed optical telecommunications networks, particularly for Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) systems. The OC-192 interface, standardized at 10 Gbps, represented a key early application, where SerDes serialized parallel data streams into high-speed serial formats for transmission over fiber optic media, enabling efficient long-haul and metropolitan area networking.^[32]^[28] During this period, SerDes designs focused on overcoming signal integrity challenges in optical transceivers, with initial implementations supporting rates up to 10 Gbps while consuming around 500 pJ/bit in power efficiency.^[33] By the 2000s, SerDes technology shifted toward Ethernet ecosystems, driven by the demand for scalable data center and enterprise interconnects. A pivotal milestone was the ratification of the IEEE 802.3ae standard in 2002, which defined 10 Gigabit Ethernet and integrated SerDes for serial interfaces operating at 10.3125 Gbps using non-return-to-zero (NRZ) signaling. This was followed by the IEEE 802.3ba standard in 2010, introducing 40 Gbps and 100 Gbps Ethernet with multi-lane SerDes configurations to support aggregated bandwidths. Post-2018 developments included the IEEE 802.3ck standard, which specified 100 Gbps electrical lanes using PAM4 modulation for backplane and chip-to-module applications, addressing the need for higher-density interconnects.^[34] The IEEE 802.3df amendment in 2024 further advanced 800 Gbps Ethernet, incorporating co-packaged optics to integrate SerDes directly with photonic components for reduced latency and improved reach.^[35] Key advancements in SerDes specifications have centered on signaling efficiency, error correction, and power optimization to sustain exponential bandwidth growth. Transitioning from binary NRZ to four-level pulse amplitude modulation (PAM4) became essential beyond 56 Gbps per lane, as PAM4 doubles spectral efficiency by encoding two bits per symbol, though it requires enhanced equalization to mitigate noise.^[36] Forward error correction (FEC) integration, such as the Reed-Solomon RS(528,514) code used in 100 Gbps backplane Ethernet (KR4-FEC), has improved bit error rates from pre-FEC targets of 10^{-5} to post-FEC levels below 10^{-12}, enabling reliable operation over lossy channels.^[37] Power efficiency has scaled dramatically, from approximately 50 pJ/bit in early 10 Gbps designs to under 5 pJ/bit in modern 112 Gbps implementations, achieved through advanced process nodes, digital signal processing, and architectural optimizations like gearboxing.^[38]^[39] Looking ahead, SerDes specifications are poised for 1.6 Tbps Ethernet by 2025-2030, propelled by AI-driven data center demands for massive parallelism and low-latency interconnects. These future systems will likely emphasize co-packaged and linear pluggable optics, further reducing power to sub-3 pJ/bit while supporting 200 Gbps electrical lanes.^[40]^[41]

Applications and Implementations

Use in Computing and Storage Interfaces

Serializer/Deserializer (SerDes) technology plays a critical role in high-speed interconnects within computing and storage systems, enabling efficient data transfer between processors, memory, and peripherals. In Peripheral Component Interconnect Express (PCIe) interfaces, SerDes facilitates backplane and chip-to-chip links, supporting data rates up to 32 GT/s per lane in PCIe Gen5 implementations commonly used in servers (with PCIe Gen6 at 64 GT/s available as of 2024).^[42]^[24] For example, a PCIe Gen5 x16 configuration achieves an aggregate bandwidth of 512 Gbps per direction, allowing rapid data movement in multi-socket CPU setups and GPU acceleration environments. This capability is essential for handling the high-throughput demands of modern data processing workloads. In storage interfaces, SerDes underpins protocols like Serial Attached SCSI (SAS-4), which operates at 22.5 Gbps per lane (marketed as 24G SAS) to connect enterprise hard drives and solid-state drives (SSDs) in array configurations.^[43] SAS-4 incorporates advanced features such as 128b/150b encoding and forward error correction to maintain signal integrity over longer distances, making it suitable for scalable storage subsystems in servers.^[44] Similarly, NVMe over Fabrics (NVMe-oF) leverages SerDes in underlying fabrics like Ethernet or Fibre Channel to enable low-latency access to distributed SSD arrays, disaggregating storage from compute nodes while supporting petabyte-scale deployments in hyperscale environments. For chiplet-based integration, the Universal Chiplet Interconnect Express (UCIe) standards (v1.0 released in 2022; v3.0 in 2025) standardize multi-die systems using SerDes at speeds up to 32 Gbps per pin in initial versions and up to 64 GT/s in advanced versions, promoting modular designs in advanced processors.^[45] This approach allows heterogeneous integration of compute, memory, and I/O dies within a single package, reducing latency and improving yield for complex SoCs like those in AI accelerators.^[46] SerDes implementations in these contexts prioritize low latency, typically under 100 ns pin-to-pin, to minimize delays in data center operations where real-time processing is critical.^[47] Power efficiency is another key metric, with modern SerDes achieving efficiencies around 1.55 pJ/b, which helps curb overall energy consumption in dense server racks handling AI and cloud workloads.^[48] A prominent case study is NVIDIA's GPUs employing SerDes in NVLink interconnects, which provide up to 900 GB/s bidirectional bandwidth between devices in multi-GPU configurations using NVLink 3.0 (as in Hopper GPUs), with newer NVLink 5.0 (2024) reaching up to 1.8 TB/s per GPU.^[49] This enables seamless scaling for high-performance computing tasks, such as training large language models, by allowing direct GPU-to-GPU communication without bottlenecking through host memory.^[50]

Role in Telecommunications and Networking

In telecommunications and networking, Serializer/Deserializer (SerDes) technology plays a pivotal role in enabling high-capacity data transmission over optical and electrical links, supporting the demands of modern infrastructure for low-latency, high-bandwidth connectivity. SerDes interfaces are integral to pluggable optical modules such as QSFP-DD, which facilitate Ethernet deployments in data centers. For instance, in 400G and 800G Ethernet switches (with 1.6T emerging as of 2025), SerDes handles serialization and deserialization at rates up to 112 Gbps per lane, allowing seamless integration with pluggable optics for interconnects between servers and aggregation points.^[51]^[52] These modules support backward compatibility with lower-speed QSFP variants, ensuring scalable upgrades in hyperscale environments without full hardware overhauls.^[53] In optical transport networks, coherent SerDes enhances dense wavelength division multiplexing (DWDM) systems by integrating with digital signal processors (DSPs) to manage complex modulation schemes. A key example is the 400G ZR standard, where SerDes operates at approximately 26.6 Gbaud using PAM4 modulation across 8 lanes to achieve transmission distances up to 120 km over single-mode fiber in pluggable QSFP-DD formats.^[51] This configuration supports IP-over-DWDM deployments in metro and regional networks, providing 400 Gbps per wavelength with forward error correction for signal integrity.^[54] Coherent SerDes thus enables efficient multiplexing of multiple channels across the C-band, reducing the need for intermediate regeneration in long-haul applications.^[51] For backplane applications in optical transport units (OTUs), SerDes retimers extend reach over extended traces, critical for chassis-based systems. In 100G OTU4 implementations, quad 28G SerDes retimers like the AVSP-4412 provide up to 32 dB of channel loss compensation at 25 Gbps per lane, supporting traces longer than 1 meter while maintaining a bit error rate below 10⁻¹⁷.^[55] These retimers incorporate adaptive equalization and backchannel communication for link training, ensuring reliable aggregation in OTN switches and routers compliant with OIF CEI-25G-LR specifications.^[56] Such capabilities are essential for high-density backplanes handling multiplexed traffic in carrier-grade equipment. Scalability in SerDes designs is achieved through multi-lane configurations, which aggregate bandwidth for terabit-scale links. For 400G applications, 8-lane setups at approximately 53 Gbps per lane (using PAM4 at 26.6 Gbaud) enable ~425 Gbps line rate total throughput, often with bit-interleaving to distribute data across lanes for improved tolerance to impairments.^[51] In 5G and emerging 6G fronthaul networks, high-performance SerDes with ultra-low jitter and latency support asymmetric operation for radio unit-to-baseband connections, facilitating real-time data aggregation over fiber links.^[57] Emerging applications leverage SerDes in edge computing nodes for IoT aggregation within telecommunications frameworks, where high-speed interfaces handle the influx of sensor data from distributed devices. In 5G edge deployments, SerDes enables low-latency processing and forwarding of aggregated IoT traffic to core networks, supporting use cases like smart city infrastructure and industrial monitoring.^[57] This integration enhances efficiency in resource-constrained environments by minimizing round-trip delays for massive machine-type communications.^[58]

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• Four FEC frames interleaved to subset of SERDES. • Good burst error BER performance. • Bit muxing between appropriate lanes. • Some lane order limitations.
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[PDF] High Speed Serdes Devices and Applications
HSS devices are the dominant form of input/output for many (if not most) high-integration chips, moving serial data between chips at speeds up to 10. Gbps and ...
[25]
IEEE 802.3ap-2007
10GBASE-T specifies a LAN interconnect for up to 100 m of balanced twisted-pair structured cabling systems.
[26]
Getting there faster: The evolution of SERDES and high-speed data ...
Jul 14, 2020 · SERDES evolved from fiber/coaxial links to chip-to-chip, with data rates increasing from 51.84 Mbps to 10Gbps and now 50Gbps with PAM4.Missing: Gigabit | Show results with:Gigabit
[27]
Getting there faster: The evolution of SERDES and high-speed data ...
Dec 15, 2020 · ... SERDES from the 1990s and today. ... It had a line rate of 1.25Gbps to support Gigabit Ethernet (802.3z), 1000BASE-X Gbps Ethernet over Fiber.
[28]
[PDF] 100G SERDES Power Study - IEEE 802
This contribution tries to summarize latest papers on PAM4 SERDES, and predict power of 100G. SERDES by scaling clock frequency. Page 3. 3. IEEE P802.3ck Task ...
[29]
802.3df-2024 - IEEE Standard for Ethernet Amendment 9: Media ...
This amendment adds MAC parameters, Physical Layers, and management parameters for the transfer of IEEE 802.3 format frames at 400 Gb/s and 800 Gb/s.
[30]
NRZ to PAM-4: 400G Ethernet Evolution | Synopsys IP
Jul 22, 2019 · This article describes PAM-4 multi-level signaling and its trade-offs and benefits vs. NRZ for 56G data rates.
[31]
Understanding FEC and Its Implementation in Cisco Optics
KR1-FEC translates 4x25G NRZ electrical signals into a 100GBASE-KR1 encoded signal. KR-FEC is denoted as RS(528, 514). Here, the RS encoding starts with a 514- ...
[32]
Energy Efficiency in Co-Packaged Optics
Early implementations of CPO have demonstrated significant power consumption reductions down to less than 5 pJ per bit, which is up to 4 times the energy ...
[33]
Perspective on the future of silicon photonics and electronics
Jun 1, 2021 · Target power requirements have dropped from thousands of pJ/bit to sub-pJ/bit over the past decade. ... The evolution of PIC bandwidth, power ...<|separator|>
[34]
Data Center AI Networking to Surge to Nearly $20B in 2025 ...
Jun 4, 2024 · The report also revealed that early 1.6 Tbps port shipment should occur in 2025. Highlights for Data Center AI Networking 1Q'24 include:.Missing: trends 2025-2030
[35]
Data center semiconductor trends 2025: Artificial Intelligence ...
Aug 12, 2025 · The total semiconductor market for data centers is projected to grow from $209 billion in 2024 to $492 billion by 2030. It is fueled by ...Missing: 1.6 Tbps
[36]
Accelerating 32 GT/s PCIe 5.0 Designs | Synopsys IP
Jan 21, 2019 · This article outlines the design challenges of moving to a PCIe 5.0 interface and how to successfully overcome the challenges using proven IP.
[37]
24G SAS Technology
Experience the industry's most reliable storage solutions with our 24G SAS technology SAS-4 controllers. Upgrade with our storage backbone.
[38]
[PDF] Introducing the 24G SAS Interface Technical Brief
Though 24G is a speed upgrade, the SAS interface has been overhauled with new capabilities such as 128b/150b encoding, 20-bit Forward Error Correction (FEC), ...
[39]
Specifications | UCIe Consortium
The UCIe specification details the complete standardized Die-to-Die interconnect with physical layer, protocol stack, software model, and compliance testing.Missing: 2022 Gbps SerDes
[40]
Unpacking the Rise of Multi-Die SoCs with UCIe | Synopsys IP
Jul 17, 2022 · UCIe is a comprehensive specification that can be used immediately as the basis for new designs, while creating a solid foundation for future specification ...
[41]
Alphawave Semi Joins UALink™ Consortium to Accelerate High ...
Dec 4, 2024 · The interface pools up to 1,024 XPUs into a single node with a latency of less than 100 ns pin-to-pin and supports data transfer at up to 224 ...
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https://www.synopsys.com/articles/accelerating-32gtps-pcie5-designs.html
[43]
NVLink & NVSwitch: Fastest HPC Data Center Platform | NVIDIA
The NVLink Switch interconnects every GPU pair at an incredible 1,800GB/s. It supports full all-to-all communication. The 72 GPUs in the NVIDIA GB300 NVL72 can ...Maximize System Throughput... · Raise Reasoning Throughput... · Nvidia Nvlink Fusion
[44]
NVIDIA NVLink and NVIDIA NVSwitch Supercharge Large ...
Aug 12, 2024 · With the NVSwitch, every NVIDIA Hopper GPU in a server can communicate at 900 GB/s with any other NVIDIA Hopper GPU simultaneously. The peak ...Multi-Gpu Inference Is... · Nvswitch Is Critical For... · Continued Nvlink Innovation...Missing: SerDes | Show results with:SerDes<|control11|><|separator|>
[45]
[PDF] Juniper 400G Optical Transceivers and Cables Guide
Jul 30, 2025 · Tunable DWDM optics (ZR and ZR+) use advanced DSP functions. DSP involves several components such as: 8. Page 13. • SerDes ( ...
[46]
[PDF] Towards High Performance 400G, 800G Data Center - #CiscoLive
25.6T G100 ASIC (7nm) | 112G SERDES. 108MB fully shared packet buffer. QSFP-DD800 Ports—backward compatible with QSFP-DD, QSFP28, QSFP+. Quad Core x86 CPU ...
[47]
Cisco 400G QSFP-DD Cable and Transceiver Modules Data Sheet
The Cisco® family of QSFP-DD modules provide the industry's highest bandwidth density while leveraging the backward compatibility to lower-speed QSFP ...
[48]
Coherent 400ZR Series - Adtran
Coherent innovation. With state-of-the-art technology, our 400G ZR optics enable 400Gbit/s DWDM transport in a QSFP-DD form factor.
[49]
[PDF] AVSP-4412 100G Retimer - Bidirectional 4x28G - Product Brief
AVSP-4412 features backchannel communication paths between SerDes to support Link Training. (IEEE-802.3ba Clause 72). In addition to the SerDes 07 and SerDes 03 ...
[50]
[PDF] White Paper CEI-25G-LR and CEI-28G-VSR Multi-Vendor ... - OIF
Inphi's CMOS 100G Ethernet and OTU4 Quad 25-28G Retimer targets next- generation ultra low power optical modules with new levels of integration and advanced ...
[51]
High-Performance SerDes Enable The 5G Wireless Edge
Apr 14, 2022 · These SerDes are architected to provide the ultra-low jitter, ultra-low latency and efficient asymmetric operation needed for 5G.
[52]
5G Wireless Infrastructure Pushes High-Speed SerDes Protocols
Jun 14, 2018 · Reducing SerDes latency variation and jitter is necessary for long-reach networking applications.