USB4
USB4 is a connectivity standard developed by the USB Implementers Forum (USB-IF) that represents a major advancement in Universal Serial Bus (USB) technology, enabling high-speed data transfer, video output, and power delivery over a single USB Type-C cable.[1] It integrates the Thunderbolt 3 protocol—contributed by Intel—to achieve asymmetric or symmetric data rates of up to 40 Gbps in its initial version, with dynamic bandwidth sharing among multiple protocols such as USB, PCIe, and DisplayPort for simultaneous device connectivity.[1] Development announced in March 2019, with the Version 1.0 specification published in August 2019, USB4 ensures backwards compatibility with prior USB standards like USB 3.2 and USB 2.0, scaling performance to the lowest common capability between connected devices.[1] In September 2022, the USB Promoter Group announced USB4 Version 2.0, which doubles the maximum bandwidth to 80 Gbps (40 Gbps per lane across two lanes) while maintaining full compatibility with the original specification and earlier USB generations.[2] This version, published by the USB-IF in October 2022, introduces enhancements for higher-performance applications, including improved support for external displays and storage, and requires certified 80 Gbps cables for optimal operation.[2] USB4 Version 2.0 also aligns with updates to the USB Type-C connector specification (Release 2.1) and USB Power Delivery (PD) 3.1, enabling power provisioning up to 240 W (48 V at 5 A) for charging laptops, peripherals, and other devices.[3] Beyond speed and power, USB4 emphasizes versatility through its tunneling architecture, which allows a single port to handle diverse data streams without dedicated hardware for each function, simplifying design for hosts like computers and docks.[1] USB4 supports the Thunderbolt 3 protocol natively via tunneling and requires DisplayPort 1.4 (or later) Alt Mode on host ports, facilitating resolutions up to 8K at 60 Hz or multiple 4K displays, along with PCIe tunneling for external graphics or storage expansion.[1] By leveraging the reversible USB Type-C interface, USB4 reduces cable clutter and enhances interoperability across consumer electronics, professional workstations, and mobile devices, positioning it as a unified solution for modern connectivity needs.[1]Overview
Key Features
USB4 represents a significant advancement in connectivity standards by integrating the protocols of USB 3.2, Thunderbolt 3, and DisplayPort 1.4 into a unified protocol stack, enabling seamless transfer of data, video, and power over a single USB Type-C connection.[1] This integration, based on the Thunderbolt protocol contributed by Intel, allows for versatile applications such as high-speed data storage, external graphics processing, and multi-display setups, while maintaining compatibility with existing USB ecosystems.[4] A core feature is the bandwidth provisioning, with a minimum guaranteed rate of 20 Gbps to ensure reliable performance across devices, and optional support scaling up to 40 Gbps in Version 1.0 for bidirectional symmetric transfer.[1] Version 2.0 extends this further with up to 80 Gbps symmetric operation or an asymmetric mode reaching 120 Gbps in one direction and 40 Gbps in the other, optimizing for scenarios like high-bandwidth video output or data ingestion.[5] USB4 ensures backward compatibility with USB 2.0, USB 3.x, and Thunderbolt 3 devices, as well as the broader USB Type-C ecosystem, including USB Power Delivery (PD) capabilities up to 240 W for charging high-power devices like laptops.[1][3] The standard's dynamic resource allocation allows asymmetric bandwidth distribution to prioritize traffic types, such as dedicating more capacity to display streams over data transfers, enhancing efficiency in mixed-use environments.[4] For video applications, USB4 supports DisplayPort tunneling, enabling configurations like dual 4K displays at 60 Hz or a single 8K display at 60 Hz, depending on the implementation and cable quality.[1] Additionally, it briefly references PCIe tunneling for external GPU connectivity, though detailed mechanisms are defined elsewhere.[1]Technical Specifications
USB4 establishes performance tiers based on signaling generations to balance speed, compatibility, and cable requirements. Version 1.0 mandates a minimum bandwidth of 20 Gbps via Gen 2x2 operation, which utilizes two lanes at 10 Gbps each, while supporting a maximum of 40 Gbps through Gen 3x2 signaling over certified 40 Gbps cables.[1] Version 2.0 extends this to 80 Gbps symmetric bandwidth using PAM3 signaling over two lanes, doubling the aggregate throughput for demanding applications like high-resolution displays and storage; an optional asymmetric mode allocates 120 Gbps in one direction (primarily for video output) paired with 40 Gbps in the reverse, enhancing efficiency for unidirectional high-bandwidth scenarios.[1] The protocol relies on a packet-based architecture for flexible data handling across tunneled protocols, employing 128b/132b encoding in Gen 3 modes to minimize overhead to about 3%, compared to higher losses in prior schemes like 8b/10b. This encoding supports robust error detection and synchronization for concurrent protocol multiplexing, such as USB, PCIe, and DisplayPort. Packets vary in size up to 256 bytes payload, allowing dynamic allocation while maintaining link efficiency. Latency is optimized for real-time applications, with low round-trip times for USB tunneling to preserve legacy USB performance. PCIe tunneling introduces variable latency based on configuration, scaling with link width up to x4 Gen 3 (approximately 32 Gbps raw), where added overhead from encapsulation results in slightly higher delays than native PCIe but remains suitable for external GPUs and storage.[6][7] Power efficiency is a core design goal, with low idle consumption to support battery-powered hosts and reduce thermal impact.[1] This metric aligns with USB Power Delivery profiles up to 240 W for active operation, emphasizing low standby draw during inactivity.[1] Certification by the USB Implementers Forum (USB-IF) ensures interoperability and reliability through standardized testing, including eye diagram assessments for signal integrity at 40 Gbps. These tests verify transmitter output against masks defined in the specification (e.g., Table 3-6), measuring jitter, voltage levels, and eye opening to confirm robust performance over cables up to 0.8 m.[8] Additional compliance matrices cover protocol layers, power negotiation, and backward compatibility with USB 3.2 and Thunderbolt 3.History and Development
Origins and Standardization
The development of USB4 originated from initiatives by the USB Promoter Group, a consortium comprising leading technology companies including Intel, Microsoft, Apple, Hewlett-Packard, and Renesas Electronics, to create a unified connectivity standard that integrates USB, Thunderbolt, and DisplayPort functionalities over the USB Type-C connector. These efforts addressed growing bandwidth fragmentation across disparate interfaces by enabling a single-cable solution capable of handling high-speed data transfer up to 40 Gbps, support for 8K video output via DisplayPort tunneling, and power delivery up to 100 W through USB Power Delivery protocols. The motivation stemmed from the need to streamline device connectivity for advanced applications, such as external storage, displays, and peripherals, while maintaining backward compatibility with prior USB generations.[9][10] Intel played a pivotal role by contributing its Thunderbolt 3 protocol specification to the USB Promoter Group, which formed the architectural foundation for USB4 and facilitated broader industry adoption beyond Intel's proprietary ecosystem. This collaboration extended to AMD, which supported USB4 integration in its processor platforms, and display technology organizations like the Video Electronics Standards Association (VESA), ensuring seamless incorporation of DisplayPort Alternate Mode for enhanced video capabilities. An initial draft of the specification emerged in early 2019, building on the Thunderbolt 3's tunneling mechanisms to support multiple protocols dynamically over shared links.[11][4] The USB Implementers Forum (USB-IF) ratified the USB4 Version 1.0 specification on August 29, 2019, marking it as a significant evolution from USB 3.2 by doubling aggregate bandwidth for optimized performance. The formal publication followed on September 3, 2019, making the specification available for adopters and spurring ecosystem development. This standardization process involved over 50 companies through the USB-IF, emphasizing interoperability and certification to mitigate compatibility issues in the evolving USB Type-C landscape. The specification was later extended with Version 2.0 in October 2022, supporting up to 80 Gbps bandwidth.[12]USB4 Version 1.0
The USB4 Version 1.0 specification was released on August 29, 2019, with the full technical details becoming available to developers through the USB Implementers Forum (USB-IF) shortly thereafter.[13] This version marked a significant evolution in USB connectivity by basing its protocol on Thunderbolt 3, enabling higher bandwidth while maintaining backward compatibility with prior USB standards. The core specifications mandate support for a minimum data rate of 20 Gbps using two lanes of differential signaling, with optional extension to 40 Gbps for devices capable of bonding those lanes to achieve full bidirectional throughput. This design prioritized symmetric data transfer, addressing limitations in predecessors like USB 3.2 by capping maximum speeds at 40 Gbps without asymmetric modes, thus simplifying implementation for high-performance applications such as external storage and display tunneling.[14] The USB-IF launched its certification program for USB4 Version 1.0 in 2020 to ensure interoperability and compliance among devices.[15] The first certified products emerged in 2021, including Intel's JHL8540 Thunderbolt 4 controller, which integrated USB4 capabilities into add-in cards and motherboards for enhanced connectivity.[16] Initial focus emphasized seamless compatibility with Thunderbolt 3 ecosystems, allowing USB4 hosts to support Thunderbolt 3 peripherals at up to 40 Gbps without requiring new cables or adapters, thereby easing the transition for existing users. Market rollout began with early adoption in premium laptops by mid-2021, exemplified by models like the Dell XPS 13 (9310) and Lenovo ThinkPad X1 Carbon Gen 9, which incorporated USB4 ports powered by Intel's Tiger Lake processors. These devices demonstrated the specification's practical impact by enabling faster external GPU connections and multi-monitor setups, accelerating ecosystem growth despite initial hardware costs. Subsequent enhancements in USB4 Version 2.0 would build on this foundation by introducing higher speeds beyond 40 Gbps.[14]USB4 Version 2.0
USB4 Version 2.0 was officially released by the USB Implementers Forum (USB-IF) in October 2022, introducing significant enhancements to the USB4 standard with support for up to 80 Gbps symmetric data transfer rates and 120 Gbps asymmetric modes (80 Gbps upstream and 40 Gbps downstream). These updates build on the foundational 40 Gbps capabilities of Version 1.0 by incorporating a new physical layer architecture that enables higher performance over existing USB Type-C cables and connectors. The specification also maintains backward compatibility with prior USB4 ports, ensuring seamless integration with older devices while unlocking advanced features on compatible hardware.[17] Key advancements in Version 2.0 include the adoption of PAM3 (Pulse Amplitude Modulation with 3 levels) signaling, which operates at 25.6 GBaud to achieve the elevated throughput without requiring entirely new cabling infrastructure. This is complemented by improved PCIe tunneling capabilities, supporting up to PCIe Gen 4 x4 (64 Gbps), allowing for more efficient external device connectivity such as GPUs and storage arrays. Additionally, power delivery has been extended to support up to 240 W via USB Power Delivery 3.1 with Extended Power Range (EPR), enabling charging of high-power devices like laptops and peripherals directly through the connection. These features collectively enhance overall system efficiency and versatility.[18][19] The first controllers supporting USB4 Version 2.0, such as Intel's JHL9480 for Thunderbolt 5 integration, received certification in 2024, paving the way for commercial products. Initial devices incorporating these capabilities began launching in 2025, including docking stations and laptops from manufacturers like ASUS and HP, which leverage the standard for expanded connectivity options.[20][21] These improvements provide better support for demanding applications, such as AI workloads, through increased PCIe bandwidth that facilitates faster data transfer to external accelerators, and reduced latency for high-speed external storage solutions. As of 2025, market analyses predict widespread adoption of USB4 Version 2.0 in gaming PCs and professional workstations, driven by its integration into Thunderbolt 5-certified devices that offer enhanced performance for graphics-intensive tasks and data-heavy computing. This shift is expected to accelerate with a projected compound annual growth rate (CAGR) of 19.3% for related high-speed connectivity solutions through 2031, as vendors prioritize compatibility with emerging AI and multimedia ecosystems.[22][23]Architecture and Protocols
Core Principles
USB4 employs a packet-switched fabric architecture, leveraging the USB4 Router as the central component for managing data flow. The USB4 Router serves as the foundational building block in any USB4 implementation, facilitating dynamic path allocation across hosts, devices, and protocol tunnels. This router core handles packet routing within the fabric, enabling efficient multiplexing of multiple data streams over a shared high-speed link. By design, the architecture supports connection-oriented tunneling for protocols such as USB 3.x and PCIe, allowing seamless integration without requiring software modifications for basic operations.[24][25] Ports in USB4 systems are role-based to maintain clear host-device hierarchies while accommodating flexibility. The Downstream Facing Port (DFP) is designated for host roles, sourcing power and initiating connections, whereas the Upstream Facing Port (UFP) is used by devices to receive power and connect upstream. Dual-role ports (DRP) support switching between DFP and UFP roles based on negotiation via USB Power Delivery (PD), enabling versatile configurations such as host-to-host tunneling or device-to-device links. This role assignment ensures topological stability, with the Connection Manager (CM) detecting and preventing invalid connections like DFP-to-DFP loops.[24] Bandwidth arbitration in USB4 utilizes a credit-based flow control mechanism to optimize resource sharing across the link. The CM oversees path setup, teardown, and allocation, dynamically allocating bandwidth to active paths while employing lazy allocation for idle paths to maximize efficiency. Up to 90% of the total link bandwidth—such as 18 Gbps on a 20 Gbps link or 36 Gbps on a 40 Gbps link—can be reserved for tunneled protocols, with the system prioritizing isochronous traffic such as USB 3.x within allocated bandwidth. USB4 Version 1.0 supports a minimum link speed of 20 Gbps. This system prevents oversubscription and supports dynamic adjustments based on real-time demands.[24][25] Security in USB4 incorporates built-in authentication mechanisms akin to those in Thunderbolt, particularly for protecting against direct memory access (DMA) attacks via PCIe tunneling. The architecture supports kernel DMA protection on compatible systems, using DMA remapping (such as Intel VT-d on Intel platforms) to isolate device memory access and prevent unauthorized reads or writes to system memory. PCIe tunneling can be selectively disabled through BIOS settings or operating system controls, ensuring only authenticated devices gain elevated privileges. These features mitigate risks from external peripherals, with the CM enforcing secure path establishment.[25] The logical topology of USB4 forms a tree structure rooted at the host router, with support for daisy-chaining up to seven devices through a maximum of six downstream routers. This configuration allows aggregated bandwidth management across the chain, where the CM constructs a spanning tree to synchronize timing via the Time Management Unit (TMU) and allocate resources holistically. Each link in the chain operates at up to 40 Gbps bidirectionally, with the overall domain ensuring end-to-end flow control and preventing bandwidth bottlenecks through credit grants and hop-based credits.[24][26]Tunneling Mechanisms
USB4 employs tunneling mechanisms to encapsulate and transport protocols such as USB 3.x, DisplayPort, and PCIe over its high-speed serial link, enabling simultaneous operation of multiple data streams within a single physical connection. This encapsulation occurs at the USB4 transport layer, where packets from native protocols are wrapped in USB4 headers for routing across the fabric, allowing dynamic multiplexing without dedicated lanes for each protocol. The design ensures backward compatibility and native performance for tunneled devices, with the USB4 router managing path selection and bandwidth distribution to prioritize active sessions.[25][27] For USB 3.x tunneling, USB4 provides native support for USB 3.2 Gen 2 (10 Gbps) and Gen 2x2 (20 Gbps) operation through dedicated adapters that map Enhanced SuperSpeed packets directly onto the USB4 transport layer. This eliminates physical layer overheads like scrambling and SKIP ordered sets from the original USB 3.x signaling, improving efficiency by reducing unnecessary protocol elements during transit. The tunneling supports both single-lane and dual-lane configurations, allowing USB 3.x devices to operate as if connected natively, with hot-plug detection handled via USB Type-C mechanisms. In USB4 Version 2.0, this extends to higher effective rates leveraging the 80 Gbps link, though capped by USB 3.x protocol limits.[28][29][30] DisplayPort tunneling in USB4 supports up to 32.4 Gbps for DisplayPort 1.4 (High Bit Rate 3 mode) in Version 1.0, enabling high-resolution video output such as 8K at 60 Hz or 4K at 120 Hz. Version 2.0 extends this to DisplayPort 2.0 capabilities at up to 80 Gbps, utilizing the full link bandwidth for ultra-high-definition displays. The mechanism includes multi-stream transport (MST), which allows a single USB4 port to drive multiple displays by branching video streams within the tunnel. Hot-plug events are signaled through auxiliary channel packets, ensuring seamless display detection and configuration. Buffering at adapters compensates for timing variations between USB4 and DisplayPort clocks.[31][10][25] PCIe tunneling facilitates external expansion devices, supporting up to PCIe Gen 3 x4 (approximately 32 Gbps bidirectional) in USB4 Version 1.0, suitable for applications like external GPUs and NVMe storage. Version 2.0 upgrades this to PCIe Gen 4 x4 (approximately 64 Gbps bidirectional), requiring all components in the tunnel path to comply with the enhanced specification. The tunneling maps PCIe transaction layer packets (TLPs) and data link layer packets (DLLPs) into USB4 frames, with single-hop topology necessitating PCIe switches in routers for multi-device support. Hot-plug functionality is preserved through dedicated control packets, enabling dynamic attachment of PCIe endpoints without system reboot.[32][30][27] Bandwidth sharing among tunnels is managed dynamically by the USB4 connection manager, which allocates portions of the total link bandwidth—20 Gbps, 40 Gbps, or 80 Gbps depending on the version and cable—to active protocols based on demand and priority. For instance, on a 40 Gbps link, 20 Gbps might be assigned to a DisplayPort tunnel for video while the remaining 20 Gbps supports USB 3.x data transfer. The allocation formula reserves approximately 10% of the link bandwidth for management and overhead, with available bandwidth calculated as roughly 0.9 times the total USB4 link rate minus committed resources for other tunnels, using weighted round-robin (WRR) scheduling for fairness. This ensures low-latency performance across mixed workloads.[25][33] Encapsulation in USB4 tunneling introduces overhead from added headers, such as packet headers, header error correction (HEC), and cyclic redundancy checks (CRC), typically amounting to 5-10% in scenarios with mixed traffic due to the combined effects of USB4 framing and native protocol remnants. Idle symbols and certain control elements from the original protocols are not tunneled, further optimizing efficiency, while forward error correction (FEC) parity for DisplayPort is omitted to minimize latency. In pure-protocol tunnels, overhead is lower, approaching the ~2.5% from 128b/130b encoding alone.[27][34][35]Protocol Adapters
Protocol adapters in USB4 serve as the interface components that convert and manage the tunneling of various input/output protocols over the USB4 fabric, enabling seamless integration of legacy and high-speed protocols such as USB 3.x, PCI Express (PCIe), and DisplayPort (DP).[24] These adapters operate within the protocol adapter layer, mapping specific I/O protocols to USB4 packets for encapsulation and decapsulation, allowing up to 64 adapters per router to support dynamic resource allocation across the link.[24] By handling protocol-specific processing without altering the underlying USB4 transport, they ensure compatibility and efficiency in multi-protocol environments.[29] The USB3 I/O adapter facilitates backward compatibility by converting USB4 packets into USB 3.x SuperSpeed formats, encapsulating and decapsulating USB 3.2 protocol data while supporting configurations like Gen 2 single-lane (2x1) or dual-lane (2x2) modes.[24] This adapter bypasses USB4-specific physical layer elements such as scrambling and SKIP ordered sets, directly translating native USB 3.2 traffic to tunneled formats for legacy devices without requiring additional hardware intervention.[29] It ensures that USB 3.x devices connected via USB4 ports operate at their native speeds, up to 20 Gbps in compatible configurations.[24] The PCI I/O adapter manages PCIe transaction layer packets by encapsulating them into USB4 tunnels, incorporating PCIe-native error correction mechanisms such as acknowledgments and negative acknowledgments (ACK/NAK) for reliable data transfer, along with retry protocols to handle transmission errors.[24] This adapter interfaces with internal PCIe switches or root complexes, enabling applications like external storage and graphics processing units by maintaining end-to-end PCIe integrity over the USB4 link.[36] The DP I/O adapter handles DisplayPort protocol tunneling by packing and unpacking video streams, supporting single-stream transport (SST) or multi-stream transport (MST) across 1 to 4 lanes at rates from reduced bit rate (RBR) to high bit rate 3 (HBR3).[24] It manages the DP AUX channel for control signaling and synchronizes the main link using time management units (TMUs) to ensure low-latency video delivery without intermediate buffering.[36] During operation, input and output DP adapters coordinate link training progress via configuration packets to maintain synchronization. Adapter negotiation occurs during USB4 link training and initialization, where adapters declare their capabilities through USB4 entry packets and sideband channel communications, allowing the connection manager to configure paths based on detected protocols and bandwidth needs.[24] This process, part of the five-phase link initialization, involves lane adaptation state machines that negotiate Gen 2 (10 Gbps) or Gen 3 (20 Gbps) speeds before proceeding to protocol-specific setup.[37] In USB4 Version 2.0, protocol adapters receive enhancements to support higher-performance tunneling, including compatibility with DisplayPort 2.0 for ultra-high bit rate (UHBR) modes and elevated PCIe speeds leveraging the 80 Gbps physical layer, enabling more efficient use of the increased bandwidth for USB 3.2, DP, and PCIe traffic. These adapters also incorporate firmware updatability provisions, allowing post-deployment updates to optimize protocol handling and compatibility via USB4's configuration layer.Physical Layer and Signaling
Signaling Modes
USB4 employs multiple signaling modes to support varying bandwidth requirements and ensure compatibility with legacy USB standards. The primary signaling mode for high-speed operation in USB4 version 1.0 utilizes Non-Return-to-Zero (NRZ) signaling at a symbol rate of 20 GT/s per lane, enabling an aggregate data rate of 40 Gbps across two lanes.[18] USB4 version 1.0 also supports Pulse Amplitude Modulation with 3 levels (PAM3) at 22.5 GT/s per lane when operating in Thunderbolt 3 tunneling mode for compatibility. This provides higher spectral efficiency in that context while maintaining compatibility with existing USB Type-C cabling. For lower-speed fallback operations, USB4 supports USB 3.2 Gen 2x2 at 20 Gbps or Gen 2 at 10 Gbps, both using Non-Return-to-Zero (NRZ) signaling with binary levels.[12] These modes ensure backward compatibility with previous USB generations by negotiating the link speed during initialization. The link training process is managed by the Link Training and Status State Machine (LTSSM), an extension of the USB 3.x protocol, which handles mode detection, equalization, and synchronization.[38] In USB4 version 2.0, forward error correction (FEC) using Reed-Solomon coding is introduced to enhance reliability at higher speeds, correcting up to 12 symbol errors per block to achieve a bit error rate below 10^{-19}. The electrical characteristics include a transmitter (TX) differential output swing of 0.8 to 1.2 V, optimized for signal integrity over typical cable lengths.[39] Receivers (RX) incorporate adaptive equalization capable of up to 40 dB of loss compensation to mitigate channel impairments such as attenuation and crosstalk.[40] USB4 version 2.0 introduces enhancements with PAM3 signaling at 25.6 GT/s per lane, supporting 80 Gbps symmetric or 120 Gbps asymmetric operation (using three lanes for transmit and one for receive), along with improved adaptive equalization for longer reach active cables. These pin assignments for signaling are defined within the USB Type-C connector standard.[1]Pinout and Connectors
USB4 employs the USB Type-C connector, which consists of 24 pins arranged in two symmetric rows (A1–A12 and B1–B12) to enable reversible, orientation-independent connections without signal remapping. The high-speed differential pairs—TX1± (A2/A3), RX1± (B2/B3), TX2± (A11/A12), and RX2± (B10/B11)—are reused for USB4 signaling, supporting two lanes for data rates up to 40 Gbps in Version 1.0 and 80 Gbps in Version 2.0.[41] Additional pins include VBUS (A6, A9, B6, B9) for power delivery up to 240 W in Version 2.0, GND (A1, A12, B1, B12) for grounding, D+ and D- (A4/A5, B4/B5) for legacy USB 2.0 signaling, CC1 and CC2 (A7, B7) for cable orientation detection and configuration channel communication, and SBU1/SBU2 (A8, B8) for sideband use, including mapping to SBTX/SBRX in USB4 operation and fallback to DisplayPort Alternate Mode. The pinout ensures flipping the connector swaps the TX/RX pairs (e.g., TX1 becomes RX1), maintaining full functionality through protocol-level adaptation.| Pin | Row A Signal | Row B Signal |
|---|---|---|
| 1 | GND | GND |
| 2 | TX1+ | RX1+ |
| 3 | TX1- | RX1- |
| 4 | D+ | D+ |
| 5 | D- | D- |
| 6 | VBUS | VBUS |
| 7 | CC1 | CC2 |
| 8 | SBU1 | SBU2 |
| 9 | VBUS | VBUS |
| 10 | RX2- | TX2- |
| 11 | RX2+ | TX2+ |
| 12 | GND | GND |