8250 UART
The 8250 UART, formally known as the INS8250 Universal Asynchronous Receiver/Transmitter, is an integrated circuit developed by National Semiconductor that serves as a serial data input/output interface in microcomputer systems, performing serial-to-parallel conversion on data characters received from peripherals or modems and parallel-to-serial conversion on data to be transmitted.[1] It supports programmable asynchronous communication, including the addition or deletion of start, stop, and parity bits, and operates with an 8-bit bidirectional data bus for configuration by system software.[1] Key features of the 8250 UART include a programmable baud rate generator capable of divisors from 1 to 65,535 using a 16x clock input, enabling baud rates from DC up to 56 kbaud with standard crystals such as 1.8432 MHz or 3.072 MHz; full programmability for 5- to 8-bit characters, even/odd/no parity options, and 1/1.5/2 stop bits; modem control functions via signals like CTS, RTS, DSR, DTR, RI, and DCD; and an interrupt system with prioritized handling for receiver ready, transmitter empty, line status changes, and modem status.[1] The chip also provides line status reporting, diagnostic capabilities such as internal loopback testing, and compatibility with popular microprocessors through its 40-pin DIP package, operating at +5V ±5% and temperatures from 0°C to +70°C.[1] Introduced in the late 1970s and widely adopted in the early 1980s, the 8250 UART gained prominence through its inclusion in the original IBM Personal Computer (IBM PC) released in 1981, where it handled serial port communications for peripherals like modems and printers, establishing a standard for PC serial interfaces.[2] Later revisions, such as the 8250A and 8250B, offered improved timing and reliability while maintaining pin and functional compatibility, paving the way for successors like the NS16450 (with enhanced AC characteristics) and the NS16550 (adding FIFO buffers for higher throughput).[3] Despite its limitations, such as single-byte buffering that restricted effective baud rates to around 9600 on slower systems, the 8250's register-based architecture influenced serial communication design for decades.Overview
Introduction
The 8250 UART is an integrated circuit developed by National Semiconductor for asynchronous serial data transmission and reception. It serves as a programmable communications interface that converts parallel data from a CPU or microprocessor into serial format for transmission over a communication line and reconstructs serial data into parallel format upon reception.[4] The primary role of the 8250 UART is to facilitate communication between computers and external peripherals, such as modems, printers, and terminals, by managing serial I/O operations in microcomputer systems. Introduced in the late 1970s, the chip gained immense popularity and was widely cloned by other manufacturers, including Western Digital with its WD8250 variant, making it a foundational component in early personal computing hardware.[5] In asynchronous communication as implemented by the 8250 UART, data frames begin with a start bit to synchronize the receiver, followed by 5 to 8 data bits, an optional parity bit for basic error checking, and one or more stop bits to signal the frame's end. This framing structure allows flexible, clockless data exchange without requiring a shared clock signal between sender and receiver, distinguishing UARTs from synchronous protocols.[4]Key Specifications
The 8250 UART operates on a supply voltage of +5 V ±10%, with an average power consumption of 80 mA.[1] It is typically housed in a 40-pin dual in-line package (DIP), though variants may use a 44-lead plastic chip carrier.[6] The chip supports baud rates up to 115,200 baud using a standard 1.8432 MHz crystal oscillator, but standard configurations using a 1.8432 MHz crystal oscillator limit practical rates to 115,200 bps for common asynchronous serial communications.[1] In early personal computer systems, effective throughput was often restricted to 9,600 bps due to the 1 ms interrupt latency typical of operating systems like MS-DOS, which could lead to data overruns if the CPU failed to service interrupts promptly at higher speeds.[7] Data buffering consists of a single-byte receiver buffer and a single-byte transmitter holding register, lacking deeper FIFO storage and thus increasing the risk of overrun errors during reception at elevated baud rates where inter-byte timing is short.[8] Supported asynchronous data formats include 5 to 8 data bits per character, with 1, 1.5, or 2 stop bits (1.5 stop bits applicable only to 5-bit formats), and optional parity generation and checking (even, odd, or none).[6] Baud rate generation requires an external timing reference clock, conventionally 1.8432 MHz for precise alignment with standard rates such as 300, 1,200, 2,400, 4,800, 9,600, 19,200, 38,400, 57,600, and 115,200 bps, achieved by programmable division of the input clock.[6]Architecture
Internal Components
The 8250 UART integrates several major functional blocks to facilitate asynchronous serial communication, including the receiver, transmitter, programmable baud rate generator, modem control logic, and interrupt logic. These components interconnect via an internal 8-bit data bus that interfaces with the CPU, allowing software access to configuration and status registers. The baud rate generator provides a 16x oversampled clock signal to both the receiver and transmitter shift registers for precise timing, while the modem control and interrupt blocks handle external signaling and event prioritization, respectively.[6][4] The receiver block converts incoming serial data into parallel format using a shift register that assembles bits from the serial input line (SIN) over multiple clock cycles. It includes a parity checker to verify data integrity by computing even or odd parity as programmed, flagging errors in the line status register (bit 2 for parity error, PE). Overrun detection monitors for data loss when new incoming data arrives before the previous byte is read from the receiver buffer register, setting the overrun error flag (bit 1, OE) in the same register. These mechanisms ensure reliable reception of 5- to 8-bit characters with configurable stop bits and parity options.[6][4] The transmitter block serializes parallel data for output, employing a shift register to output bits sequentially on the serial output line (SOUT), appending start, parity, and stop bits as configured. It features a transmit holding register that buffers a single byte of data from the CPU before loading it into the shift register, allowing double-buffering to prevent transmission gaps; the transmitter holding register empty (THRE) status is indicated in the line status register (bit 5). This design supports efficient data flow without requiring constant CPU intervention during transmission.[6][4] The modem control block manages handshaking and status signals for interfacing with modems or similar devices, controlling outputs such as Request to Send (RTS) and Data Terminal Ready (DTR) via the modem control register, and monitoring inputs including Clear to Send (CTS), Data Set Ready (DSR), Data Carrier Detect (DCD), and Ring Indicator (RI). These signals enable flow control and connection status detection, with changes in input lines reflected in the modem status register for CPU polling or interrupt triggering. The block supports both modem-specific operations and general-purpose I/O modes.[6][4] The interrupt logic prioritizes and generates interrupts based on four sources to alert the CPU to key events, using a fixed hierarchy: receiver line status (highest priority, covering errors like overrun or parity), received data available, transmitter holding register empty, and modem status changes (lowest priority). This prioritization is encoded in the interrupt identification register, which identifies the active source, while the interrupt enable register allows selective masking. The logic outputs a single interrupt signal (INTR) when enabled conditions occur, facilitating efficient event handling in multitasking environments.[6][4]Registers
The 8250 UART employs eight memory-mapped registers, selected by the three least significant bits of the address bus (A2–A0), to provide the interface for configuration, data transfer, status monitoring, and interrupt management. These registers are located at offsets from a base I/O port address, such as 0x3F8 for the first serial port in IBM PC-compatible systems. Access to certain registers, particularly those related to baud rate programming, is controlled by the Divisor Latch Access Bit (DLAB) in the Line Control Register. The original 8250 lacks dedicated FIFO buffering, using single-byte holding registers instead, which can limit performance under high data rates due to potential overrun errors.[1] The register map is as follows:| Offset (hex) | DLAB | Register Name | Access Mode |
|---|---|---|---|
| 0x00 | 0 | RBR (Receiver Buffer Register) | Read only |
| 0x00 | 0 | THR (Transmitter Holding Register) | Write only |
| 0x00 | 1 | DLL (Divisor Latch LSB) | Read/Write |
| 0x01 | 0 | IER (Interrupt Enable Register) | Read/Write |
| 0x01 | 1 | DLM (Divisor Latch MSB) | Read/Write |
| 0x02 | - | IIR (Interrupt Identification Register) | Read only |
| 0x03 | - | LCR (Line Control Register) | Read/Write |
| 0x04 | - | MCR (Modem Control Register) | Read/Write |
| 0x05 | - | LSR (Line Status Register) | Read only |
| 0x06 | - | MSR (Modem Status Register) | Read only |
| 0x07 | - | SCR (Scratch Register) | Read/Write |
Pinout and Interfaces
The 8250 UART is packaged in a 40-pin dual in-line package (DIP), providing interfaces for microprocessor buses, serial data lines, modem control, clock generation, and power. This configuration enables seamless integration into early computing systems for asynchronous serial communication, supporting data rates up to 115.2 kbps under typical conditions. The pin assignments are optimized for compatibility with 8-bit microprocessors like the Intel 8080 or Z80, using TTL-compatible logic levels.[10] The parallel data interface connects to the host processor via an 8-bit bidirectional data bus on pins 18 through 25 (D0 to D7, with D0 on pin 25 and D7 on pin 18), which transfers register data and configuration commands in tri-state mode to avoid bus conflicts. Address decoding for the registers occurs through A0 on pin 28, A1 on pin 27, and A2 on pin 26, allowing selection of specific registers during read or write operations. Control signals include chip select (CS, active low) on pin 29 to enable the device, read strobe (/RD, active low) on pin 24 to latch data from the UART to the bus, and write strobe (/WR, active low) on pin 25 to load data from the bus into the UART; these signals ensure synchronized access in Intel bus architectures. The interrupt request output (INTRPT, open-drain) on pin 30 signals the processor of events like data ready or modem status changes, requiring a pull-up resistor.[10] Serial data interfaces are provided by the receiver input (SIN) on pin 10, which accepts asynchronous TTL-level serial data from external devices or modems, and the transmitter output (SOUT) on pin 11, which outputs serialized TTL-level data; both support configurable word lengths of 5 to 8 bits, with start/stop bits and optional parity. These pins form the core RS-232 physical layer interface when connected through level shifters like the 1488/1489 transceivers.[10] Modem control interfaces enable hardware handshaking and status monitoring, with request to send (RTS, active low output) on pin 32 to request transmission clearance, clear to send (CTS, active low input) on pin 36 indicating remote readiness, data set ready (DSR, active low input) on pin 37 from modem indicating operational status, data terminal ready (DTR, active low output) on pin 33 signaling local readiness, data carrier detect (DCD, active low input) on pin 38 detecting carrier signal, and ring indicator (RI, active low input) on pin 39 for incoming call detection. These TTL-level signals can trigger interrupts for changes in modem state, supporting full-duplex communication in dial-up applications.[10] Clocking for baud rate generation uses input (XIN) on pin 16 and output (XOUT) on pin 17, typically driven by a 1.8432 MHz crystal oscillator to produce standard baud rates (e.g., 300, 1200, 9600) via an internal divider; an external clock can alternatively be applied to XIN with XOUT left open. Power is supplied at +5 V DC on Vcc (pin 40), with multiple ground returns on pins 7, 20, and 31 to minimize noise and ensure stable operation across the full temperature range of 0°C to 70°C.[10]| Pin | Signal | Type | Function |
|---|---|---|---|
| 7 | GND | Supply | Ground |
| 16 | XIN | Input | Crystal oscillator input |
| 17 | XOUT | Output | Crystal oscillator output |
| 18 | D7 | Bidirectional | 8-bit data bus (MSB) |
| 19 | D6 | Bidirectional | 8-bit data bus |
| 20 | GND | Supply | Ground |
| 21 | D5 | Bidirectional | 8-bit data bus |
| 22 | D4 | Bidirectional | 8-bit data bus |
| 23 | D3 | Bidirectional | 8-bit data bus |
| 24 | /RD | Input | Read strobe (active low) |
| 25 | D0 | Bidirectional | 8-bit data bus (LSB) |
| 26 | A2 | Input | Address input MSB for register selection |
| 27 | A1 | Input | Address input |
| 28 | A0 | Input | Address input LSB for register selection |
| 29 | /CS | Input | Chip select (active low) |
| 30 | INTRPT | Output | Interrupt request (open drain) |
| 31 | GND | Supply | Ground |
| 32 | RTS | Output | Request to send (active low) |
| 33 | DTR | Output | Data terminal ready (active low) |
| 36 | CTS | Input | Clear to send (active low) |
| 37 | DSR | Input | Data set ready (active low) |
| 38 | DCD | Input | Data carrier detect (active low) |
| 39 | RI | Input | Ring indicator (active low) |
| 40 | Vcc | Supply | +5 V power supply |
| 10 | SIN | Input | Serial data input (TTL level) |
| 11 | SOUT | Output | Serial data output (TTL level) |
Operation
Data Transmission
The data transmission process in the 8250 UART begins when the CPU loads a data byte into the Transmitter Holding Register (THR).[6] The Transmitter Holding Register Empty (THRE) flag in the Line Status Register (LSR) is then set to indicate that the THR is empty and ready for the next byte, which resets the flag upon loading.[6] Once loaded, the byte is automatically transferred to the internal Transmitter Shift Register (TSR) when the latter is available, initiating the serial output on the SOUT pin.[11] The transmission sequence follows a standard asynchronous format: the UART shifts out a start bit (logic 0), followed by 5 to 8 data bits transmitted least significant bit (LSB) first, an optional parity bit if enabled, and 1 or 2 stop bits (logic 1).[6][2] The word length, parity selection, and number of stop bits are configured via the Line Control Register (LCR).[11] After the final stop bit, the transmitter returns to the idle state where SOUT remains high (logic 1, marking state) until new data is loaded.[6] The transmitter operates in distinct states: idle, with SOUT held high; loading, when data is written to the THR; and shifting, during which the TSR serially outputs the formatted byte at the programmed baud rate.[6] The Transmitter Empty (TEMT) flag in the LSR indicates when both the THR and TSR are empty, confirming completion of transmission.[11] The 8250 UART does not generate native transmit error conditions such as underrun flags; however, to prevent transmission gaps or incomplete frames due to delayed data loading, software must poll the THRE flag before writing to the THR, ensuring timely transfer to the TSR.[6] Break transmission, used to signal an interrupt or reset on the line, is initiated by setting bit 6 of the LCR to logic 1, which forces SOUT to a continuous spacing state (logic 0) for an indefinite duration until the bit is cleared.[6] In loopback mode (enabled via the Modem Control Register, MCR), bit 4 of the MCR can also control break output.[6]Data Reception
The 8250 UART receives serial data through the SIN (Serial Input) pin in an asynchronous format, beginning with the detection of a start bit, which is a falling edge transition from logic 1 (mark) to logic 0 (space). Upon detecting this transition, the receiver synchronizes its internal timing and initiates the sampling process for the subsequent data bits. The receiver uses a 16x oversampling clock derived from the baud rate generator to sample the input signal at the midpoint of each bit period, ensuring accurate bit detection despite potential noise or timing variations. This oversampling technique divides each bit time into 16 intervals, with samples taken after 8 intervals for the start bit confirmation and 8, 24, 40, etc., for data bits.[6] The receiver operates through distinct states: idle, where it continuously monitors SIN for the start bit; start bit detection and verification, involving two samples to confirm the logic 0 state; data bit sampling, shifting each of the 5 to 8 data bits (depending on configuration) into the receive shift register (RSR) on the rising edge of the sampling clock; and stop bit verification, checking for one or more logic 1 bits to validate the frame. If parity is enabled, an additional parity bit is sampled and checked immediately after the data bits. Once the full frame is received without errors, the assembled byte is transferred from the RSR to the receiver buffer register (RBR). In case of a framing error, the receiver attempts to resynchronize by sampling the next potential start bit twice.[6][12] Error detection is integral to the reception process, with flags set in the line status register (LSR) to indicate issues. An overrun error occurs if a new complete character arrives and is transferred to the RSR before the previous byte is read from the RBR, causing data loss (LSR bit 1). A parity error is flagged if the received parity bit does not match the computed parity for the data bits when parity generation is enabled (LSR bit 2). Framing errors are detected when the stop bit(s) are not logic 1, indicating a misalignment or noise-induced corruption (LSR bit 3). A break condition is recognized when SIN remains at logic 0 for more than a full character frame, typically signaling a line break or fault (LSR bit 4). These errors do not prevent further reception but must be handled by software to maintain data integrity.[6][12] The RBR serves as a single-byte holding register for received data in the 8250, lacking the FIFO buffering found in later variants. Upon transfer from the RSR, the data ready (DR) flag in the LSR (bit 0) is set to logic 1, potentially triggering a receiver data available interrupt if enabled in the interrupt enable register (IER). Reading the RBR clears the DR flag and resets the interrupt, allowing the next byte to be stored. If the RBR is not read in time, subsequent data leads to an overrun, highlighting the need for timely polling or interrupt-driven handling in software.[6][12]Baud Rate Generation
The baud rate generator in the 8250 UART is a programmable 16-bit binary counter that divides an input timing reference clock to produce the bit rate for serial transmission and reception.[6] It consists of two 8-bit latches forming the divisor, which can range from 1 to 65,535 (2^16 - 1), and generates a 16× clock output for the transmitter logic, with an option to route it to the receiver via the BAUDOUT pin.[6] The input clock typically operates at 1.8432 MHz to enable precise standard baud rates, though it supports frequencies from DC to 3.1 MHz.[1] To program the baud rate, the divisor value is loaded into the Divisor Latch Low (DLL) and Divisor Latch High (DLM) registers, accessed only when the Divisor Latch Access Bit (DLAB) in the Line Control Register is set to 1.[6] The resulting baud rate is calculated as the input clock frequency divided by (16 × divisor), where the factor of 16 accounts for the 16× oversampling used in the UART's shift registers.[6] For example, with a 1.8432 MHz clock, a divisor of 12 yields 9600 baud, since 1,843,200 / (16 × 12) = 9,600 Hz exactly.[6] Common baud rates are achieved using specific integer divisors with the 1.8432 MHz clock, ensuring minimal error for rates up to 38,400 baud.[6] The following table lists representative divisors for standard rates:| Baud Rate (bps) | Divisor (decimal) |
|---|---|
| 300 | 384 |
| 1200 | 96 |
| 2400 | 48 |
| 4800 | 24 |
| 9600 | 12 |
| 19,200 | 6 |
| 38,400 | 3 |