Universal asynchronous receiver-transmitter
A Universal Asynchronous Receiver-Transmitter (UART) is a hardware communication protocol and peripheral interface that enables asynchronous serial data transmission between devices, converting parallel data from a microprocessor or computer into serial format for transmission and reversing the process for received serial data.[1] It operates without a shared clock signal, instead using start and stop bits to frame each data packet and a pre-agreed baud rate to synchronize the sender and receiver, ensuring reliable point-to-point or multi-drop communication.[2] This design allows for full-duplex operation over two wires (transmit and receive lines), making it suitable for short-distance connections in embedded systems.[3] The UART was developed in the early 1960s, initially to address the need for interfacing teletypes with early computers such as the PDP-1 by converting parallel signals to serial ones for efficient data handling.[4] Iconic implementations, like the Western Digital WD1402A introduced in 1971, became foundational in personal computers and became part of the IEEE Spectrum's Chip Hall of Fame for their role in enabling widespread serial I/O.[4] Over decades, UART standards evolved from early asynchronous designs to include features like FIFO buffers for reducing CPU overhead, with modern variants supporting baud rates up to several megabits per second while maintaining backward compatibility.[5] Key features of UART include configurable frame formats with 5 to 8 data bits, optional even/odd parity for error detection, and 1 or 2 stop bits, often implemented with hardware flow control (e.g., RTS/CTS) to manage data flow and prevent overruns.[5] It supports interrupt-driven or polled operation modes, and in advanced peripherals, integrated FIFOs (up to 16 bytes or more) buffer data to handle varying transmission speeds without stalling the processor.[5] These attributes contribute to its low complexity and cost-effectiveness, requiring minimal pins and no external clock line, though it is limited to relatively low speeds compared to synchronous protocols like SPI or I2C.[6] UART finds extensive applications in embedded and microcontroller-based systems for tasks such as debugging via serial consoles, interfacing with peripherals like GPS receivers, Bluetooth modules, and sensors, and connecting to legacy equipment using standards like RS-232 or RS-485.[3] In IoT devices, it serves as a bridge for wireless modules and human-machine interfaces, while in industrial settings, it enables reliable data exchange in automation and control systems due to its robustness against simple transmission errors.[7] Its enduring popularity stems from ease of implementation in software and hardware, supporting both full-duplex exchanges and half-duplex modes in multi-device networks.[6]Fundamentals
Definition and Purpose
The Universal Asynchronous Receiver-Transmitter (UART) is an integrated circuit (IC) or embedded peripheral module designed to handle asynchronous serial port communication between electronic devices, such as microcontrollers and peripherals. It functions by converting parallel data from a processor's data bus into a serial bit stream for transmission and, upon reception, deserializing the incoming serial data back into parallel format for processing by the host device.[1][8] The primary purpose of a UART is to enable efficient, point-to-point data exchange in full-duplex mode over minimal wiring, typically two lines for transmit and receive, facilitating connections between computers, embedded systems, and devices like sensors or modems without requiring additional synchronization hardware. This conversion process allows processors, which natively handle parallel data, to interface with serial transmission media, such as RS-232 cables, supporting applications in debugging, control systems, and low-speed data logging.[9][8][10] Fundamentally, a UART's architecture includes parallel input/output registers interfaced with shift registers to perform serialization (transmitter side) and deserialization (receiver side), forming a basic block diagram of data bus connections to serial lines. Its asynchronous operation distinguishes it from synchronous protocols like SPI by forgoing a continuous shared clock signal, instead depending on mutually agreed baud rates—such as 9600 or 115200 bits per second—for timing synchronization, with start and stop bits delimiting each data frame to maintain alignment.[8]Key Characteristics
UART employs several key configurable parameters to adapt to diverse communication needs. The data word length, which represents the payload of each transmitted frame, is typically adjustable from 5 to 9 bits, though 7 or 8 bits are the most prevalent configurations for standard applications. Parity settings offer options such as none, even, odd, mark, or space, allowing the inclusion of an optional bit to detect single-bit errors in the data stream. Additionally, the number of stop bits can be set to 1, 1.5, or 2, providing flexibility in frame termination to accommodate varying synchronization tolerances between transmitter and receiver.[11][12][12] Baud rate, defining the transmission speed in bits per second, spans a wide range in UART systems, with common values from 300 bps to 115,200 bps suitable for legacy and general-purpose uses. Modern UART variants, integrated into high-performance microcontrollers, extend this capability to rates exceeding 1 Mbps, and up to 5 Mbps in some implementations.[13][14][15] A defining feature of UART is its support for full-duplex communication, facilitated by independent TX and RX lines that permit simultaneous data transmission and reception without interference. For error detection, UART relies on built-in parity checking as its primary mechanism, offering rudimentary validation of data integrity across each frame, though it does not incorporate more robust methods like CRC for multi-bit error correction.[16][8] The protocol's inherent simplicity contributes to its widespread adoption, requiring only a minimal pin count—typically just TX and RX for basic operation, with optional RTS and CTS pins for hardware flow control—while eliminating the need for an external clock signal through asynchronous timing derived from embedded start and stop bits.[17][18]Operation
Data Framing
In UART communication, the data frame defines the structure of each transmitted packet to ensure reliable asynchronous transfer without a shared clock signal. A typical frame begins with a start bit, which is a logic low (0) signal that indicates the onset of data transmission and allows the receiver to detect the beginning of the frame through edge detection.[8] This start bit synchronizes the receiver's internal timing, enabling it to sample subsequent bits at the agreed baud rate without prior clock alignment.[11] Following the start bit, the frame includes 5 to 8 data bits, transmitted least significant bit (LSB) first, which carry the actual payload information.[5] An optional parity bit may follow the data bits to provide basic error detection by checking the evenness or oddness of the data; if even parity is selected, the bit is set to make the total number of 1s even, and vice versa for odd parity.[19] The frame concludes with 1 or 2 stop bits, which are logic high (1) signals that mark the end of the transmission and return the line to its idle state of continuous logic 1.[20] The most common frame format is 8N1, consisting of 8 data bits, no parity, and 1 stop bit, widely used in applications like serial console interfaces due to its balance of efficiency and simplicity.[21] Prior to transmission, the communication line remains in an idle state at logic 1, ensuring the start bit's falling edge is clearly detectable.[22] A key potential issue in data framing is the framing error, which occurs when a baud rate mismatch between transmitter and receiver causes the stop bit to be sampled incorrectly, often resulting in an unexpected logic level; this error is detected by verifying that the stop bit(s) are at the expected logic 1.[11]Transmission Process
The transmission process in a UART begins when parallel data from the host processor is written to the transmit holding register (THR).[9] If the transmit shift register (TSR) is empty, the THR data is immediately transferred to the TSR, emptying the THR and setting the transmit holding register empty (THRE) flag in the line status register (LSR). This transfer triggers an interrupt to the host if THRE interrupts are enabled, allowing the processor to load the next byte into the THR without waiting for the current transmission to complete.[9] Once loaded into the TSR, the data undergoes serialization for output on the TX line, which is held idle at a logic high level when not transmitting.[8] The process appends a start bit (logic low) to the beginning of the frame, transitioning the TX line from high to low to signal the receiver.[9] This is followed by the data bits—typically 5 to 8 bits, starting with the least significant bit (LSB)—shifted out serially from the TSR at precise intervals determined by the baud rate clock.[8] If parity is enabled, a parity bit is inserted after the data bits to provide error checking, calculated based on the configured parity mode (odd, even, mark, or space). The frame concludes with one or more stop bits (logic high), restoring the TX line to its idle state and marking the end of the transmission.[9] The shift register operates as a parallel-in, serial-out device, clocked by the baud rate generator to ensure each bit duration matches the configured baud rate.[8] During transmission, the TSR remains dedicated to the current byte until all bits, including start, data, parity, and stop, are output, preventing new data from interrupting the process. In UARTs with FIFO buffers, multiple bytes can be queued in a transmit FIFO before shifting into the TSR, enhancing throughput by reducing interrupt overhead.[9] Hardware flow control, such as RTS/CTS, integrates into the transmission to manage data flow and prevent receiver overrun.[8] The transmitter monitors the CTS signal from the receiver; if CTS is deasserted (low), the UART pauses after completing the current byte, holding subsequent bytes in the THR or FIFO until CTS is reasserted. This ensures reliable communication in bidirectional links where receiver buffer capacity varies. A typical timing diagram for UART transmission illustrates the bit sequence over time, with the horizontal axis representing baud rate intervals:- Idle: TX high (logic 1).
- Start bit: TX low (logic 0) for one baud interval.
- Data bits: 8 bits shifted LSB first, each held for one baud interval (e.g., 01010101 for byte 0x55).
- Parity bit (if enabled): One baud interval, e.g., 1 for even parity.
- Stop bits: One or two baud intervals at high (logic 1).