BASIC Stamp
The BASIC Stamp is a family of small, programmable microcontroller modules developed by Parallax Inc., designed to simplify embedded systems prototyping and education by allowing users to program in a BASIC-like language called PBASIC without requiring expertise in low-level assembly or C code.[1][2] Each module integrates a PIC microcontroller-based interpreter chip, EEPROM for program storage, RAM for variables, a voltage regulator, and multiple general-purpose input/output (I/O) pins to interface with sensors, motors, displays, and other hardware components.[3][4] Invented by Parallax co-founder Chip Gracey and first released in 1992 as the BS1 module, the BASIC Stamp was named for its compact, postage stamp-sized form factor, which made it accessible for hobbyists, educators, and engineers.[1] The lineup expanded with the more capable BS2 in 1995, introducing enhanced PBASIC features, followed by variants such as the BS2px, BS2e, and others through the early 2000s—including PBASIC 2.5 in 2003 with structured programming elements like IF-THEN-ELSE and subroutines—each offering improvements in speed, memory, and I/O count.[1] PBASIC, the core programming language, executes as a single linear process with simple, case-insensitive syntax optimized for beginners, translating high-level commands directly into machine code for tasks like pulse-width modulation, capacitive voltage measurement (e.g., via RCTIME), and serial communication.[2][5] The BASIC Stamp significantly influenced the microcontroller hobbyist and educational communities, with over 3 million units in use by 2002 and powering initiatives like Parallax's "Stamps in Class" program launched in 1997, which included robotics kits such as the Boe-Bot for teaching STEM concepts in schools and universities.[1] Its emphasis on rapid prototyping and readability democratized microcontroller programming, fostering innovation in fields from robotics to industrial automation while remaining relevant for legacy and educational applications as of 2025, although several variants reached end-of-life in 2024.[1][6][7]History and Development
Origins and Founding
Parallax Inc. was founded in 1986 by Chip Gracey and Lance Walley, who operated initially from their apartment under the name Innovative Software Engineering. The company's early efforts centered on developing tools for personal computing, including sound digitizers and programming hardware for the Apple II, as well as programmers for microcontrollers like the 8051 and PIC series. By 1990, Parallax released its PIC Programmer, a product that gained enough traction to be acquired by Microchip Technology, reflecting the growing demand for accessible microcontroller development tools.[1] Building on this foundation, Parallax developed the first BASIC Stamp module in 1992, utilizing a PIC16C56 microcontroller from Microchip with an embedded PBASIC interpreter stored in ROM. This design aimed to simplify programming for hobbyists by providing a high-level BASIC-like language, eliminating the need for low-level assembly code typically required for PIC devices. The module's compact form factor, measuring roughly the size of a postage stamp, inspired its name—"Stamp" for its diminutive scale, combined with the BASIC interpreter functionality.[1][8] The BASIC Stamp targeted electronics educators and hobbyists who sought an approachable alternative to complex microcontroller programming, prioritizing ease of use and rapid prototyping over raw computational power. Initially released as a kit priced at $139, it quickly became a staple in educational and prototyping environments, fostering hands-on learning in embedded systems.[1][9]Key Milestones and Evolution
The BASIC Stamp 2 was released in 1995, utilizing the PIC16C57 microcontroller from Microchip Technology, which doubled the execution speed from approximately 2,000 to 4,000 PBASIC instructions per second and increased the number of I/O pins to 16 compared to the original BASIC Stamp 1's 8 pins.[1][3][10] In 1998, Parallax formed a partnership with Scenix Semiconductor (later rebranded as Ubicom) to develop the SX series microcontroller, leading to the integration of this technology in the BASIC Stamp 2sx module launched in 2001, which supported clock speeds up to 50 MHz for enhanced performance over prior models.[1][11] The BS2p series debuted in 2003, incorporating the PIC16F57 microcontroller and maintaining the 2K bytes of EEPROM for program storage while introducing expanded capabilities, with subsequent variants including the low-power BS2pe and the high-speed BS2px to address diverse application needs.[3][12] Parallax expanded beyond traditional PBASIC-based modules with the Java-programmable Javelin Stamp in 2002 and the Propeller-based Spin Stamp in 2006, which utilized the SPIN language, although these were positioned as complementary rather than core evolutions of the BASIC Stamp line.[13][14] Following the 2006 introduction of the Spin Stamp, development of new PBASIC-compatible BASIC Stamp models declined as Parallax shifted emphasis toward the Propeller platform and other innovations, coinciding with the emergence of the open-source Arduino in 2005, which offered greater flexibility and lower costs for hobbyists.[1][15] As of 2025, Parallax continues to provide ongoing support for legacy BASIC Stamp models, including software tools, documentation, and sales of remaining inventory like the BS2-IC, ensuring compatibility for educational and legacy applications.[16][17]Technical Overview
Hardware Components
The BASIC Stamp modules are compact microcontroller boards designed for easy integration into prototypes and educational projects. The BS1 features a 14-pin single in-line package (SIP) with dimensions of approximately 1.41 x 0.40 inches, while models from the BS2 series and later use a standard 24-pin dual in-line package (DIP) with a footprint of approximately 0.6 inches by 0.7 inches, facilitating straightforward breadboarding and soldering onto custom PCBs.[3][18] At the core of each module is a PBASIC interpreter chip based on a Microchip PIC microcontroller, such as the PIC16C56 for the BASIC Stamp 1 or the PIC16C57 for the BASIC Stamp 2, which executes the interpreted PBASIC code and manages overall operation.[19][18] Program storage occurs in an onboard serial EEPROM, providing non-volatile memory capacities ranging from 256 bytes in the BASIC Stamp 1 to 2 kilobytes in the BASIC Stamp 2, allowing users to store PBASIC programs and data that persist without power.[20][3] The interpreter chip itself uses one-time programmable (OTP) ROM to hold the PBASIC interpreter firmware, ensuring reliable execution without modifiable code in that section.[19] Supporting the processor are essential passive and active components for stable operation, including a 5-volt linear voltage regulator that accepts input from 5.5 to 15 volts DC and provides regulated power to the module's internals.[3] A ceramic resonator or optional crystal oscillator generates the clock signal, typically at 4 MHz for the BASIC Stamp 1 and 20 MHz for the BASIC Stamp 2, enabling instruction execution rates suitable for simple control tasks.[18][3] Decoupling capacitors are integrated to filter noise and maintain power stability, while a reset circuit ensures reliable initialization upon power-up.[20] The modules provide 8 to 16 general-purpose input/output (I/O) pins, depending on the model, which operate at TTL levels (0 to 5 volts) and can be configured via PBASIC commands for digital input, output, or limited special functions like pulsed-width modulation, though they lack built-in analog-to-digital or digital-to-analog converters and thus require external circuitry for analog signal handling.[3][21] Volatile RAM, typically 16 to 32 bytes, is available for runtime variables and temporary data storage during program execution.[3] This modular architecture emphasizes simplicity, with all critical elements surface-mounted on a small printed circuit board enclosed in the DIP package for drop-in compatibility with standard development boards.Electrical Specifications and Interfaces
The BASIC Stamp modules, particularly the foundational BASIC Stamp 1 (BS1) and BASIC Stamp 2 (BS2) series, operate on a power supply provided through the VIN pin, accepting 5.5 to 15 VDC unregulated input, which is internally regulated to 5 VDC output at the VDD pin for powering the module and connected components.[22] Current draw varies by model and operating mode; for the BS2, it typically measures 3 mA during run mode and drops to 50 µA in sleep mode under nominal 5 V conditions with no external loads, while the BS1 draws about 1 mA in run mode and 25 µA in sleep.[22] These specifications ensure compatibility with common battery and wall-adapter sources, though total system current must account for attached peripherals to avoid exceeding the internal regulator's capacity of approximately 100 mA.[22] Input/output (I/O) pins on BASIC Stamp modules adhere to TTL-compatible voltage levels, operating between 0 and 5 V, with logic high thresholds around 2.0 V and low below 0.8 V, allowing direct interfacing with standard digital logic families.[21][22] Each I/O pin supports up to 20 mA sourcing and 25 mA sinking current individually, with group limits of 40 mA sourcing and 50 mA sinking across every eight pins to prevent overheating; short-circuit protection is provided via 220 Ω series resistors, limiting peak current to about 23 mA.[22] The BS1 features 8 I/O pins, while the BS2 provides 16, enabling bidirectional digital signal handling without additional level shifters for 5 V systems.[18] Programming occurs via a serial interface using RS-232 levels at 9600 baud (N,8,1) for the BS2 or 4800 baud for the BS1, connected through dedicated pins (SOUT/SIN for BS2, PCO/PCI for BS1) and employing DTR/RTS signals from the host for reset and download mode entry.[22] USB adapters are commonly used for modern hosts, converting to the required serial protocol without altering the module's electrical requirements. Built-in protocol support includes bit-banged I²C via I2CIN and I2COUT commands, 1-Wire via OWIN and OWOUT, PWM generation on up to four channels through the PWM command (producing 0–5 V pulses), and precise servo control using PULSOUT for 1–2 ms pulses at 50 Hz.[22] Environmental operating conditions for BASIC Stamp modules span 0 to 70°C, suitable for indoor prototyping and educational environments, though no integrated ESD protection is included, necessitating external safeguards for robust deployments.[22] Expansion capabilities leverage the I/O pins for direct connections to sensors (e.g., analog via A/D converters), actuators like relays or motors, LCD displays through parallel or serial modes, and other modules via the supported protocols, with total current limits guiding parallel load configurations.[22]Programming Fundamentals
PBASIC Language Syntax
PBASIC is a token-based interpreted programming language designed specifically for the BASIC Stamp microcontroller modules, enabling straightforward control of digital and analog I/O operations. Programs in PBASIC begin with compiler directives such as{$STAMP BS2} to specify the module type and {$PBASIC 2.0} or {$PBASIC 2.5} to indicate the language version, followed by optional sections for defining constants (CON), variables (VAR), and pins (PIN). The program concludes with the END directive, which halts execution and places the module into a low-power mode on BS2 variants. BS1 supports limited subroutines via GOSUB/RETURN (up to 4 nested levels and 16 calls per program), while BS2 provides enhanced support with GOSUB/RETURN allowing up to 4 nested levels (or 16 in some variants) and 255 calls for more modular code structure.[22]
At its core, PBASIC supports basic commands for variable manipulation and control flow. The LET statement assigns values to variables, treating all data as 16-bit unsigned integers with no support for floating-point numbers or native strings (arrays can simulate string handling). For example, LET x = 5 stores the integer 5 in variable x. Pin control uses INPUT pin to configure a pin for reading and OUTPUT pin to set it for writing. Flow control includes FOR...NEXT loops for iteration, such as FOR counter = 1 TO 10 ... NEXT, which executes the body 10 times (BS1 limits nesting to 8 levels, BS2 to 16), and conditional branching with IF...THEN, like IF pin0 = 1 THEN highpin, where BS1 jumps to labels only and BS2 allows inline statements or ELSEIF.[22]
Specialized commands extend PBASIC for hardware interactions. Digital I/O is simplified with HIGH pin to set a pin to logic high (5V) and LOW pin to logic low (0V), e.g., HIGH 0 asserts pin 0. Timing and pulse generation are handled by PULSOUT pin, duration for precise pulses (duration in microseconds, scaled by system clock), commonly used for servo control like PULSOUT 12, 1500, and PWMOUT for continuous pulse-width modulation on BS2. Serial protocols employ SHIFTOUT dataPin, clockPin, mode, [bytes] to transmit data bit-by-bit (modes like LSBPRE for least-significant-bit first) and SHIFTIN for reception, facilitating communication with devices like shift registers. Debugging outputs via serial to a host PC use DEBUG, such as DEBUG "Value: ", DEC var to print a variable in decimal format.[22]
Variables in PBASIC are predefined slots with named aliases, limited to integer types: bits (1-bit), nibbles (4-bit), bytes (8-bit), or words (16-bit). BS1 provides 14 bytes total (e.g., via SYMBOL var = B0), while BS2 offers 26 bytes across B0–B25 (bytes) or W0–W12 (words), declared as var VAR Byte. Access is direct, with no dynamic allocation, and programs store initial values or data in EEPROM at compile time. Program size is constrained by EEPROM capacity: BS1 fits up to 256 bytes (roughly 80–100 tokens, where each command tokenizes to 1–2 bytes), and BS2 up to 2048 bytes (up to 2000+ tokens). The compiler translates source code into these tokens for storage and interpretation.[22]
Error handling in PBASIC omits exceptions or interrupts, relying instead on polling mechanisms for timing and input detection. Commands like PAUSE duration implement non-blocking delays via busy-wait loops, and input functions such as BUTTON or SERIN include optional timeouts to avoid infinite waits, ensuring deterministic behavior in embedded applications. This polling-based approach aligns with the interpreter's sequential execution model on the BASIC Stamp hardware.[22]
Interpreter and Execution Model
The PBASIC interpreter in the BASIC Stamp is a firmware-based system embedded within a Microchip PIC microcontroller, such as the PIC16C57 in the BASIC Stamp 2 (BS2), which executes tokenized PBASIC programs sequentially from EEPROM memory.[23][19] The interpreter chip provides approximately 2048 bytes of EEPROM for storing up to about 500 PBASIC instructions in the BS2 model, with execution occurring at an effective speed of roughly 4,000 PBASIC instructions per second at a 20 MHz clock rate.[23][3] Upon power-up or reset, the interpreter initializes by clearing all RAM to zero and configuring I/O pins as inputs with initial output states low, then begins execution from EEPROM address 0 (or the start of program slot 0 in multi-slot models).[23] The program runs sequentially through the tokenized code, looping back to the beginning unless interrupted by a STOP command, at which point execution halts until reset; otherwise, it reaches the END command, entering a low-power idle mode while retaining EEPROM contents.[23] PBASIC source code is compiled into a compact binary token format by the development tools, where commands and literals are represented as numeric tokens (for example, strings are converted to ASCII byte sequences), and the resulting tokens are downloaded and stored in EEPROM for runtime fetching and decoding by the interpreter.[23] Variable names in the source are resolved to specific RAM locations during tokenization, with the process supporting single-file programs for BS1 and BS2 or multi-file projects (up to eight slots) for advanced models like the BS2p using directives such as{$STAMP BS2p, file2, file3}.[23]
The primary development environment is the BASIC Stamp Editor, a Windows-based IDE available in versions up to 2.5, which provides syntax checking, auto-indentation, simulation via a Debug Terminal, and program download over serial or USB connections.[24][25] It generates tokenized object code for direct EEPROM loading and supports conditional compilation for cross-model compatibility.[23]
Debugging relies on serial I/O commands like SEROUT for output and SERIN for input to communicate with a host PC or peripherals, often paired with the DEBUG command to display variables or strings in decimal, hexadecimal, or other formats directly in the IDE's terminal.[23][26] There are no built-in breakpoints or step-through capabilities; instead, developers use LED indicators on I/O pins or external oscilloscopes for timing analysis, with the Debug Terminal enabling real-time monitoring during execution.[23][27]
Firmware updates for the interpreter are infrequent and typically require purchasing a revised hardware module, as the code is preprogrammed into the PIC's OTP or ROM; however, they maintain backward compatibility across PBASIC versions (e.g., 2.5 is compatible with 2.0 code) and models, allowing older programs to run on newer variants without modification.[23][28]
Models and Variants
BASIC Stamp 1
The BASIC Stamp 1 (BS1), released in 1992 by Parallax, Inc., represents the inaugural model in the BASIC Stamp microcontroller family, designed to simplify embedded programming through an onboard PBASIC interpreter. It is built around a PIC16C56 microcontroller chip, which hosts the interpreter firmware, paired with a 256-byte external serial EEPROM for user program storage and 16 bytes of RAM for variables and operations. This configuration enabled hobbyists and educators to implement control logic without low-level assembly coding, marking a pivotal step in accessible microcontroller technology.[1][20][29] Key hardware specifications include 8 general-purpose I/O pins capable of sourcing up to 20 mA or sinking up to 25 mA per pin, with a total current limit of 40 mA sourcing and 50 mA sinking across all pins. The module operates on 5.5 to 15 VDC (Vin) or 5 VDC (Vdd) at about 1 mA typical current draw, driven by a 4 MHz resonator for an effective execution speed of approximately 2,000 PBASIC instructions per second. Program capacity is constrained to the 256-byte EEPROM, which typically holds around 80 compressed token instructions, emphasizing efficient coding practices.[30][18][31][18] As the simplest iteration, the BS1 supports fundamental PBASIC syntax including FOR...NEXT loops for iteration, BRANCH and GOSUB for flow control, PWM for generating modulated pulses, and PULSOUT for precise timing tasks like servo positioning, alongside 14 byte variables (B0–B13) for data handling. However, its limitations—such as execution speeds in the low thousands of instructions per second, absence of a dedicated SERVO command, and tight memory footprint—restrict it to straightforward applications without complex computations or high-speed requirements. These constraints highlight its role as an entry-level tool focused on core concepts rather than advanced performance.[20] The BS1 remains available in production as of 2025, with the microcontroller module priced at $29 from Parallax, often employed in basic projects involving LEDs, buttons, and simple sensors for educational prototyping. It established the architectural baseline for the BASIC Stamp lineup, influencing the development of enhanced models like the BASIC Stamp 2 that expanded on its foundational design.[18][30]BASIC Stamp 2 and Derivatives
The BASIC Stamp 2 (BS2), released in 1995, marked a significant advancement over its predecessor with its use of the Microchip PIC16C57 microcontroller operating at a 20 MHz oscillator speed, providing 16 general-purpose I/O pins plus 2 dedicated serial pins, 2K bytes of EEPROM for program storage supporting approximately 500 instructions, 32 bytes of RAM accommodating 26 variables, and the full suite of 42 PBASIC2 commands for an effective execution rate of about 4,000 instructions per second.[1][32][33] This model established the core architecture for the BS2 family, emphasizing ease of use in educational and prototyping environments while delivering reliable performance equivalent to roughly 4 MIPS in PBASIC operations.[34] Subsequent derivatives built on the BS2 foundation by enhancing memory capacity, processing speed, I/O options, and power efficiency to address diverse application needs. The BS2e, introduced around 2000, retained the same PIC-based core and 20 MHz speed as the BS2 but added support for up to 16K bytes of external EEPROM across eight 2K-byte slots for expanded program and data storage (up to ~4,000 instructions), along with 64 bytes of scratchpad RAM and 45 PBASIC commands, all at a reduced cost compared to the original.[28][33] The BS2p24 and BS2p40 models, launched in 2003, shifted to the Ubicom SX48 microcontroller with a 20 MHz turbo mode, offering 16 or 32 I/O pins respectively (plus 2 serial), 2K bytes internal EEPROM plus up to 16K external, 38 bytes of RAM (including 12 for I/O registers and 26 variables), 128 bytes of scratchpad RAM, and 61 PBASIC commands for improved execution at ~12,000 instructions per second—enabling advanced features like I/O polling and protocol support.[7][33][35] Further variants optimized for speed and power. The BS2sx, released in 2001, employed the Ubicom SX28 microcontroller at 50 MHz with 16 I/O pins (plus 2 serial), up to 16K bytes of external EEPROM across eight 2K-byte slots (~4,000 instructions), 32 bytes of RAM for 26 variables, 64 bytes of scratchpad RAM, and 45 PBASIC commands, achieving up to 2.5 times the execution speed of the BS2 at ~10,000 instructions per second.[7][33] The BS2pe, introduced in 2004 as a low-power extension of the BS2p series, utilized the Ubicom SX48 at an 8 MHz turbo speed with 16 I/O pins (plus 2 serial), up to 32K bytes of external EEPROM (16K source code capacity), 38 bytes of RAM for 26 variables, 128 bytes of scratchpad RAM, and 61 PBASIC commands, delivering ~6,000 instructions per second alongside sleep modes for battery-operated applications like data logging.[19][33][36] Similarly, the BS2px from 2004 leveraged the Ubicom SX48 at 32 MHz turbo with 16 I/O pins (plus 2 serial), 2K internal plus 16K external EEPROM, 38 bytes of RAM for 26 variables, 128 bytes of scratchpad RAM, and 63 PBASIC commands for the highest performance in the family at ~19,000 instructions per second, tailored for real-time tasks with specialized I/O configurations.[19][33] All BS2 derivatives maintain compatibility with the core PBASIC syntax for seamless code portability.[33]| Model | Processor | Oscillator Speed | I/O Pins | EEPROM (Program) | RAM (Variables) | PBASIC Commands | Execution Speed (inst/sec) |
|---|---|---|---|---|---|---|---|
| BS2 | PIC16C57 | 20 MHz | 16 + 2 | 2K (~500 inst) | 32 bytes (26) | 42 | ~4,000 |
| BS2e | PIC-based | 20 MHz | 16 + 2 | 16K external (~4,000 inst) | 32 bytes (26) | 45 | ~4,000 |
| BS2p24 | Ubicom SX48 | 20 MHz Turbo | 16 + 2 | 2K + 16K external (~4,000 inst) | 38 bytes (26) | 61 | ~12,000 |
| BS2p40 | Ubicom SX48 | 20 MHz Turbo | 32 + 2 | 2K + 16K external (~4,000 inst) | 38 bytes (26) | 61 | ~12,000 |
| BS2sx | Ubicom SX28 | 50 MHz | 16 + 2 | 4K (up to 16K external) (~4,000 inst) | 32 bytes (26) | 45 | ~10,000 |
| BS2pe | Ubicom SX48 | 8 MHz Turbo | 16 + 2 | Up to 32K external (16K source) | 38 bytes (26) | 61 | ~6,000 |
| BS2px | Ubicom SX48 | 32 MHz Turbo | 16 + 2 | 2K + 16K external (~4,000 inst) | 38 bytes (26) | 63 | ~19,000 |