IEEE 1284
IEEE 1284 is a technical standard developed by the Institute of Electrical and Electronics Engineers (IEEE) that defines a signaling method for asynchronous, fully interlocked, bidirectional parallel communications between host computers and peripherals, such as printers.[1] It builds upon the original Centronics parallel port interface to enable higher-speed data transfer in both directions while ensuring backward compatibility with existing hardware.[2] Originally published in 1994 as IEEE Std 1284-1994, the standard was revised in 2000 as IEEE Std 1284-2000 to incorporate enhancements like improved electrical interfaces and cabling for better performance over longer distances, up to 32 feet, with data rates exceeding 1 MB/s.[1][2] The 2000 revision was reaffirmed in 2011 but later withdrawn in 2016 and inactivated in 2022, reflecting its obsolescence in modern computing environments dominated by USB and other interfaces, though it remains relevant for legacy systems.[3] Key features include support for two interface levels—Level I (open-drain for basic compatibility) and Level II (totem-pole drivers for high-speed operation)—along with standardized connectors (Types A, B, and C) and cabling specifications to minimize signal degradation.[2][4] The standard supports five primary modes of operation to accommodate various communication needs: Compatibility Mode (also known as Centronics or Standard Parallel Port, SPP), which provides unidirectional, byte-wide forward data transfer at 50-150 kB/s; Nibble Mode, enabling reverse data transfer in 4-bit increments for basic bidirectional functionality; Byte Mode, allowing reverse byte-wide transfers; Enhanced Parallel Port (EPP) Mode, a high-speed bidirectional protocol optimized for real-time peripherals like storage devices; and Extended Capabilities Port (ECP) Mode, designed for high-performance applications such as printers and scanners with features like run-length encoding and FIFO buffering.[2][5] These modes allow negotiation between the host and peripheral to select the most suitable protocol, including a device ID string for identification during initialization.[1] Overall, IEEE 1284 significantly advanced parallel port capabilities in the 1990s, facilitating reliable peripheral connectivity before the widespread adoption of serial interfaces.[4]History and Development
Origins and Standardization
The development of IEEE 1284 was initiated in 1991 through the formation of the Network Printing Alliance (NPA), a consortium aimed at standardizing bidirectional parallel communication for computer peripherals, particularly printers, to address the limitations of proprietary interfaces.[6] The NPA sought to create a universal standard that would enable reliable, high-performance data exchange between hosts and devices, moving beyond the unidirectional constraints of earlier systems. This effort was sponsored under the IEEE Standards Board, reflecting a collaborative push by industry stakeholders to unify parallel port technologies for broader interoperability.[7] Key contributors to the standard included major printer manufacturers such as Seiko Epson Corporation, Lexmark International, IBM, and Texas Instruments, who recognized the need for a cohesive framework amid fragmented implementations.[8] The legacy of the Centronics parallel interface, originally developed in the 1970s for printer connections, heavily influenced the project, as its widespread adoption had created a de facto but inconsistent standard that hindered advanced features like bidirectionality.[9] These companies, along with other NPA members, provided technical expertise and testing to ensure the standard addressed real-world deployment challenges in printing and peripheral ecosystems. IEEE 1284 was formally ratified by the IEEE Standards Board on March 30, 1994, and approved as an ANSI standard later that year, marking its official adoption as the "Standard Signaling Method for a Bidirectional Parallel Peripheral Interface for Personal Computers."[7] The working group's primary goals centered on enabling high-speed, bidirectional data transfer rates up to 2 MB/s while maintaining full compatibility with existing Centronics parallel ports. This included mechanisms for device negotiation to support advanced operational features, ensuring seamless integration without requiring hardware overhauls.Evolution and Revisions
Following the initial IEEE 1284-1994 standard, which established the baseline for bidirectional parallel communications, the IEEE introduced IEEE Std 1284.1-1997 to address compatibility challenges across manufacturers. This supplementary standard defines a transport-independent printer/system interface (TIP/SI), providing protocols and methodologies for software developers, computer vendors, and printer manufacturers to ensure orderly information exchange and standardized testing procedures between hosts and peripherals. By focusing on a minimum set of compatible functions, it facilitated broader adoption while allowing for innovation in implementations.[10] In 2000, the core standard was revised and published as IEEE Std 1284-2000, superseding the 1994 version with refinements to operational modes, including enhancements to the Enhanced Capabilities Port (ECP) protocol. These updates improved efficiency in bidirectional data transfer and better supported integration with operating systems like Windows through optimized plug-and-play features and reduced overhead in peripheral negotiation. The revision maintained backward compatibility with existing hardware while extending support for higher-speed communications up to several megabytes per second in advanced modes.[3][11] Subsequent maintenance included the administrative withdrawal in February 2006 of related extensions IEEE 1284.3-2000 (for superimposed bidirectional transmission) and IEEE 1284.4-2000 (for a data link layer protocol), which had aimed to mitigate signal integrity issues and support longer cable lengths in multi-device setups. These withdrawals reflected evolving priorities, as no formal errata sheets were issued for the main standard addressing cable limitations explicitly, though the 2000 revision reaffirmed specifications for up to 10 meters in compliant cabling.[3] Active development of IEEE 1284 ceased around 2010, driven by the widespread adoption of USB as the preferred interface for peripherals due to its hot-pluggable nature, power delivery, and higher speeds. The standard received its final reaffirmation in 2011, followed by ANSI withdrawal in 2016 and inactivation as reserved in 2022, marking the end of ongoing revisions.[3][12]Technical Overview
Key Characteristics
IEEE 1284 establishes a parallel interface employing an 8-bit data bus complemented by dedicated control lines for handshaking, including the STROBE signal to initiate data transfer and the ACKNOWLEDGE signal to confirm receipt by the peripheral.[11] This architecture enables efficient synchronization between the host and device, ensuring orderly data exchange over the parallel connection.[13] The standard facilitates bidirectional communication, supporting transfer rates starting at 150 KB/s in compatibility mode and extending to 2 MB/s in advanced configurations such as Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP) modes.[13] Auto-negotiation occurs through a dedicated IEEE 1284 sequence, where the host queries the peripheral's capabilities to select the highest compatible mode, optimizing performance without manual configuration.[11] Electrically, the interface adheres to TTL-compatible signaling with logic levels ranging from 0 to 5 V, providing robust compatibility with legacy systems while maintaining signal reliability.[14] To preserve integrity, the maximum cable length is specified at 10 meters for standard IEEE 1284-compliant cables, beyond which signal attenuation may degrade performance.[13]Operational Modes
IEEE 1284 defines five primary operational modes to support varying levels of data transfer directionality, speed, and functionality between a host and peripheral device, ensuring backward compatibility while enabling enhanced bidirectional communication. These modes are negotiated at connection time to select the optimal protocol based on device capabilities, with each mode utilizing specific handshaking signals over the parallel interface's control and status lines. The standard prioritizes interoperability, requiring all compliant devices to support at least the basic forward and reverse channels. Compatibility Mode provides unidirectional output from the host to the peripheral, emulating the traditional Centronics parallel port protocol for legacy printer compatibility. It transfers data at approximately 150 KB/s using basic STROBE handshaking, where the host asserts the STROBE signal to latch 8-bit data bytes into the peripheral. This mode relies on asynchronous, byte-wide forward transfers without reverse channel support in its base form, making it suitable for simple output-only applications.[11][2] Nibble Mode enables bidirectional communication by allowing reverse data transfer from the peripheral to the host in 4-bit increments over the interface's status lines (such as ACK, BUSY, PE, and FAULT). Operating at about 75 KB/s, it serves primarily for status reporting or limited input, such as printer error codes or device identification, and is mandatory for all IEEE 1284-compliant peripherals when paired with Compatibility Mode for forward transfers. The peripheral encodes two nibbles to form a full byte, using handshaking signals like nACK to synchronize with the host.[11][2] Byte Mode extends reverse communication to full 8-bit bidirectional transfers at up to 150 KB/s, utilizing the data lines in both directions after switching control from the host. It requires host adapter support for line direction changes via signals like nSelectIn and AUTOFD, making it ideal for peripherals needing higher reverse throughput, such as scanners returning image data. Unlike Nibble Mode, it avoids status line limitations but still operates asynchronously with STROBE-based handshaking.[11][2] EPP (Enhanced Parallel Port) Mode facilitates high-speed bidirectional transfers up to 2 MB/s by providing direct address and data access akin to a microprocessor bus interface, supporting real-time peripherals like network adapters or storage devices. It incorporates automatic address and data strobing, interrupt capabilities, and DMA support for efficient CPU-peripheral interaction without software polling, achieving speeds ten times faster than basic modes through interlocking handshaking. This mode is particularly valuable for applications requiring low-latency, register-based operations.[11][2] ECP (Extended Capabilities Port) Mode offers advanced bidirectional performance up to 2 MB/s, optimized for printers and scanners with features like run-length encoding (RLE) compression to reduce data volume and FIFO buffering (typically 16 bytes or more) for burst transfers. It employs hardware handshaking, DMA channels, and interrupt-driven operation to minimize host overhead, enabling efficient handling of large datasets in both directions while supporting channel addressing for multiplexed devices. ECP's compression and buffering distinguish it for bandwidth-intensive tasks.[11][2] The negotiation process allows the host and peripheral to agree on a mode at initialization, ensuring compatibility. The process begins in Compatibility Mode, where the host signals intent to negotiate by setting the data lines first to 0x55 (01010101 binary) and then to 0xAA (10101010 binary) while asserting nSelectIn high and nAutoFd low; the peripheral confirms compliance via status line responses such as toggling nAck. Once negotiation is entered, the host places an 8-bit Extensibility byte on the data lines—such as 0x00 for Nibble Mode or 0x01 for Byte Mode—then pulses nSTROBE to signal the request. The peripheral responds via status lines (e.g., nACK low to acknowledge compliance, with bit patterns indicating supported modes like EPP via 0x40 or ECP via 0x10/0x30), and the host confirms by deasserting signals; if needed, an Extensibility Link request (0x80) extends the phase for additional mode bytes. This handshake, completed within milliseconds, defaults to Compatibility Mode if negotiation fails.[11]Physical Implementation
Connectors
IEEE 1284 specifies three distinct connector types to facilitate connections between hosts and peripherals, ensuring compatibility with both legacy and enhanced bidirectional parallel interfaces. These connectors are designed with precise physical dimensions and pin assignments to support data transfer, control signals, and grounding while accommodating varying device form factors. The standard prioritizes reliable electrical performance through defined shielding and impedance requirements for attached cables. The IEEE 1284-A connector is a 25-pin D-subminiature (DB-25) interface primarily used on the host side, such as personal computers. It features a trapezoidal shell with two rows of pins, where pins 2 through 9 are assigned to the 8-bit data lines, pins 1, 14, 16, and 17 handle key control signals like nStrobe (pin 1), nAutoFd (pin 14), nInit (pin 16), and nSelectIn (pin 17), and pins 18 through 25 serve as ground connections for signal integrity. This connector maintains backward compatibility with earlier parallel port standards but lacks pins for some advanced signals like Host Logic High (HLH).[2] In contrast, the IEEE 1284-B connector is a 36-pin Champ-style interface, also known as the Centronics connector, intended exclusively for the peripheral side, such as printers. It employs a 0.085-inch centerline spacing with bail locks for secure attachment and an extended pinout that supports bidirectional operation. Data lines occupy pins 2-9, control signals include nStrobe on pin 1 and nAckReverse on pin 10, while grounds are distributed across pins 19-30 and 32-35; additionally, pin 18 provides an optional +5V power supply for peripheral logic, though not all implementations include it.[2][15] For compact devices requiring smaller footprints, IEEE 1284 introduces the Type C connector, a 36-pin high-density (MDR36) interface with 0.050-inch centerline spacing and clip latches, suitable for both host and peripheral applications to enable full signal support including peripheral logic high (PLH) on pin 36 and host logic high (HLH) on pin 18. Data lines occupy pins 6-13, key control signals include nStrobe on pin 15, nInit on pin 14, nSelectIn on pin 16, and nAutoFd on pin 17, while grounds are on pins 19-35. This type promotes space-efficient designs without compromising electrical specifications.[2][4][16]| Connector Type | Pin Count | Primary Usage | Key Physical Features | Example Pin Assignments |
|---|---|---|---|---|
| IEEE 1284-A (DB-25) | 25 | Host | D-subminiature shell, 2 rows | Data: 2-9; Control: 1 (nStrobe), 14 (nAutoFd), 16 (nInit), 17 (nSelectIn); Ground: 18-25 |
| IEEE 1284-B (Centronics) | 36 | Peripheral | 0.085" centerline, bail locks | Data: 2-9; Control: 1 (nStrobe), 10 (nAckReverse); Ground: 19-30, 32-35; Power: 18 (+5V optional) |
| IEEE 1284-C (MDR36) | 36 | Host/Peripheral | 0.050" centerline, clip latches | Data: 6-13; Control: 15 (nStrobe), 14 (nInit), 16 (nSelectIn), 17 (nAutoFd), 18 (HLH), 36 (PLH); Ground: 19-35 |