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R3000

The R3000 is a 32-bit reduced instruction set computing (RISC) microprocessor chipset developed by MIPS Computer Systems and released in 1988 as an evolution of the earlier R2000 design.^[1] It implements the MIPS I instruction set architecture (ISA), featuring a compact set of instructions optimized for high performance through a five-stage pipeline that enables near one-instruction-per-cycle execution.^[3] Key technical specifications of the R3000 include approximately 110,000 to 125,000 transistors fabricated on a 1.2-micrometer process, with initial clock speeds of 20 MHz and power dissipation around 4 watts; later variants like the R3000A supported up to 40 MHz with cache controllers for external caches, such as 64 KB configurations.^[1]^[3] The architecture employs a Harvard design with separate 32-bit instruction and data buses, an on-chip memory management unit (MMU) featuring a 64-entry fully associative translation lookaside buffer (TLB) for handling up to 4 GB of virtual address space, and support for up to three coprocessors, including one for floating-point operations.^[3] Performance metrics for the family reached sustained throughputs of 20 to 35 million instructions per second (MIPS), depending on the model and clock rate, making it suitable for multitasking environments like UNIX System V and BSD 4.3.^[3] The R3000 gained prominence for its role in high-end computing, powering UNIX workstations from manufacturers such as Silicon Graphics (e.g., the Personal IRIS 4D/20 series used in 3D rendering for films like Jurassic Park) and Digital Equipment Corporation, as well as embedded applications in multiprocessing systems.^[4] Over one million units were produced, marking it as one of the first commercially successful RISC processors and influencing subsequent MIPS designs.^[4] In the late 1990s, it evolved into embedded variants like the MIPS32 4Kc core, which utilized a 0.25-micrometer process for 200 MHz operation at low power (around 2 mW/MHz), targeting battery-operated devices with up to 600 MIPS per watt efficiency.^[1]

History and development

Background and design origins

The MIPS R3000 microprocessor emerged from the broader evolution of reduced instruction set computing (RISC) research at Stanford University, where the foundational MIPS project began in the early 1980s under the leadership of Professor John L. Hennessy.^[5] This academic initiative, known as Stanford MIPS, aimed to develop a high-performance microprocessor leveraging RISC principles to simplify instruction execution and improve efficiency through techniques like pipelining.^[5] Hennessy's work built on his expertise in compilers and architecture, influencing the design of processors that prioritized a streamlined instruction set over the complexity of contemporary complex instruction set computing (CISC) systems.^[5] The precursor to the R3000 was the R2000, introduced by MIPS Computer Systems in 1985 as the first commercial implementation of the MIPS I instruction set architecture (ISA).^[6] The R2000, while innovative, was constrained by its high manufacturing costs—driven in part by the need for multiple chips in a chipset configuration—and the requirement for an external floating-point unit (FPU), such as the R2010 coprocessor, which increased system complexity and expense.^[7] These factors limited the R2000 primarily to academic research environments and niche high-end workstation applications, where its performance in integer operations was valued but broader adoption was hindered by the overall system price, often exceeding $12,000 for basic configurations.^[8] To address these shortcomings, the R3000's design origins centered on creating a more fully integrated 32-bit RISC chipset capable of competing directly with CISC processors like the Intel 80386, which dominated the emerging personal computer and workstation markets in the late 1980s.^[9] Key goals included enhancing simplicity in the instruction set to enable faster execution cycles, boosting overall speed through better pipelining and cache management, and ensuring scalability for professional workstation use cases such as computer-aided design and scientific computing.^[6] MIPS founders, including Hennessy alongside John Moussouris and Edward “Skip” Stritter, drew directly from the Stanford project's emphasis on RISC fundamentals to prioritize these objectives, aiming to reduce the chip count and integration barriers that plagued the R2000.^[6] Early design challenges for the R3000 revolved around balancing die size with performance, leading to decisions like retaining coprocessor interfaces for optional FPUs while incorporating support for external caches to avoid bloating the core processor chip.^[7] This approach allowed for modular scalability—enabling manufacturers to add specialized components without redesigning the central CPU—while keeping the base architecture compact and cost-effective relative to its predecessor.^[7] The resulting design maintained compatibility with the MIPS I ISA, providing a seamless upgrade path from the R2000.^[6]

Release and production

The MIPS R3000 microprocessor was officially introduced in June 1988 by MIPS Computer Systems, marking the company's second-generation RISC processor following the R2000.^[1] Operating under a fabless model, MIPS outsourced fabrication to partners such as Integrated Device Technology (IDT), which produced the 79R3000 variant, LSI Logic, and NEC, enabling scalable manufacturing without in-house foundries.^[10] By the early 1990s, production exceeded 1 million units, reflecting strong market uptake in professional computing applications.^[11] The chip was targeted at original equipment manufacturers (OEMs) for integration into workstations and embedded systems, with initial volume pricing positioned to support high-performance Unix-based platforms. Production ramped up to mass scale in 1989, facilitating widespread adoption by key customers including Silicon Graphics (SGI) for its IRIS 4D workstation series and later Sony for consumer electronics.^[12]

Architecture

Instruction set and pipeline

The R3000 implements the MIPS I instruction set architecture (ISA), a 32-bit reduced instruction set computing (RISC) design characterized by a load/store architecture, fixed-length 32-bit instructions, and a three-operand format for most operations. This ISA emphasizes simplicity and efficiency, supporting 32 general-purpose registers (denoted $0 to $31, with $0 hardwired to zero) and restricting memory access to dedicated load (e.g., LW) and store (e.g., SW) instructions. Key instruction categories include arithmetic operations such as ADD, ADDU, SUB, and ADDI for integer addition and subtraction; logical operations like AND, OR, NOR, and shifts (e.g., SLL); and conditional branches such as BEQ and BNE for equality and inequality tests. The base ISA comprises about 55 instructions, excluding coprocessor-specific extensions.^[13]^[14] Instructions are encoded in three primary formats to accommodate different operand types. The R-type format handles register-to-register operations, featuring a 6-bit opcode, 5-bit fields for source registers rs and rt, a 5-bit destination register rd, a 5-bit shift amount, and a 6-bit function code to specify the operation (e.g., ADD uses opcode 0 and function 100000). The I-type format supports immediate operands and is used for loads, stores, arithmetic with constants (e.g., ADDI), and PC-relative branches (e.g., BEQ with a 16-bit signed offset), consisting of a 6-bit opcode, 5-bit rs and rt fields, and a 16-bit immediate value. The J-type format is reserved for unconditional jumps like J and JAL, with a 6-bit opcode followed by a 26-bit target address shifted left by two bits and concatenated with the upper 4 bits of the PC. These formats enable compact encoding while facilitating pipelined execution.^[13]^[14] The R3000 employs a classic five-stage pipeline to achieve high throughput: Instruction Fetch (IF), where the next instruction is retrieved from memory; Instruction Decode and Register Fetch (ID), involving opcode decoding and operand reading; Execute (EX), performing ALU operations or address calculations; Memory Access (MEM), handling loads and stores; and Writeback (WB), updating the register file. To mitigate control hazards from branches and jumps, the architecture incorporates a single branch delay slot: the instruction immediately following a branch or jump is unconditionally executed, regardless of the branch outcome, allowing compilers to fill this slot with useful code to avoid stalls. Load instructions also feature a one-cycle delay before the data is available, further influencing software scheduling.^[13]^[14] Exception handling in the MIPS I ISA ensures precise interruptions, where the processor state remains consistent as if all prior instructions completed and subsequent ones did not begin. Upon an exception (e.g., arithmetic overflow or syscall), the Exception Program Counter (EPC) register stores the virtual address of the faulting instruction, enabling precise restart; if the exception occurs in a branch delay slot, a BD bit in the Cause register is set, and the EPC points to the branch instruction itself. This mechanism supports reliable recovery without speculative execution complexities.^[13]

Microarchitecture and coprocessors

The MIPS R3000 employs a Harvard architecture, featuring separate instruction and data buses to enable simultaneous access to program instructions and data, which enhances throughput in systems without integrated caches.^[15] The core design lacks on-chip caches, instead relying on external cache implementations provided by the system designer to manage instruction and data storage, allowing flexibility in cache size and configuration while maintaining a streamlined 32-bit RISC pipeline.^[15] At the heart of the R3000 is a register file consisting of 32 general-purpose 32-bit registers (GPRs), labeled $0 through $31, which serve as the primary storage for operands during instruction execution.^[15] Register $0 is hardwired to always return zero, facilitating efficient arithmetic operations, while $31 is conventionally used for link addresses in procedure calls.^[15] Additionally, the architecture includes two special 32-bit registers, HI and LO, dedicated to holding the upper and lower 32 bits of 64-bit results from multiply and divide instructions, enabling seamless handling of extended precision computations without additional data movement.^[15] The R3000 supports up to four coprocessors, designated CP0 through CP3, integrated via a dedicated coprocessor interface that allows parallel execution of specialized operations alongside the main integer pipeline.^[15] CP0 functions as the mandatory system control coprocessor, managing essential hardware functions such as exception handling, interrupt processing, and virtual memory operations through its internal registers.^[15] CP1 is reserved for the floating-point unit (FPU), while CP2 and CP3 are available for user-defined extensions, such as custom accelerators in embedded applications.^[15] Access to these coprocessors occurs through dedicated MIPS I instructions, such as MFC (move from coprocessor) and MTC (move to coprocessor), which transfer data between the GPRs and coprocessor registers.^[15] The R3010 serves as the dedicated FPU coprocessor (CP1) for the R3000, providing a tightly coupled 64-bit floating-point capability compliant with the IEEE 754 standard for single- and double-precision arithmetic.^[16] It includes eight 64-bit floating-point registers (FPRs), configurable as 16 32-bit registers, and supports core operations such as ADD.D (double-precision addition) and MUL.D (double-precision multiplication), along with conversion, comparison, load, store, and move instructions.^[16] The R3010 integrates via the R3000's coprocessor bus, monitoring for floating-point opcodes and executing them independently in a 6-stage pipeline with three concurrent units for addition/subtraction, multiplication, and division, while the main CPU processes non-floating-point instructions.^[16] Control and status transfers between the R3000 and R3010 utilize instructions like CFC1 (coprocessor from control register 1) and CTC1 (coprocessor to control register 1), enabling software to configure rounding modes and handle exceptions efficiently.^[16]

Memory subsystem

The MIPS R3000 employs a 32-bit virtual addressing scheme, providing a total address space of 4 GB. This space is partitioned into distinct segments to facilitate efficient memory access in both user and kernel modes. The user segment (Useg or kuseg), spanning 0x00000000 to 0x7FFFFFFF (2 GB), is intended for user-level processes and requires translation through the memory management unit (MMU) for access. In kernel mode, the address space includes Kseg0 (0x80000000 to 0x9FFFFFFF, 512 MB), which maps directly to the lower 512 MB of physical memory with caching enabled; Kseg1 (0xA0000000 to 0xBFFFFFFF, 512 MB), which similarly maps to physical memory but bypasses caching for uncached operations such as I/O; and Kseg2 (0xC0000000 to 0xFFFFFFFF, 1 GB), which is mapped and cacheable via the MMU.^[17]^[3] The MMU is integrated into the Coprocessor 0 (CP0) and handles virtual-to-physical address translation primarily for the Useg and Kseg2 segments. It features a 64-entry fully associative translation lookaside buffer (TLB) that supports page sizes of 4 KB, enabling efficient mapping of virtual pages to physical frames. Each TLB entry includes fields for the virtual page number, physical frame number, address space identifier (ASID) for process isolation, and control bits for caching, validity, and dirtiness. TLB operations, such as probing, reading, and writing entries, are performed via dedicated CP0 instructions, with software responsible for handling misses through exception routines. The fully associative design allows flexible replacement policies, including random or indexed writes, to manage the limited 64 entries across multiple processes.^[17]^[3] To minimize die area and cost, the R3000 incorporates no on-chip primary caches, instead providing an external cache interface for separate instruction and data caches, each configurable up to 256 KB. The interface supports direct-mapped caches with write-through policy for data and burst refill capabilities, allowing efficient loading of cache lines from main memory. Kseg0 accesses utilize these caches, while Kseg1 accesses proceed uncached directly to memory or peripherals. The on-chip cache controller ensures transparent operation to software. The memory bus protocol utilizes a 32-bit address bus and a 32-bit data bus, enabling full 32-bit transfers in a multiplexed fashion. It supports burst mode transfers specifically for cache line fills, permitting sequential reads of multiple words (typically 4 or more) in a single transaction to reduce latency during misses. This protocol facilitates high-bandwidth access to external memory while maintaining compatibility with the R3000's pipeline, including stall mechanisms for bus arbitration in multiprocessor configurations.^[3]

Technical specifications

Clock speeds and performance

The original R3000 microprocessor operated at clock frequencies ranging from 16.7 MHz to 33.33 MHz.^[3] In workstation configurations such as the DECstation 5000 Model 200, a 25 MHz R3000 delivered a SPECmark89 rating of 18.5, establishing it as a competitive performer in early 1990s UNIX environments.^[18] The processor achieved sustained throughput approaching 1 instruction per cycle (IPC) in steady-state execution, yielding up to 28 MIPS at 33 MHz, though real-world performance was moderated by branch delays and load-use hazards in its 5-stage pipeline.^[3] Launch configurations typically rated 20-30 MIPS at 20-25 MHz speeds. Power consumption for the R3000 was low for its era, approximately 3.8 W at 25 MHz based on maximum supply current draws of around 750 mA at 5 V.^[3] In integer workloads, the R3000 outperformed the Intel 80386, with results further enhanced by external cache configurations.^[19]

Physical and fabrication details

The MIPS R3000 CPU core was fabricated containing approximately 115,000 transistors.^[1] The processor utilized a 1.2 μm CMOS process technology.^[1] The R3000 was packaged in a 144-pin PGA or 172-pin ceramic flatpack, with the pinout providing dedicated interfaces for the 32-bit address bus, 32-bit data bus, and up to three coprocessor connections including the system control coprocessor (CP0).^[3] The core R3000 chipset comprised the R3000 as the primary CPU, the R3010 as the floating-point coprocessor (FPU), and the R3020 as a memory buffer coprocessor supporting external secondary cache interfaces.^[3]^[20]

Variants and derivatives

R3000A and performance variants

The R3000A, introduced by Integrated Device Technology (IDT) in 1991, represents an enhanced iteration of the base R3000 microprocessor, incorporating a 32-bit MIPS RISC core compatible with the MIPS I instruction set architecture. It supports clock frequencies from 16.67 MHz to 33.33 MHz, with certain configurations reaching up to 40 MHz, delivering sustained performance of up to 28 MIPS. The design includes an on-chip cache controller for external Harvard-architecture caches, typically configured at 64 KB each for instructions and data in high-performance setups, enabling single-cycle access and multiword block refills. It interfaces directly with the external R3010 floating-point unit (FPU) for full IEEE 754-1985 compliance, supporting 64-bit double-precision operations.^[3]^[1] Performance variants of the R3000A, such as the R3051 and R3052, integrate small on-chip caches to further boost efficiency, with the R3051 featuring a 4 KB instruction cache and 2 KB data cache, while the R3052 doubles the instruction cache to 8 KB. These additions, combined with 4-deep write and read buffers, minimize pipeline stalls and achieve up to 35 MIPS at 40 MHz. Key enhancements over the base R3000 include relaxed memory timing in the "E" revision for easier system integration, improved multiprocessing capabilities via internal address latches on cache RAMs, and optional features like parity checking and byte-order flexibility. The architecture maintains the 5-stage pipeline of the original while optimizing for reduced external component count in workstation environments.^[3] The PR3400, manufactured by Performance Semiconductor starting in 1991, serves as a high-performance single-chip variant that combines the PR3000A CPU core—derived from the R3000A—with the PR3010A FPU on one die, operating at up to 40 MHz. This integration streamlines floating-point processing by minimizing inter-chip communication latency and enhancing overall pipeline efficiency, resulting in superior throughput for compute-intensive tasks. Targeted at high-end workstations, the PR3400 underpins systems like the DECstation 5000 Model 240, where it delivers 42.9 MIPS integer performance and 10.8 MFLOPS, nearly doubling prior models' capabilities through higher clock rates and ASIC optimizations.^[21]^[22]

Embedded and specialized versions

The R3000 architecture was adapted into several embedded variants optimized for low-power, high-integration applications in consumer electronics, control systems, and cost-sensitive designs, featuring reduced pin counts, on-chip caches, and integrated peripherals while maintaining compatibility with the MIPS I instruction set.^[23] These derivatives prioritized compact form factors and efficiency over raw performance, enabling deployment in ASICs and system-on-chip solutions.^[3] IDT's RISController family, introduced in the early 1990s, comprised embedded microprocessors like the 79R3081 that integrated the R3000A-compatible core with a floating-point accelerator (FPA), 16 KB instruction cache, and 4 KB data cache, and memory management unit on a single chip to minimize system cost and board space in control applications.^[24] The series supported instruction set compatibility with the R3000 family, allowing software portability while adding peripherals such as DMA controllers and serial interfaces for real-time embedded tasks.^[3] Toshiba's CW4003, developed in the 1990s for digital imaging, was a compact R3000 derivative core embedded in LSI Logic's DCAM-101 system-on-chip, with a multiplier-arithmetic bolt-on unit for enhanced pixel processing in cameras. It included a coprocessor 2 interface for JPEG compression/decompression and CCD interfacing.^[25] The Toshiba TX3900 series extended the R3000 into microcontroller territory with scaled-down implementations, such as the TMPR3904F, featuring 32-bit R3000 cores, configurable caches, and integrated peripherals like timers and I/O ports for automotive and consumer embedded systems at 3.3V operation.^[26] These variants emphasized low pin counts and direct memory access support to suit ASIC integration in cost-sensitive environments.^[27] Philips Semiconductors' PR31500, a 1990s single-chip solution, incorporated an R3000 core at 37-40 MHz with 4 KB instruction and 1 KB data caches, plus a multiply-accumulator for DSP tasks, multi-channel DMA, UARTs, and memory controllers for ROM/Flash/RAM interfacing in embedded communications devices like modems.^[23] Operating at 3.3V in a 208-pin LQFP package, it supported big/little-endian modes and an R3000A-compatible TLB for efficient real-time processing.^[23] Performance Semiconductor's PR3000 family provided low-power R3000-compatible CPUs, such as the PR3000A at 25-33 MHz, with reduced pinouts (e.g., 160-pin surface-mount) and integrated cache controllers to lower board costs in embedded control systems, achieving 4.1-5.4 MFLOPS on Linpack benchmarks.^[28] For specialized radiation-hardened applications in space and defense, Synova's Mongoose-V was a 10-15 MHz R3000 implementation with integrated R3010 FPU, on-chip caches, and SOI technology for single-event upset tolerance up to 1E-10 errors/day, deployed in NASA's New Horizons mission for onboard computing.^[29] Similarly, the RH-3000 chipset, developed under U.S. Naval Research Laboratory sponsorship, offered a rad-hard R3000-compatible CPU with concurrent error detection, FPA, and support chips tolerant to 100 krad total dose for small satellite payloads and avionics. These variants used larger feature sizes and hardened fabrication to ensure reliability in harsh radiation environments without sacrificing MIPS I compatibility.

Applications and legacy

Use in workstations and servers

The MIPS R3000 microprocessor was prominently adopted by Silicon Graphics (SGI) in its IRIS series workstations, such as the IRIS Indigo introduced in 1991, where it operated at 33 MHz to handle general-purpose processing and support graphics rendering tasks.^[30]^[31] This integration allowed the R3000, paired with the R3010 floating-point unit, to offload certain graphics operations like pixel filling and line drawing via the Raster Engine (REX) ASIC, enabling cost-effective 24-bit color graphics with features such as texture mapping and fogging in IRIX, SGI's Unix variant.^[30] The Indigo targeted mainstream professional users with multitasking, virtual memory, and network capabilities, positioning it as an accessible entry into high-performance computing for design and visualization.^[30] Sony incorporated the R3000 into its NEWS workstation line starting with the NWS-3860 model in 1989 and the NEWS 3710 in 1990, using a 20 MHz variant with floating-point acceleration for engineering and computer-aided design (CAD) applications.^[32]^[33] These systems featured 8 MB of RAM, X Window System support with extensions for shapes and Bezier curves, and expandability via SCSI and Ethernet, making them suitable for technical workflows requiring fast graphics and reliable Unix-based operation.^[33] The R3000's RISC design contributed to efficient performance in these environments, supporting up to 1280x1024 resolution displays and stereo audio for professional visualization tasks.^[33] In server applications, the R3000 powered early Unix systems, including NEC's UP4800/520 introduced in April 1991, a 33 MHz R3000-based machine with 33 MIPS performance and R3010 FPU, designed for database processing, online transactions, and multi-user environments supporting up to 110 lines.^[34] This server offered 64-320 MB of main memory, ECC protection, and dual-CPU configurations for high reliability in core network roles under Unix.^[34] Other early MIPS-based servers, such as those from MIPS Computer Systems like the R3000-equipped Magnum series running RISC/os (a BSD Unix variant), provided scalable Unix computing for enterprise use. These implementations highlighted the R3000's versatility in professional server setups. The R3000's deployment in these workstations and servers facilitated the growth of RISC-based Unix systems, enabling MIPS architectures from vendors like SGI to compete effectively with Sun Microsystems' SPARC and Hewlett-Packard's PA-RISC platforms in the late 1980s and 1990s professional computing market.^[35]^[11] By offering competitive performance in graphics-intensive and multi-user scenarios at relatively accessible price points, it helped establish MIPS as a key player in the Unix workstation segment, which saw intense rivalry among RISC designs during this era.^[35]

Adoption in embedded and consumer systems

The R3000 found significant adoption in consumer electronics, most notably as the central processor in the original Sony PlayStation console released in 1994. This system utilized a customized R3000A variant clocked at 33.8688 MHz, enabling 3D graphics rendering and gameplay for a wide range of titles, which contributed to the console's commercial success with over 102 million units sold worldwide.^[36]^[37] The integration demonstrated the R3000's suitability for cost-sensitive, high-volume production in gaming hardware, where its MIPS I instruction set supported efficient real-time processing without requiring an external floating-point unit for basic operations. In defense and aerospace applications, the R3000 became a cornerstone for real-time systems under the Joint Integrated Avionics Working Group (JIAWG) standards, which selected its architecture for modular avionics computing in military aircraft. This choice was driven by the processor's reliable 32-bit RISC design, capable of handling fault-tolerant operations in harsh environments, as implemented in systems like the F-16's modular mission computer. A prominent example is the NASA New Horizons spacecraft, launched in 2006, which employed the radiation-hardened Mongoose-V variant—a direct derivative of the R3000 operating at 12 MHz—for command and data handling, guidance, and control tasks during its mission to Pluto. The Mongoose-V incorporated the R3000 core alongside an R3010 floating-point unit, on-chip caches, and error-correcting memory interfaces to ensure robustness in space.^[38]^[39] Beyond these high-profile uses, the R3000 powered various embedded systems in avionics, networking, and printing. In avionics, it served as the basis for 32-bit processors delivering up to 20 MIPS in distributed military architectures, supporting real-time data processing for flight controls and sensors. Networking equipment, such as early routers, leveraged R3000-based designs for packet routing and protocol handling, exemplified by single-chip implementations that integrated the CPU with ATM interfaces for efficient data flow at 20-25 MIPS. In consumer printing, variants like the R3041 targeted low-end laser printers, providing 14 MIPS at 20 MHz for raster image processing and print engine control in high-volume devices. The R3000's versatility in these domains extended the longevity of the MIPS ISA in embedded markets well into the 2000s, influencing subsequent derivatives and sustaining its presence in real-time and volume-driven applications despite competition from ARM architectures.^[40]

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May 16, 2023 · There were Sun workstations (SPARC), Silicon Graphics (MIPS) ... We can compare the sales volumes in the Unix workstation market in 1990 ...
[36]
Five most iconic devices to use MIPS CPUs - WAVE Computing
Five most iconic devices to use MIPS CPUs · SGI Indigo (MIPS R3000) · Sony PlayStation (MIPS R3000 CPU) · Nintendo 64 (MIPS R4300i CPU) · NEC Cenju-4 (MIPS R10000 ...Missing: fabricated | Show results with:fabricated
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Platform Totals - VGChartz
For current platforms, all figures are current sales as measured by VGChartz ... PlayStation (PS). 40.78. 31.09. 21.59. 9.04. 102.49. 7, Nintendo Wii (Wii). 45.51 ...
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[PDF] Advanced Integrated Aircraft Survivability Equipment ... - DTIC
The MIPSCO R3000 processor is used in multiple military configurations, including on a. SEM-E module in the F- 16 MMC. It is acknowledged as one of the ...
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MIPS steers spacecraft to Pluto - Electronics Weekly
Jan 15, 2015 · Both are duplicated to increase reliability. MIPS Mongoose V NASA New Horizons Introduced in the late 1980s, R3000 is a 32bit RISC machine ...
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First-Hand:Commercialization of Embedded RISC Cores
Jan 12, 2015 · My strategy to create new markets with MIPS and V850 RISC architectures was quite successful and significantly increased NEC's microcontroller business.