Slot 2
Slot 2 is a CPU socket specification developed by Intel for high-end server and workstation processors, introduced in 1998 as the counterpart to the consumer-focused Slot 1.[1] It utilizes a 330-pin Single Edge Contact (SEC) cartridge interface, known as the SC330 connector, which accommodates larger processor cartridges with integrated L2 cache modules ranging from 512 KB to 2 MB running at full core speed.[2] Designed for multi-processor configurations, Slot 2 supports up to four CPUs in scalable systems, a 100 MHz front-side bus (FSB), and AGTL+ signaling for improved electrical performance in enterprise environments.[3] The Slot 2 interface debuted with the Pentium II Xeon processors in June 1998, available at clock speeds of 400 MHz and 450 MHz, targeting mid-range to high-end servers and workstations.[2] These processors featured the Deschutes core, Dual Independent Bus architecture for separate data and address buses, and advanced power management including thermal sensors via SMBus for system monitoring.[2] Priced significantly higher than desktop equivalents—ranging from $2,000 to over $3,000 per unit—Slot 2 modules emphasized reliability and scalability, supporting up to 64 GB of memory and binary compatibility with prior Intel x86 architectures.[1] Intel extended Slot 2 support to the Pentium III Xeon family starting in March 1999, with models reaching up to 1 GHz by 2000 and incorporating Streaming SIMD Extensions (SSE) for enhanced multimedia and scientific computing performance.[3] Key specifications included core voltages of 1.8–2.1 V, L1 cache of 16 KB each for instructions and data, and optional 133 MHz FSB in later variants for improved bandwidth.[3] The larger cartridge form factor—measuring approximately 5.5 inches by 2.5 inches—allowed for more cache chips and passive cooling solutions, distinguishing it from the sleeker Slot 1 used in Pentium II desktop CPUs.[1] Slot 2's design facilitated easy upgrades in enterprise settings but was eventually superseded by Socket 370 and Pin Grid Array (PGA) sockets with the shift to Pentium 4 and later architectures around 2001.[1] Despite its short lifespan, it played a crucial role in powering early multi-processor systems for business applications, emphasizing Intel's focus on segmented markets for consumer versus professional computing.[2]Overview
Definition and Purpose
Slot 2 is the physical and electrical specification for the 330-lead Single Edge Contact (SEC) cartridge, developed by Intel as an interface for its Pentium II Xeon processors and subsequent server-oriented variants.[4][2] This cartridge design integrates the processor core, L2 cache, and thermal management components into a single, socketable module that connects via the SC330 edge connector, enabling robust handling and performance in demanding environments.[4] The primary purpose of Slot 2 was to support high-performance server and workstation applications by accommodating larger L2 cache sizes—up to 2 MB—operating at full core speed to eliminate performance bottlenecks common in earlier designs.[2] Unlike consumer-focused interfaces, it provided enhanced power delivery capabilities, with initial voltage specifications of 2.0 V for the core (VCCCORE) and 1.5 V for I/O, remaining at 2.0 V for both core and L2 cache in 450 MHz models.[2] This configuration, with power regulation handled by motherboard circuitry rather than an integrated voltage regulator module on the cartridge, allowed for up to four-processor multiprocessing and support for up to 64 GB of physical memory, prioritizing scalability and reliability in enterprise systems.[2] Introduced in June 1998, Slot 2 formed a key element of Intel's strategy to strengthen its position in the mid-range to high-end server market, directly challenging RISC-based systems from competitors like Sun and HP through improved memory bandwidth and floating-point performance.[5][2] By enabling these advancements in a cost-effective x86 architecture, it helped Intel capture a growing segment projected to exceed $2 billion in revenue by 2001.[5]Physical Design
The Slot 2 connector utilizes a 330-contact edge connector with gold-plated fingers arranged at a 1.0 mm pitch, designed for high-volume server and workstation applications. This edge-card interface connects the processor cartridge to the motherboard, enabling a robust mechanical and electrical linkage optimized for multi-processor environments. The cartridge itself adopts a Single Edge Contact (SEC) form factor, enclosing the processor die and L2 cache chips within a protective plastic housing that includes an integrated substrate for component mounting. Unlike earlier Slot 1 designs, the SEC omits an onboard voltage regulator module (VRM), with power regulation instead handled by dedicated circuitry on the motherboard to support higher power demands in server configurations.[4][6] The overall cartridge measures approximately 6.00 inches (152 mm) in length by 4.99 inches (127 mm) in height, providing ample space for larger cache configurations up to 2 MB while maintaining compatibility with standard server chassis. The edge connector spans roughly the length of the cartridge's substrate, requiring precise insertion to ensure all 330 contacts align without damage. A dedicated retention mechanism, featuring plastic clips and latch arms, secures the cartridge in place, offering stability against vibrations in multi-processor systems. The design incorporates a designated area on the plastic cover for mounting passive heatsinks, along with insulating materials to prevent electrical shorting between components and the chassis.[6][4] In contrast to traditional pin-grid socket designs, Slot 2's edge-card insertion facilitates simpler upgrades in server environments by allowing the entire cartridge to be swapped without socket manipulation, though it demands careful alignment to avoid bending the delicate gold fingers. This mechanical approach prioritizes ease of maintenance in enterprise settings, where motherboards often integrate multiple Slot 2 interfaces alongside onboard power delivery components.[4]Development and History
Origins in Pentium II Architecture
Slot 2 emerged as an evolution of the Slot 1 interface developed for the Pentium II processor, but it was specifically redesigned for the Pentium II Xeon variants to meet the demands of server and workstation environments. This redesign addressed key server requirements, including support for error-correcting code (ECC) memory to enhance data integrity in mission-critical applications and scalability for multi-processor configurations, enabling up to four CPUs in symmetric multiprocessing (SMP) setups.[7] Unlike the consumer-oriented Pentium II, which prioritized cost-effective desktop performance, the Slot 2 architecture facilitated these enterprise features by expanding the cartridge size and pin count to integrate additional signaling for reliability and parallelism. A pivotal engineering choice in Slot 2's creation was the adoption of a larger single-edge contact cartridge (SECC) to house off-die L2 cache operating in pipeline burst mode at full processor speed, which significantly lowered access latency compared to the half-speed on-cartridge cache used in standard Slot 1 Pentium II implementations. This configuration allowed for L2 cache sizes up to 2 MB directly on the module, optimizing bandwidth for data-intensive server workloads without relying on motherboard-mounted cache solutions that could introduce variability and higher latency. The triple-row pin design of Slot 2, with 330 contacts, provided the necessary electrical pathways to support this integrated cache while maintaining backward electrical compatibility with Slot 1 systems where feasible. During Intel's research and development efforts from 1997 to 1998, a primary focus was ensuring compatibility with a 100 MHz front-side bus (FSB) to boost inter-processor communication and memory throughput in multi-socket systems. Initial prototypes underwent rigorous testing for thermal dissipation, targeting capabilities up to a 30 W thermal design power (TDP) to handle the increased heat from full-speed cache and higher bus speeds in densely packed server chassis. These tests validated the cartridge's heat spreader and airflow integration, preventing thermal throttling under sustained loads typical of enterprise computing.[7][8] The integration of a voltage regulator module (VRM) directly on the Slot 2 cartridge represented a forward-thinking design to decouple power delivery from the motherboard, allowing independent scaling of core voltages for evolving clock speeds without requiring widespread board redesigns. This on-cartridge VRM supported variable supply levels, such as 2 V for early models, while distributing power efficiently across the larger module to minimize voltage droop in multi-processor environments. By isolating power management to the processor cartridge, Intel aimed to extend the lifespan of Slot 2-based systems amid rapid advancements in fabrication processes and performance demands.Timeline of Introduction and Evolution
Slot 2 was first publicly showcased by Intel at the Spring Intel Developer Forum (IDF) on February 17, 1998, during a keynote address by CEO Andrew Grove, where it was presented as the connector for upcoming high-end server and workstation processors to enable multiprocessor configurations.[9] On April 20, 1998, Intel announced the "Pentium II Xeon" brand name for its new line of server-oriented processors, signaling the impending debut of Slot 2-based systems.[10] The Slot 2 connector officially debuted on June 29, 1998, alongside the initial Pentium II Xeon processors at 400 MHz, featuring 512 KB, 1 MB, or 2 MB of Level 2 cache and a 100 MHz front-side bus, targeted at dual- and quad-processor enterprise environments.[11] In early 1999, Slot 2 evolved to support the Pentium III Xeon family, with the first models introduced on March 17, 1999, using the Tanner core at 500 MHz and retaining the 100 MHz front-side bus for improved performance in multi-user workloads. A significant update arrived in October 1999, when Intel released Coppermine-core Pentium III Xeon processors compatible with Slot 2, introducing support for a 133 MHz front-side bus alongside the existing 100 MHz option, which enhanced data throughput for database and virtualization applications. These Coppermine variants, such as the 667 MHz models with 1 MB or 2 MB cache, marked a shift to 0.18-micron manufacturing for greater efficiency.[12] By 2000, Slot 2 reached its performance peak with extensions to higher clock speeds, including the release of 933 MHz Pentium III Xeon processors in May and culminating in the industry's first gigahertz server processor, the 1 GHz Pentium III Xeon with 256 KB cache, on August 22, 2000.[13][14] This model, still using the Coppermine core and optional 133 MHz front-side bus, along with larger cache variants up to 2 MB, catered to demanding enterprise tasks like scientific simulations. Major server vendors, including Dell with its PowerEdge 6300 series and HP with NetServer LH 4 models, saw peak adoption of Slot 2 systems around this period for mid-range enterprise deployments. Slot 2 began phasing out in 2001 as Intel transitioned to pin-grid array sockets for next-generation Xeons. The introduction of the first NetBurst-based Intel Xeon processors on May 21, 2001, utilizing Socket 603, effectively ended new Slot 2 developments, with production winding down by 2002 in favor of the more scalable PGA designs.[15]Technical Specifications
Electrical and Signaling Characteristics
The Slot 2 interface employs a front-side bus operating at 100 MHz or 133 MHz using Gunning Transceiver Logic Plus (GTL+) signaling, featuring a 64-bit data path that delivers a theoretical peak bandwidth of up to 1.06 GB/s at the higher clock speed.[16] This bus architecture facilitates efficient data transfer between the processor cartridge and the chipset, supporting the demands of server and workstation environments.[11] Power delivery for Slot 2 processors is specified at a core voltage typically ranging from 1.65–2.1 V via VID pins (2.0 V for early Pentium II Xeon models), with thermal design power (TDP) reaching up to 35 W for high-end models such as the 450 MHz Pentium II Xeon variants. Current draw at the core can peak at approximately 14 A under full load for the 450 MHz model, estimated via the basic power equation: P = V_{\text{core}} \times I_{\text{core}} where P represents power in watts, V_{\text{core}} is the core voltage, and I_{\text{core}} is the core current; this formulation underscores the need for robust regulation to maintain stability (noting TDP includes cache and other components).[16] Signaling on Slot 2 utilizes Advanced GTL+ (AGTL+) for address and control lines, incorporating differential techniques to minimize noise and crosstalk in symmetric multiprocessing (SMP) configurations with up to four processors.[16] This approach enhances signal integrity across multi-drop bus topologies, complemented by support for the Advanced Programmable Interrupt Controller (APIC) via dedicated PICCLK and PICD[1:0] signals, enabling efficient interrupt handling in SMP systems.[17] A distinctive feature of Slot 2 is the integration of a Voltage Regulator Module (VRM) directly on the processor cartridge, which manages voltage regulation and supports dynamic voltage scaling through VID[4:0] pins that allow automatic adjustment to processor-specific requirements ranging from 1.8 V to 2.8 V. This on-cartridge design simplifies motherboard compatibility across voltage variants. L2 cache operates at full core speed with optimized access latencies.[18]Connector and Pin Configuration
The Slot 2 connector utilizes a 330-pin single-edge contact (SEC) design, with 165 gold-plated pins on each side of the processor cartridge edge for interfacing with the motherboard slot. This configuration supports the high-bandwidth requirements of the Pentium II Xeon processor, including a 64-bit data path and advanced server features. The connector incorporates two keying notches—one near the leading edge and another offset—to ensure correct insertion orientation and prevent compatibility with shorter Slot 1 cartridges.[19][20] The 330 pins are functionally grouped into signal lines for address, data, and control; power and ground supplies; and reserved connections. Signal pins dominate the allocation, carrying the processor's external bus interface, while power pins distribute core voltage and termination references. Reserved pins are designated for future use or no-connect status to maintain compatibility across revisions. This pin distribution enables robust multi-processor configurations in server environments.[19][20] Key signal groups include the 36-bit physical address bus A[35:0]#, which handles memory addressing across the front-side bus (FSB), and the 64-bit data bus D[63:0]# for bidirectional data transfer. Control signals such as the bus clock BCLK (driving FSB timing at 100 MHz) and reset RESET# occupy dedicated early-row pins (e.g., pins 1-66 on the B-side include initial clock and reset lines). Error correction and reporting use specific pins like BERR# for bus error detection in ECC-enabled systems. Power delivery is managed through multiple VCC_CORE pins (VCCP at 2.0 V nominal, with up to 35 pins supporting currents to 14 A) and VSS grounds, alongside VTT (1.5 V) for AGTL+ signal termination.[19][21][22] The following table summarizes critical pin mappings for major functional groups, based on the A-side and B-side layouts (pins numbered sequentially from the leading edge):| Side | Pin Range | Key Signals | Function |
|---|---|---|---|
| A | 1-66 | BCLK (A97), RESET# (B98, cross-side reference) | FSB clock distribution and system reset initiation |
| A/B | 20-120 | A[35:0]# (e.g., A#(35) at B101, A#(0) at B23) | 36-bit address bus for memory and I/O access |
| A/B | 40-150 | D[63:0]# (e.g., D#(63) at B46, D#(0) at B96) | 64-bit bidirectional data bus |
| A/B | Scattered | BERR# (A100), AERR# (B99) | Bus error reporting and parity checking for ECC |
| A/B | Multiple (e.g., B2, B5, A5) | VCC_CORE (VCCP), VSS | Core power (2.0 V) and ground distribution |
| A/B | Scattered | VTT, RESERVED (e.g., A26, B3) | Termination voltage (1.5 V) and no-connect pins |