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Common gate

The common-gate configuration is a fundamental amplifier topology in electronics for field-effect transistors (FETs), including junction FETs (JFETs) and metal-oxide-semiconductor FETs (MOSFETs), where the input signal is applied to the source terminal, the output is taken from the drain terminal, and the gate is connected to ground or a fixed bias voltage, effectively making it the common terminal for both input and output signals.^[1] This setup results in a non-inverting voltage gain, low input impedance, and high output impedance, making it suitable for applications requiring current buffering or impedance matching in multistage amplifiers.^[2] Unlike the more common-source configuration, which inverts the signal, the common-gate provides unity current gain and is often used in cascode amplifiers to improve bandwidth and isolation.^[1] Key characteristics of the common-gate amplifier include a midband voltage gain typically approximated as A_v \approx g_m R_D, where g_m is the transconductance of the transistor and R_D is the drain resistance, assuming negligible channel-length modulation and body effect.^[2] The input resistance is low, on the order of $1/g_m (often around 100–500 Ω for typical devices), which contrasts with the high input impedance of common-drain (source follower) configurations and makes it ideal for driving low-impedance sources like transmission lines.^[1] Output resistance approximates R_D, providing good current drive capability.^[2] In JFET implementations, similar principles apply, with no phase inversion between input and output, and the configuration shares analogies with the common-base bipolar junction transistor amplifier in terms of low input impedance and high gain stability.^[3] The common-gate topology is less frequently used as a standalone amplifier compared to common-source or common-drain due to its low input impedance, but it excels in integrated circuits for high-frequency applications, such as RF amplifiers, where its ability to handle high currents and provide isolation is beneficial.^[1] Design considerations often involve selecting appropriate biasing to ensure operation in the saturation region, with source degeneration resistors to stabilize gain and improve linearity.^[2] Overall, it remains a cornerstone in analog electronics for scenarios demanding precise current amplification and minimal Miller effect.^[3]

Overview

Definition and principles

The common-gate amplifier is one of the three basic configurations for field-effect transistor (FET) amplifiers, along with the common-source and common-drain arrangements, in which the gate terminal serves as the common element between the input and output circuits. This setup leverages the voltage-controlled nature of FETs, such as JFETs and MOSFETs, to process signals where the gate is maintained at a fixed potential. At its core, the common-gate configuration applies the input signal to the source terminal and extracts the output from the drain terminal, with the gate AC-grounded through a bypass capacitor or direct connection to ground for signal purposes. This arrangement results in a low input impedance looking into the source terminal, approximately $1/g_m, due to the effect of source degeneration, where variations in source voltage modulate the channel current and the gate-to-source voltage.^[4] The transconductance parameter, g_m, which quantifies the relationship between the small-signal drain current and the gate-to-source voltage, is central to its performance as it governs the device's responsiveness to input variations. The common-gate topology emerged in the mid-20th century as part of the foundational developments in transistor amplifier designs, coinciding with the practical realization of JFETs in the 1950s and MOSFETs in the late 1950s to early 1960s. In operation, it does not invert the polarity of the input signal relative to the output and acts primarily as a current buffer, facilitating applications that require unity current gain with minimal phase shift.^[1]

Basic circuit configuration

The common-gate amplifier employs a field-effect transistor (FET), typically a junction FET (JFET) or metal-oxide-semiconductor FET (MOSFET), in a configuration where the gate terminal serves as the common node, connected directly to ground for both direct current (DC) and alternating current (AC) signals. The input signal is applied to the source terminal through an input coupling capacitor to isolate the AC signal from any preceding DC bias, while the output signal is extracted from the drain terminal via an output coupling capacitor, which connects to the load. A drain resistor (R_D) is placed between the drain and the positive power supply (V_{DD}), providing a path for the drain current and setting the DC operating point at the output. Key components in this setup include the source resistor (R_S), connected between the source terminal and ground, which establishes the DC bias current by developing a voltage drop that influences the gate-to-source voltage (V_{GS}). Coupling capacitors at the input and output prevent DC offsets from affecting the signal path, and the power supply V_{DD} (often with a ground reference) energizes the circuit. In some designs, a bypass capacitor is added in parallel with R_S to shunt AC signals to ground, effectively removing R_S from the AC signal path while preserving its DC biasing function. Biasing techniques for the common-gate circuit vary by device type. For JFETs, which are typically depletion-mode devices, self-biasing is commonly used: the gate is grounded, and R_S generates a negative V_{GS} through the device's inherent pinch-off characteristics, stabilizing the operating point without additional gate voltage. In MOSFET configurations, enhancement-mode NMOS devices require the source to be biased negatively relative to the grounded gate to turn the channel on; this is achieved by adjusting R_S and V_{DD} to set an appropriate drain current, often with the substrate (body) tied to the source or the most negative supply to minimize body effect. Depletion-mode MOSFETs adapt similarly to JFETs, relying on R_S for self-bias. Variations in the circuit accommodate different FET types and signal requirements. For instance, in high-frequency applications, the input coupling capacitor may be omitted if the source is driven directly by a low-impedance source, and active current sources can replace R_D for improved linearity, though passive resistor-based setups remain standard for basic implementations. These adaptations ensure the configuration's suitability as a current buffer while maintaining the gate's grounded reference.

Comparison to other configurations

Versus common source

The common-gate (CG) amplifier configuration provides a non-inverting output signal with a phase shift of 0°, in contrast to the common-source (CS) amplifier, which inverts the input signal by 180°.^[5]^[1] This difference arises from the input signal application: in CG, the signal is applied to the source while the gate is grounded, resulting in the output at the drain following the input polarity, whereas in CS, the gate input leads to inversion through the drain output.^[5] In terms of impedance profile, the CG amplifier exhibits low input impedance, approximately $1/g_m where g_m is the transconductance, typically on the order of a few hundred ohms, paired with high output impedance similar to that of the CS amplifier.^[5]^[6] This contrasts sharply with the CS amplifier's high input impedance (ideally infinite) and moderate output impedance.^[6]^[7] The low input impedance of the CG makes it suitable for interfacing with low-impedance sources, while the CS's high input impedance is advantageous for voltage-driven signals.^[5] Regarding gain types, the CG amplifier achieves unity current gain (approximately 1), with moderate voltage gain given by g_m R_D where R_D is the drain resistance, whereas the CS amplifier provides high voltage gain (magnitude g_m R_D) but lower effective current gain due to its negligible input current.^[5]^[6] The unity current gain in CG stems from the direct path of current from source to drain, making it effective for current buffering.^[1] The CG configuration is particularly suited for current buffering and high-frequency applications, where its low input impedance facilitates maximum power transfer from preceding low-impedance stages and avoids the Miller capacitance effect present in CS.^[5]^[7] In comparison, the CS amplifier is preferred for general voltage amplification due to its high input impedance and inverting gain, which is useful in multi-stage designs requiring phase shifts.^[5]^[6]

Versus common drain

The common-gate (CG) amplifier functions primarily as a current buffer, providing unity current gain where the output current closely mirrors the input current, typically with a current gain of approximately 1. In contrast, the common-drain (CD) amplifier, also known as the source follower, serves as a voltage buffer, offering a voltage gain near unity while featuring high input impedance and low output impedance to effectively isolate stages or drive loads without significant voltage attenuation.^[8]^[4]^[8] Both configurations exhibit non-inverting phase response, preserving the input signal's polarity at the output. However, the CG amplifier's output impedance is relatively high and dominated by the drain resistance (Rd), making it suitable for applications requiring current delivery to high-impedance loads, whereas the CD amplifier's output impedance is low, approximately 1/gm (where gm is the transconductance), enabling it to drive low-impedance loads effectively.^[1]^[8]^[9] In terms of power handling, the CG amplifier is particularly advantageous for high-power radio frequency (RF) applications due to its low input capacitance, which minimizes parasitic effects and supports broader bandwidths in RF chains. Conversely, the CD amplifier is more oriented toward impedance matching, leveraging its high input and low output impedances to interface between stages with differing impedance levels, such as in output buffering or signal conditioning.^[10]^[11] A key trade-off in the CG configuration is the sacrifice of input impedance—typically low at around 1/gm—for enhanced bandwidth, as the reduced Miller effect at the input allows higher-frequency operation without significant gain roll-off. The CD configuration, by prioritizing faithful voltage following with minimal gain (close to 1), emphasizes stability and load driving capability over amplification, making it less suited for bandwidth-critical paths but ideal for preserving signal integrity in follower roles.^[12]^[13]

Electrical characteristics

Input and output impedance

The input impedance of the common-gate amplifier is characteristically low, making it suitable for applications requiring current buffering. In the configuration where the source is bypassed with a capacitor for alternating-current (AC) signals, the input impedance Z_{\text{in}} looking into the source is approximately \frac{1}{g_m}, with g_m denoting the transistor's transconductance. This low value arises from the small-signal hybrid-π model, where the gate is AC-grounded, yielding v_{gs} = -v_{\text{in}}; the input current is then i_{\text{in}} = g_m v_{gs} + \frac{v_s}{r_o} \approx g_m (-v_{\text{in}}) (neglecting the high r_o), so Z_{\text{in}} = \frac{v_{\text{in}}}{i_{\text{in}}} \approx \frac{1}{g_m}.^[2]^[14] When the source degeneration resistor R_s is unbypassed, the source degeneration effect increases the input impedance to approximately Z_{\text{in}} = R_s + \frac{1}{g_m}. Here, the total input voltage v_{\text{in}} = i_{\text{in}} R_s + v_s, with v_s \approx i_{\text{in}} / g_m from the transistor's source terminal, leading to the additive form that reflects reduced sensitivity to variations due to feedback.^[2]^[15] The output impedance Z_{\text{out}}, measured looking into the drain with the input short-circuited (source AC-grounded), is approximately the drain resistor R_d in parallel with the transistor's early output resistance r_o, so Z_{\text{out}} \approx R_d \parallel r_o. Since r_o is typically much larger than R_d, Z_{\text{out}} \approx R_d, resulting in a high value that exceeds the input impedance. This elevated output impedance stems from the grounded gate, which eliminates the Miller multiplication of the gate-drain capacitance and prevents feedback degradation.^[8]^[2] These impedances depend on key parameters: g_m, which scales inversely with input impedance and is proportional to the drain bias current I_D and overdrive voltage; R_s, which directly adds to input impedance when present; and the channel-length modulation parameter \lambda, where r_o = \frac{1}{\lambda I_D} modulates the output impedance by affecting early voltage effects in longer-channel devices.^[14]^[15] In practice, Z_{\text{in}} and Z_{\text{out}} are determined analytically from the small-signal model or via simulation in tools like SPICE, applying a test voltage source at the port and computing the ratio to the resulting current. Experimental measurement involves injecting a small AC test signal and using an oscilloscope with a series resistor to derive the current, or employing network analyzers for S-parameter extraction under biased conditions.^[6]^[14]

Voltage and current gain

The low-frequency small-signal voltage gain A_v of a common-gate MOSFET amplifier, defined as the ratio of output voltage at the drain to input voltage at the source, is derived using the hybrid-π model. In the ideal case with infinite channel-length modulation parameter (i.e., infinite output resistance r_o) and no external load beyond the drain resistor R_D, the gain simplifies to A_v = g_m R_D, where g_m is the transconductance of the MOSFET.^[14]^[16] To derive this using nodal analysis, consider the small-signal equivalent circuit: the gate is AC-grounded, the input voltage v_i is applied directly to the source (no series resistance), and the output is taken at the drain across R_D to ground. The gate-source voltage is v_{gs} = -v_i since the gate is at 0 V. The MOSFET is modeled with a voltage-controlled current source g_m v_{gs} directed from drain to source and no r_o term. Applying Kirchhoff's current law (KCL) at the drain node, the sum of currents leaving the node is zero:

\frac{v_o}{R_D} + g_m v_{gs} = 0

Substituting v_{gs} = -v_i and v_o = A_v v_i:

\frac{A_v v_i}{R_D} + g_m (-v_i) = 0 \implies A_v v_i \left( \frac{1}{R_D} - g_m \right) = 0 \implies A_v = g_m R_D

This positive gain arises because the input at the source inverts the v_{gs}, and the drain current flows through R_D to produce an in-phase output relative to the input.^[14]^[16] When an external load R_L is present in parallel with R_D, the effective load becomes R_D \parallel R_L, yielding A_v = g_m (R_D \parallel R_L). Including the non-ideal finite output resistance r_o (due to channel-length modulation), the derivation incorporates the term (v_o - v_i)/r_o in the KCL at the drain node:

\frac{v_o}{R_D} + g_m (-v_i) + \frac{v_o - v_i}{r_o} = 0

Rearranging terms:

v_o \left( \frac{1}{R_D} + \frac{1}{r_o} \right) = v_i \left( g_m + \frac{1}{r_o} \right) \implies A_v = \frac{g_m + 1/r_o}{1/R_D + 1/r_o} = (g_m + 1/r_o) (R_D \parallel r_o)

For typical operation where g_m \gg 1/r_o, this approximates to A_v \approx g_m (R_D \parallel r_o), reducing the gain compared to the ideal case as r_o shunts the load. With R_L, replace R_D by R_D \parallel R_L \parallel r_o.^[14]^[16] The presence of an unbypassed source resistance R_s (e.g., for degeneration or bias) reduces the voltage gain by providing negative feedback. In the small-signal model, R_s is in series with the source, so the source voltage v_s = v_i - i_i R_s, where i_i is the input current. For infinite r_o and no R_L, the effective transconductance decreases, leading to A_v \approx \frac{g_m R_D}{1 + g_m R_s}. This degeneration stabilizes the gain against variations in g_m but lowers its magnitude, with the denominator term dominating for g_m R_s \gg 1. Including finite r_o, the formula becomes A_v \approx \frac{g_m (R_D \parallel r_o)}{1 + g_m R_s + R_s / r_o}.^[14] The low-frequency small-signal current gain A_i, defined as the ratio of output current at the drain to input current at the source, is approximately unity (A_i \approx 1). This results from the buffering action of the common-gate configuration, where the input current entering the source nearly equals the output current leaving the drain, as the gate draws negligible current and the device acts as a current follower. In the short-circuit output condition (drain shorted to ground for current gain measurement), i_o = -g_m v_{gs} + (0 - v_s)/r_o \approx g_m v_i (with v_{gs} = -v_i), and the input current i_i \approx g_m v_i since the input resistance is $1/g_m, yielding A_i = i_o / i_i \approx 1. Finite r_o introduces a small deviation, but A_i remains close to 1 for most practical biases.^[4]^[8]

Applications and performance

Practical uses

The common-gate amplifier finds prominent use in RF and microwave circuits, particularly as the upper stage in cascode configurations within low-noise amplifiers (LNAs), where its low input capacitance minimizes Miller effect and enhances high-frequency performance, while providing high reverse isolation to prevent feedback. This topology supports wideband operation up to several GHz, making it suitable for receivers in wireless communication systems. For instance, common-gate LNAs have been designed for broadband input matching in microwave applications, optimizing signal current at the output.^[17] In instrumentation and sensing applications, the common-gate configuration serves as a building block for high-accuracy current mirrors and sensors, benefiting from its unity current gain that faithfully transfers input current to the output with minimal distortion. A precision high-voltage current sensing circuit employing a common-gate pMOS differential input pair with high gain (~140 dB) and low input offset (<1 mV) is suitable for monitoring in power systems.^[18] Similarly, sense amplifiers with common-gate input stages detect currents as low as 100 µA, delivering rail-to-rail digital outputs with high bandwidth (up to 3.5 GHz) and low noise, as applied in ferroelectric random-access memory (FeRAM) and optical transceivers.^[19] The common-gate amplifier's inherently low input impedance, approximately 1/g_m, enables effective impedance transformation in matching networks for antennas and low-impedance sources within communication systems, facilitating efficient power transfer without additional matching components. This property is leveraged in RF front-ends to match the amplifier input to source impedances, improving signal reception in blocker-resilient receivers. Historically, common-gate stages appeared in early transistor-based RF amplifiers during the mid-20th century to handle high-frequency signals in compact designs, evolving into modern CMOS RF integrated circuits for 5G and beyond. In contemporary 5G applications, common-gate structures form capacitively cross-coupled input stages in mmWave down-converter ICs operating from 18–28 GHz, supporting high-data-rate communications and joint sensing systems with gains of 4.5–7.5 dB.^[20]^[21] Stacked common-gate transistors in CMOS SOI power amplifiers further enhance efficiency for sub-6 GHz and mmWave 5G bands.^[20]^[21] Recent advancements include D-band (110-170 GHz) bidirectional common-gate amplifiers for future 6G communications, leveraging CMOS symmetry for high-frequency operation.^[22]

Advantages and limitations

The common-gate configuration offers several key advantages in amplifier design, particularly for high-frequency applications. Its structure minimizes the Miller effect on the gate-drain capacitance, resulting in low effective input capacitance and enabling high bandwidth operation.^[23] Additionally, it provides good linearity for handling large signals, making it suitable for scenarios requiring distortion-free amplification.^[24] The configuration also exhibits a stable current gain approximately equal to unity, which ensures reliable current buffering without significant amplification variability across frequencies.^[25] Despite these strengths, the common-gate amplifier has notable limitations. The low input impedance, typically on the order of 1/g_m, demands a low-impedance source to drive it effectively, often requiring additional buffering stages for compatibility with higher-impedance signals.^[26] Voltage gain is moderate compared to other topologies, generally limited by the load resistance and transconductance, which may necessitate cascading for higher overall gain.^[27] Furthermore, performance is sensitive to source termination, as mismatches can degrade stability and noise figure.^[26] Design trade-offs in common-gate amplifiers involve balancing source resistance (R_s) to achieve stability while avoiding excessive gain reduction, as higher R_s improves isolation but lowers input matching.^[26] Biasing currents must also be optimized to minimize power consumption without compromising linearity or bandwidth, often leading to higher overall power in cascaded designs.^[24] This configuration is generally avoided for applications with high-impedance inputs, where it performs poorly without additional circuitry.^[26]

Analysis methods

Small-signal equivalent circuit

The small-signal equivalent circuit for the common-gate amplifier adapts the hybrid-π model of the MOSFET, with the gate terminal AC-grounded such that the gate-to-source voltage v_{gs} = 0 relative to the gate but effectively v_{gs} = -v_{is} due to the input signal applied at the source.^[14] In this configuration, the small-signal input voltage v_{is} drives the source, while the output voltage v_{od} is observed at the drain; the model incorporates the voltage-controlled current source g_m v_{gs} = -g_m v_{is}, the drain-to-source output resistance r_{ds}, and neglects parasitic capacitances such as C_{gs} and C_{gd} due to their minimal impact at low frequencies.^[14]^[3] The equivalent circuit consists of a dependent current source g_m v_{is} directed from the drain to the source (accounting for the sign inversion from v_{gs}), with r_{ds} connected in parallel between drain and source terminals.^[14] The source resistor R_s appears in series with the input signal at the source node, and the drain resistor R_d is in series with the output at the drain node; the gate remains grounded for AC signals, and any body effect or other parasitics are typically omitted in this basic low-frequency representation.^[14] This circuit facilitates linear analysis around the DC operating point without considering frequency-dependent effects.^[3] Key parameters g_m (transconductance) and r_{ds} (output resistance) are extracted from the MOSFET datasheet curves at the chosen bias point in the saturation region, assuming small-signal perturbations that maintain linear operation.^[14] Specifically, g_m is found from the slope of the drain current I_D versus gate-source voltage V_{GS} curve at constant V_{DS}, or approximated as g_m \approx 2 \sqrt{K I_D}, where K = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} is the device transconductance factor and I_D is the DC drain bias current.^[14] Likewise, r_{ds} is derived from the slope of the I_D versus V_{DS} curve at constant V_{GS}, given by r_{ds} = \frac{1}{\lambda I_D}, where \lambda is the channel-length modulation parameter specified in the datasheet.^[28] These values ensure the model accurately represents device behavior for signals much smaller than the bias voltages.^[14] Analysis of the circuit involves setting up Kirchhoff's current law (KCL) equations at the source and drain nodes, supplemented by Kirchhoff's voltage law (KVL) loops if needed to relate voltages across elements.^[14] For instance, KCL at the source node sums the input current through R_s, the portion of the dependent current source, and any current through r_{ds}; similarly, at the drain node, the current source g_m v_{is} plus the r_{ds} branch current equals the output current through R_d.^[3] Solving these simultaneous equations yields expressions for output voltage, input impedance, or other parameters as functions of the model elements.^[14]

Frequency response considerations

The common-gate amplifier exhibits advantageous high-frequency performance primarily due to the absence of the Miller effect on the gate-drain capacitance C_{gd}, as the gate-source voltage v_{gs} remains approximately zero under small-signal conditions.^[29] This configuration grounds the gate, preventing voltage amplification across C_{gd} that would otherwise multiply its effective capacitance at the input, unlike in common-source amplifiers where feedback significantly degrades bandwidth.^[30] Consequently, the common-gate stage achieves a high transition frequency f_T = \frac{g_m}{2\pi (C_{gs} + C_{gd})}, often approaching the device's intrinsic f_T when the load resistance is not excessively large, yielding a superior gain-bandwidth product for wideband applications.^[29] In the frequency-dependent small-signal model, parasitic capacitances such as C_{gs} (gate-source) and C_{ds} (drain-source) are incorporated alongside the basic hybrid-π equivalent circuit.^[30] The dominant poles arise from the time constants associated with these elements: the input pole from \tau_{in} \approx (R_S \parallel 1/g_m) C_{gs}, where R_S is the source resistance, and the output pole from \tau_{out} \approx R_D (C_{gd} + C_{ds} + C_L), with R_D as the drain resistance and C_L the load capacitance.^[29] Notably, the time constant involving R_D C_{gd} remains minimal without Miller multiplication, contributing to pole locations at higher frequencies compared to configurations with pronounced feedback.^[30] The frequency roll-off is typically determined by the lower of the input and output poles, with the input pole frequency approximated as f_{p,in} \approx \frac{1}{2\pi (R_S \parallel 1/g_m) C_{gs}}. When R_S \gg 1/g_m, this becomes f_{p,in} \approx \frac{g_m}{2\pi C_{gs}}.^[29] For unity-gain bandwidth, particularly in current-buffer roles where the midband voltage gain approaches 1, this extends toward the device's f_T, enabling operation up to several GHz in RF integrated circuits.^[30] In radio-frequency applications, the common-gate topology outperforms the common-source by minimizing feedback capacitance effects, providing better isolation and stability at high frequencies.^[29]

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