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Cascode

A cascode is a two-stage configuration in that stacks a transconductance stage—typically a for junction transistors (BJTs) or for metal-oxide-semiconductor field-effect transistors (MOSFETs)—with a or stage, respectively, to minimize the and enhance performance. The term "cascode" is a portmanteau of "cascade to cathode," first used in a 1939 paper by F.V. Hunt and R.W. Hickman describing vacuum tube circuits as a cascade of a grounded-cathode stage followed by a grounded-grid stage. This topology was developed as a technique to counteract the Miller capacitance in triode amplifiers, providing an alternative to pentode tubes which were introduced in the 1920s. It was reintroduced for solid-state devices after the 1947 invention of the transistor, with early cascode references appearing in the literature in the late 1930s for vacuum tubes, and the topology adapted for BJTs post-1947. A notable patent for a cascode amplifier using transistors was filed in 1952 by Edwin Keith Nelson. Key advantages of the cascode include wide due to reduced feedback —often achieving frequencies up to 5 MHz compared to 2 MHz in single-stage common-emitter amplifiers—high for better voltage gain (e.g., approximately -181 in the stage), and moderately high in the kilohm range. It also provides low noise and improved stability, making it suitable for high-frequency applications. Historically applied in ultra-high-frequency (UHF) television tuners and intermediate-frequency (IF) amplifiers before the advent of RF dual-gate MOSFETs, cascodes remain prevalent in modern RF/ circuits, power amplifiers, and operational amplifiers for their ability to handle high voltages and frequencies while maintaining .

Introduction

Definition and Basic Configuration

The cascode is a two-stage that combines a stage with a stage to realize high and in circuits. This configuration originated in as a circuit known as a of grounded and grounded stages. In its basic form using bipolar junction transistors (BJTs), the cascode employs a stage followed by a stage. The input signal is applied to the base of the CE transistor (Q1), whose collector connects directly to the emitter of the CB transistor (Q2), with the base of Q2 typically AC-grounded via a . The output is taken from the collector of Q2 across a load . Here, the CE transistor (Q1) serves as the input stage, handling voltage from the signal source, while the CB transistor (Q2) acts as the output stage, providing current buffering to isolate the input from the load. For metal-oxide-semiconductor field-effect transistors (MOSFETs), the cascode uses a common-source (CS) stage cascaded with a common-gate (CG) stage, analogous to the BJT version. The input signal drives the gate of the CS transistor (M1), whose drain connects to the source of the CG transistor (M2), with the gate of M2 biased to a fixed voltage. The output appears at the drain of M2 connected to a load. In this setup, the CS transistor (M1) performs the initial voltage amplification, and the CG transistor (M2) delivers current buffering for the output. BJTs and MOSFETs form the building blocks of these configurations, with BJTs being current-controlled devices that amplify based on base-emitter current and MOSFETs being voltage-controlled devices that respond to gate-source voltage.

Historical Overview

The cascode configuration originated in the vacuum tube era during the 1930s as a two-stage amplifier designed to mitigate the and improve high-frequency performance. The term "cascode," derived from "cascade" and "cathode," was first coined by Frederick Vinton Hunt and Roger Wayne Hickman in their seminal 1939 paper "On Electronic Voltage Stabilizers," published in the Review of Scientific Instruments. In this work, the authors described a series-connected pair of triodes—a grounded-cathode input stage followed by a grounded-grid stage—that effectively reduced interelectrode capacitances, enabling higher gain-bandwidth products in voltage stabilization and amplification circuits. During the 1940s, particularly amid , the cascode gained early practical adoption in radio receivers, including superheterodyne designs for military applications, where its superior supported reliable in compact, high-performance systems. This period marked the configuration's shift from theoretical innovation to widespread engineering use, influencing mixer and stages in communication equipment. The transition to solid-state devices occurred in the 1950s following the invention of the (BJT) in 1947. The first documented transistorized cascode circuit is credited to S. H. Bowers at the Signals Research and Development Establishment in , , around the late 1950s, as referenced in a 1960 technical analysis that highlighted its advantages in transistor-based amplifiers. By the 1960s, companies like integrated cascode topologies into early monolithic circuits, such as three-stage amplifiers, to achieve stable high-frequency operation in discrete and integrated designs. In the 1970s, with the rise of metal-oxide-semiconductor field-effect transistors (MOSFETs) and integrated circuits, the cascode evolved further, becoming a staple for enhancing output resistance and bandwidth in analog ICs.

Operation

Transistor-Level Mechanism

In a cascode , the signal flow begins at the input , which operates in a (CE) or (CS) to provide g_m, converting the input voltage to a signal. This is then buffered and directed to the output , configured as (CB) or common-gate (CG), which isolates the input stage's output from the load while delivering the to the output with minimal voltage swing at the intermediate node. The output stage's low , approximately $1/g_{m2} for the upper , ensures that the collector (or ) voltage of the input remains nearly constant, preventing significant and enhancing high-frequency performance. The cascode configuration significantly reduces the , which in a single-stage multiplies the C_{gd} (or C_{\mu} for BJT) by a factor of (1 + |A_v|), where A_v is the large stage , leading to increased input and limitation. In the cascode, the voltage across the of the input , from its output terminal to input terminal, is approximately -1 (assuming matched transconductances), resulting in an effective input C_{in} \approx C_{gd} (1 - A_v) \approx 2 C_{gd}, far smaller than the multiplied value in a non-cascoded stage. This isolation occurs because the low-impedance input of the output stage shields the path, minimizing multiplication and extending the 's . The overall voltage gain of the cascode is derived from the , where the input stage generates a i = g_{m1} v_{in}, which flows largely unattenuated through the output stage due to its current-buffering action, yielding A_v \approx -g_{m1} R_L for a load resistance R_L, with g_{m1} as the of the input . This approximation holds because the output stage contributes negligible additional voltage gain (near unity) but high output resistance, approximating the single-stage times the load. For the BJT cascode, the small-signal model replaces the input CE transistor with a hybrid-pi equivalent (including g_{m1} v_{\pi1}, r_{\pi1}, and r_{o1}) connected at its collector to the emitter of the CB transistor, modeled as a current source g_{m2} v_{\pi2} in parallel with r_{\pi2} and r_{o2}, with the base of the CB transistor AC-grounded. The model shows the input voltage driving v_{\pi1} through r_{\pi1}, generating current that flows into the low-impedance $1/g_{m2} of the CB stage, and the output taken across R_L in parallel with r_{o2}. In the MOSFET cascode, the small-signal model uses voltage-controlled current sources for both transistors: the CS input stage with g_{m1} v_{gs1} and output resistance r_{o1}, feeding the CG output stage with g_{m2} v_{gs2} (where v_{gs2} is the voltage at the source of M2) and r_{o2}, with the gate of the CG transistor AC-grounded. The intermediate node exhibits low impedance \approx 1/g_{m2}, and the overall model highlights the series connection of the two transconductances, with output resistance boosted to approximately g_{m2} r_{o2} r_{o1}. This structure parallels the BJT case, providing similar isolation and gain mechanisms but with MOSFET-specific parameters like channel-length modulation in r_o.

Biasing and Stability

In cascode amplifiers, DC biasing establishes the operating points of the stacked transistors to ensure linear operation while providing sufficient headroom for signal swing. For (BJT) cascodes, a common approach uses a to set the tail current for the common-emitter input stage, ensuring balanced collector currents across differential pairs if applicable. The output stage often employs a or , such as another , to define the collector voltage. The supply voltage must satisfy V_{CC} > 2 V_{BE} + V_{CE,sat}, where V_{BE} is the base-emitter drop (typically 0.7 V) and V_{CE,sat} is the saturation voltage (around 0.2 V), to keep both transistors in the forward-active region; for example, with V_{CC} = 12 V, this allows proper biasing without clipping. For metal-oxide-semiconductor field-effect transistor (MOSFET) cascodes, biasing similarly relies on current mirrors to source the drain current for the common-source input transistor, with the cascode transistor's gate biased via a voltage reference or diode-connected replica to maintain overdrive. The stacked configuration requires the supply to exceed two gate-source drops plus saturation voltages, typically V_{DD} > 2(V_{GS} - V_{TH}) + 2V_{DSAT}, where V_{TH} is the threshold voltage (around 0.5 V) and V_{DSAT} is the saturation overdrive (0.1–0.2 V); low-voltage variants use wide-swing current mirrors to minimize headroom to approximately 1–1.5 V by biasing bottom transistors near the edge of saturation. Active loads, such as PMOS mirrors, further stabilize the output DC level. Analysis of DC operating points confirms current continuity in the cascode stack, where the collector current of the input transistor equals the emitter current of the common-base (or common-gate) stage, I_C \approx I_E, assuming high beta or lambda values. Both transistors must remain in active (BJT) or saturation (MOSFET) regions, verified by checking V_{CE} > V_{CE,sat} for BJTs and V_{DS} > V_{DSAT} for MOSFETs at the quiescient point; deviations can be adjusted via resistor dividers or mirror scaling. Stability in cascode circuits addresses risks like in BJT configurations, where uneven heating increases current in hotter transistors, potentially leading to failure; this is exacerbated by the high amplifying small imbalances. Prevention involves emitter degeneration resistors (typically 10–100 Ω) that provide to equalize currents and dissipate excess heat. High gain can also induce oscillations, particularly from parasitic capacitances or inductive loads; solutions include shunt feedback networks or source/emitter degeneration to reduce the gain-bandwidth product and improve phase margins. A key pitfall in low-voltage designs (below 2 V) is headroom limitation, where the stacked transistors consume 1–2 V for biasing, reducing output swing and risking saturation; this constrains applications in sub-1.8 V processes, often requiring folded cascode variants or reduced overdrive to maintain operation.

Advantages and Disadvantages

The cascode configuration provides several performance advantages over single-transistor amplifiers, primarily through enhanced between input and output stages. One key benefit is the significantly higher , which for a (BJT) cascode approximates g_{m2} r_{o1} r_{o2}, where g_{m2} is the and r_{o1}, r_{o2} are the output resistances of the input and output transistors, respectively; this enables higher voltage gain when loaded. Additionally, the structure achieves wide bandwidth by mitigating the , as the (for BJT) or common-gate (for ) upper transistor shields the input transistor's gate-drain from voltage gain multiplication, reducing effective input capacitance and improving high-frequency response. This results in a gain-bandwidth product enhancement. The configuration also offers improved and reverse , minimizing distortion and signal leakage from output to input. Despite these strengths, cascode amplifiers have notable drawbacks stemming from their two-transistor stack. A primary limitation is the increased supply voltage requirement, as the stacked devices consume additional voltage headroom—typically at least two V_DS,sat (for ) or V_BE + V_CE,sat (for BJT)—which can limit operation in low-voltage environments. This headroom demand often leads to higher power consumption compared to single-stage designs, especially under the same bias current conditions. Furthermore, implementing cascodes in integrated circuits introduces complexity, including challenges in matching devices and routing to avoid parasitic effects that could degrade performance. Trade-offs in cascode designs balance these factors; while the structure generally yields better performance through reduced paths, mismatched s can introduce even-order , potentially compromising overall in applications.

Configurations

BJT Cascode

The BJT cascode employs junction s to form a two-stage , where the input stage is typically an NPN operating in common-emitter mode, with its collector connected to the emitter of the output stage, which is another NPN in mode. This setup provides a current-driven input to the stage, enhancing overall performance. In complementary configurations, a may serve as the output stage for applications requiring inverted polarity or balanced operation. Analysis of the BJT cascode often utilizes h-parameters to model the small-signal behavior of each stage. The forward current gain h_{fe}, equivalent to the transistor's \beta, governs the current amplification in the common-emitter stage, while the input impedance h_{ie} approximates the base-emitter resistance r_{\pi} for the input stage. The common-base stage contributes a current gain near , making the overall current gain approximately equal to \beta of the input transistor, with reduced dependence on variations in \beta compared to a single-stage common-emitter . At low frequencies, the small-signal input resistance r_{in} of the BJT cascode is approximately r_{\pi} of the input transistor, as the low input impedance of the common-base stage does not significantly load the common-emitter collector. The output resistance r_{out} is substantially increased to r_{o2} (1 + g_{m2} r_{\pi 1}), where r_{o2} is the Early-effect output resistance of the output transistor, g_{m2} is its transconductance, and r_{\pi 1} is the input resistance of the input transistor; this approximation holds under the condition that g_{m2} r_{\pi 1} \gg 1, yielding r_{out} \approx \beta_2 r_{o2}. Thermal and matching considerations in BJT cascodes are influenced by \beta variations, which can arise from changes or device mismatches, potentially affecting stability. However, the cascode structure mitigates these effects by isolating the input stage's \beta variations from the output, resulting in voltage that is nearly independent of \beta fluctuations, unlike standalone common-emitter designs. Proper and between transistors are essential to minimize \beta mismatch-induced distortions. In practical implementations, BJT cascodes are commonly used in audio , such as in the voltage amplification stage (VAS) of power , where a cascode boosts and reduces ; for example, a 50 W employs a simple NPN cascode in the VAS to achieve several M\Omega and lower THD by a factor of 5 at low frequencies. Integrated BJT cascodes appear in monolithic audio ICs, like those with cascoded pairs for improved , though they add complexity compared to versions that allow easier and higher voltage handling in high-power designs.

MOSFET Cascode

The MOSFET cascode configuration employs an NMOS transistor in a common-source arrangement as the input stage, with its drain connected to the source of a second NMOS or PMOS transistor configured as a common-gate output stage. The input signal is applied to the gate of the first transistor (M1), while the gate of the output transistor (M2) is held at a fixed bias voltage to control the current path. This setup exploits the transconductance g_{m1} of M1 to generate a signal current, which flows through M2, where the output conductance g_{ds2} plays a key role in determining the stage's impedance characteristics. Channel-length modulation in M2, modeled by g_{ds2} = \lambda I_D (with \lambda as the channel-length modulation parameter and I_D the drain current), reduces the effective output resistance but is mitigated by the cascode topology's feedback mechanism. At low frequencies, the input resistance of the MOSFET cascode is very high (ideally infinite), due to the gate isolation of the common-source input stage. The output resistance is enhanced to r_{out} \approx g_{m2} r_{o1} r_{o2}, where g_{m2} is the of M2 and r_{o1}, r_{o2} are the output resistances of M1 and M2, respectively, providing a substantial increase over a single transistor's r_o by shielding M1 from output voltage variations and amplifying the intrinsic resistance through the g_{m2} effect. These parameters stem from the , where channel-length modulation introduces early voltage effects (V_A = 1/\lambda), limiting the output resistance but enabling high voltage gain A_v \approx g_{m1} r_{out} in amplifiers. Compared to BJT cascodes, MOSFET versions offer inherently higher , facilitating easier integration in voltage-driven circuits. In CMOS integrated circuits, the MOSFET cascode excels in low-voltage environments, such as sub-1 V supplies, by allowing stacking to achieve high output resistance and gain without excessive headroom demands, making it suitable for modern scaled technologies. However, the common-gate M2 experiences body effect, elevating its V_{th2} = V_{th0} + \gamma (\sqrt{|V_{SB} + 2\phi_F|} - \sqrt{2\phi_F}) due to the non-zero source-body voltage V_{SB}, which can degrade performance unless compensated by wider widths. This configuration's isolation also suppresses the Miller multiplication of gate-drain in M1, improving in high-gain applications. MOSFET cascodes find application in switched-capacitor circuits, such as integrators and filters, where their high output resistance ensures precise during sampling and transfer phases, reducing non-idealities like finite gain errors. For instance, in a basic switched-capacitor , the provides differential gains exceeding 60 dB while maintaining settling times under 10 ns in 0.18 μm , outperforming simple common-source stages by minimizing output swing dependencies.

Specialized Variants

The dual-gate MOSFET cascode configuration employs a dual-gate transistor where the first gate receives the RF input signal, while the second gate serves for control or injection, enabling improved isolation and in radio-frequency (RF) circuits. This leverages the cascode structure to minimize capacitance effects, providing high and low suitable for applications. In RF mixers, such as doubly balanced designs operating at frequencies up to 60 GHz, the dual-gate approach facilitates direct up-conversion with active IF baluns, achieving conversion s around 10-15 while suppressing LO-RF leakage. The folded cascode topology addresses low-voltage constraints by folding the cascode branch to stack transistors of opposite , allowing operation with supply voltages as low as 1 V without stacking same-type devices that would exceed threshold limits. This arrangement uses PMOS transistors for the input stage and NMOS for the cascode, or vice versa, to maintain headroom while preserving high . The voltage gain is given by A_v \approx g_{m1} \left( \frac{g_{m} r_o^2}{2} \right) where g_{m1} is the of the input , and the term in parentheses approximates the parallel output resistance of the two cascode branches (assuming matched g_m and r_o), typically yielding gains exceeding 60 dB in complementary implementations. Complementary folded cascode operational amplifiers fabricated in 0.8-μm achieve unity-gain bandwidths of 14 MHz with 5-pF loads, demonstrating suitability for low-power, high-swing applications. Regulated cascode circuits enhance performance by incorporating a loop around the cascode , which regulates the voltage to minimize output conductance and boost output beyond standard cascode levels. This mechanism effectively senses and corrects voltage variations, resulting in an approximate output of r_{out} \approx r_o (1 + g_{m,reg} r_o), where g_{m,reg} is the of the regulating and r_o is the channel of the cascode device. Such designs are particularly valuable in current mirrors and transimpedance amplifiers, where low input (via shunt ) combines with output impedances over 100 times higher than simple mirrors, enabling operation at supplies below 1 V with minimal . Recent variants, such as the recycling folded cascode operational transconductance amplifier (), build on the folded by recycling bias currents to increase effective without additional power, targeting ultra-low-power neural interfaces. Post-2020 developments integrate this in multi-channel systems-on-chip (SoCs) for brain-machine interfaces, achieving noise efficiency factors (NEF) as low as 1.13 and power efficiencies of 12.5 pJ per pulse for impulse radio (IR-UWB) transmission. These OTAs, often chopper-stabilized, support 32-channel neural recording with capacitively coupled inputs to reject offsets, providing gains over 50 while consuming sub-μW per channel in 65-nm processes.

Applications

Traditional Uses in Amplifiers and Mixers

The cascode configuration found early traditional applications in voltage stages of operational amplifiers, where it enabled high output voltage and improved stability by reducing the on the input . In (IF) stages of superheterodyne receivers, cascodes provided high with minimal risk of , thanks to their superior reverse and extension compared to common-emitter configurations. This made them ideal for discrete radios in the 1960s, where stability under varying loads was critical for reliable signal amplification. In mixer circuits for superheterodyne receivers, the cascode served as an effective up- or down-converter by allowing (LO) injection at the common-base or common-gate terminal, which enhanced port-to-port and suppressed LO leakage into the RF path. This topology minimized distortion while maintaining conversion , making it a staple in early RF designs from the mid-20th century. Historical implementations, such as those in and radio tuners, leveraged this isolation to improve overall receiver selectivity without requiring complex filtering. A specialized variant, the dual-gate (FET) cascode, became prominent in television tuners during the for its dual functionality in and mixing, with the second gate enabling (AGC) for dynamic range adjustment and image frequency rejection. Devices like the 40673 dual-gate were commonly employed in VHF/UHF tuners, where the cascode structure provided low and high for up to 500 MHz. This configuration allowed independent control of RF input and LO signals, reducing cross-modulation in consumer TV receivers of the era. The roots of these applications trace back to radio designs, initially with vacuum-tube cascodes for low-noise RF amplification, which transitioned to -based versions in the postwar period for compact, high-performance discrete circuits. By the , cascode IF and stages were standard in commercial amplifiers and receivers, exemplifying their role in enabling operation with enhanced .

Modern Implementations in ICs

In modern integrated circuits, cascode configurations have been pivotal in operational transconductance amplifiers (OTAs) and operational amplifiers (op-amps) for biomedical implants, particularly in low-noise neural recording systems. Recycling folded-cascode OTAs, implemented in sub-micron processes, achieve input-referred densities as low as 4.5 /√Hz while consuming under 10 μW, enabling long-term implantable devices for monitoring neural signals in the 0.1-10 kHz band. A class-AB folded-cascode op-amp with novel biasing, fabricated in 180 nm , delivers a of 80 dB and of 3.2 μVrms, supporting high-fidelity in neural prosthetics with power efficiency below 5 μW. These designs leverage folded variants to extend output swing and reduce in low-voltage environments typical of battery-powered implants. In RF and millimeter-wave applications, cascode structures enhance and efficiency in 5G power amplifiers (), addressing the demands of high-data-rate communications. Differential cascode in 22 nm cover the 24.25-43.5 GHz 5G band, achieving saturated output power of 15.5 dBm and power-added efficiency (PAE) up to 18% at 6 backoff, with improved via neutralisation techniques to mitigate Miller . For ultra-low-voltage (ULV) circuits, cascode stages operated in deep subthreshold (supply <0.5 V) boost DC to over 60 in single-stage OTAs, enabling energy-harvesting nodes with sub-1 V operation and noise figures below 5 , as demonstrated in 130 nm prototypes. These implementations prioritize robustness against process variations in subthreshold regimes, facilitating ULV RF front-ends for wireless sensor networks. Cascode MOSFETs using wide-bandgap materials like and have advanced high-voltage switching in , particularly for (EV) chargers. / cascode devices, combining a low-voltage Si MOSFET with a high-voltage JFET or HEMT, handle 1200 V blocking with switching losses under 50 mW at 100 kHz, offering dv/dt control up to 100 V/ns to suppress in fast chargers. In 650 V cascode configurations, EV onboard chargers achieve efficiencies exceeding 98% at 7.2 kW, surpassing standalone SiC MOSFETs by reducing conduction losses through the cascode's normally-on JFET channel. These structures mitigate gate drive challenges in wide-bandgap tech, enabling compact, high-frequency converters for 800 V EV powertrains. Advancements in scaling have integrated cascodes into 28 nm nodes for s, balancing power and performance in compact dies. A pseudo-differential cascode (LNA) in 28 nm bulk for 60 GHz applications consumes 5 mW at 0.9 V supply, delivering 21 dB and 6.3 dB across a 2 GHz , ideal for low-power wake-up receivers in battery-constrained devices. This scaling exploits thin-gate oxides and multi-metal layers for inductive peaking, achieving input matching below -10 dB while integrating ESD protection, thus supporting dense arrays in smart agriculture and wearables without compromising . As of 2025, enhanced recycling folded-cascode OTAs continue to advance low-power biomedical and applications, achieving high with input-referred noise below 5 nV/√Hz in sub-0.5 V processes.

Analysis and Design

Low-Frequency Two-Port Parameters

The low-frequency two-port parameters of a cascode amplifier are derived using small-signal models that neglect frequency-dependent capacitances and focus on resistive and elements. For (BJT) cascodes, the h-parameters (hybrid parameters) are commonly employed, defined as h_i (), h_r (reverse voltage ratio), h_f (forward current gain), and h_o (output ). These parameters characterize the common-emitter input followed by a output stage. For metal-oxide-semiconductor (MOSFET) cascodes, y-parameters (short-circuit ) are more appropriate due to the high , with y_11 (), y_12 (reverse transadmittance), y_21 (forward transadmittance), and y_22 (output ).

BJT Cascode h-Parameters

The small-signal hybrid-π model is used to derive the h-parameters for the BJT cascode, where the first transistor (Q1) operates in common-emitter mode and the second (Q2) in common-base mode. The collector of Q1 connects directly to the emitter of Q2, providing current buffering with minimal voltage gain in the first stage to minimize the Miller effect at low frequencies. The input impedance h_i is approximately the base-emitter resistance of Q1, as the low input impedance of the common-base Q2 (roughly r_e2, the emitter resistance of Q2) loads the collector of Q1, resulting in near-unity voltage gain for the first stage: h_i \approx r_{\pi 1} = \frac{\beta_1 + 1}{g_{m1}} where β_1 is the current gain of Q1 and g_m1 is its transconductance. This approximation holds when the Early effect is neglected and base resistances are small. The forward current gain h_f is the product of the current gains of the two stages. The common-emitter Q1 provides β_1, while the common-base Q2 provides α_2 ≈ 1 (common-base current gain). Thus, h_f \approx \beta_1 \alpha_2 \approx \beta_1 = \frac{\alpha_1}{1 - \alpha_1} with α_1 the common-base current gain of Q1. Detailed derivation from the hybrid-π model involves solving for i_b / i_c with v_2 = 0, confirming the near-unity contribution from Q2. The reverse voltage gain h_r is negligible due to the isolation of the common-base stage, which presents high reverse impedance: h_r \approx \frac{1}{\beta_2 (1 + g_{m2} R_L)} \ll 1 where β_2 and g_m2 are parameters of Q2, and R_L is the load resistance. This low value enhances stability in cascaded stages. The output admittance h_o is dominated by the output conductance of Q2: h_o \approx \frac{1}{r_{o2}} + \frac{1 + \beta_1}{r_{\pi 1} r_{o1}} but simplifies to h_o ≈ 1/r_o2 when the first stage's contribution is small.

MOSFET Cascode y-Parameters

For the MOSFET cascode, the small-signal model uses voltage-controlled current sources with output resistances, suitable for the common-source input (M1) followed by common-gate output (M2). At low frequencies, gate currents are zero in the ideal model, leading to infinite input impedance. The input admittance y_11 is ideally zero. The reverse transadmittance y_12 ≈ 0 due to high reverse in the cascode structure. The forward transadmittance y_21 is the of M1, as the current generated by M1 passes nearly unattenuated through M2: y_{21} \approx g_{m1} Derivation involves short-circuiting the output (v_2 = 0) and computing i_1 / v_1, where the common-gate M2 exhibits unity current . Including body effect, it becomes g_m1 + g_mb1, but g_mb1 is often small. The output y_22 is enhanced by the cascode: y_{22} \approx \frac{1}{r_{o2} (1 + g_{m2} r_{o1})} reflecting the high output resistance.

Design Guidelines

For unity current gain in the cascode (h_f ≈ β_1 for BJT or y_21 / y_11 ≈ g_{m1} for MOSFET), match the transconductances of the transistors: g_m1 ≈ g_m2 (or β_1 ≈ β_2 for BJT). This ensures the second stage buffers without attenuation, maximizing overall gain while maintaining stability. Biasing should place both transistors in active/saturation regions with equal collector/drain currents for optimal matching.

High-Frequency Considerations

In high-frequency models of cascode amplifiers, parasitic capacitances play a critical role in limiting performance. For bipolar junction transistor (BJT) cascodes, the base-collector capacitance C_{bc} (also denoted C_\mu) and collector-substrate capacitance C_{cs} introduce feedback and loading effects that degrade gain and phase response at elevated frequencies. Similarly, in metal-oxide-semiconductor field-effect transistor (MOSFET) cascodes, the gate-drain capacitance C_{gd} and drain-bulk capacitance C_{db} contribute to Miller multiplication and output pole shifting, necessitating their inclusion in small-signal hybrid-pi or T-models for accurate simulation above the midband range. The transition frequency f_T, a key figure of merit for device speed, is given by f_T = \frac{g_m}{2\pi (C_\pi + C_\mu)} for BJTs and f_T = \frac{g_m}{2\pi (C_{gs} + C_{gd})} for MOSFETs, where g_m is the transconductance, C_\pi (or C_{gs}) is the input capacitance, and the parasitics determine the unity current-gain frequency, often reaching tens of GHz in modern processes. Cascode configurations extend bandwidth compared to single-stage common-emitter or common-source amplifiers by shielding the input transistor's from the , where the effective input capacitance is reduced from C_{gd}(1 + g_m R_L) to approximately C_{gd}. This results in a higher -3 bandwidth f_{-3\text{dB}} \approx \frac{g_m}{2\pi C_L} for the or common-gate output stage, limited primarily by the load capacitance C_L rather than amplified parasitics, enabling operation up to several GHz in broadband designs. In contrast, single-stage amplifiers suffer bandwidth compression due to the full Miller multiplication, often limiting f_{-3\text{dB}} to lower values for the same . To mitigate parasitic impacts in RF cascode design, layout techniques emphasize compact stacking of transistors to minimize interconnect inductances and capacitances, such as interleaving fingers in cascode pairs to reduce and extrinsic parasitics that cause oscillations or . Inductive peaking, where series inductors are added at the or of the cascode , compensates for high-frequency by resonating with parasitic capacitances, extending flat- by up to 1.8 times in UWB LNAs without increasing power consumption. In millimeter-wave integrated circuits, a cascode LNA in 22-nm FD-SOI achieves a minimum of 2.1 dB at 28 GHz with , providing 23.1 dB and 4.8 GHz (23.7–28.5 GHz) for mm-wave applications as of 2022. A broadband cascode LNA in 65-nm achieves a minimum of 2.49 dB at 25.4 GHz with 24.8 dB peak and 17.1 GHz (23.2–40.3 GHz) using transformer-based T-type as of 2024.

References

  1. [1]
    The Cascode Amplifier | Bipolar Junction Transistors
    The cascode amplifier configuration has both wide bandwidth and a moderately high input impedance. The cascode amplifier is combined common-emitter and common- ...
  2. [2]
    Transistor Cascode Topology - MIT
    The cascode topology was invented to solve the Miller effect [1] in triode amplifiers. However, with the invention of the pentode (at right), ...
  3. [3]
    Cascode amplifier - US2786901A - Google Patents
    March 26, 1957 E. K. NELSON cAsconE AMPLIFIER Filed April 2e, 1952 United States Patenti() CASCODE AMPLIFIER ,Edwin Keith Nelson, ;Pico, Calif., assignor to ...
  4. [4]
    [PDF] cascode ≡ a two-transistor configuration formed of a common-emitter
    The cascode is a very useful two-transistor stage that provides the performance of a common-emitter/-source stage with a much smaller Miller effect and much ...
  5. [5]
    [PDF] The Cascode Amplifier
    A cascode is a CE Stage cascaded with a CB Stage. (Historical Note: the cascode amplifier was a cascade of grounded cathode and grounded grid vacuum tube ...
  6. [6]
    [PDF] Cascode Amplifiers by Dennis L. Feucht Two-transistor ...
    The basic cascode amplifier consists of an input common-emitter (CE) configuration ... basic shunt-feedback circuit is shown below (left), and with BJT T ...
  7. [7]
    [PDF] Analysis of the Transistor Cascode Configuration - MIT
    It is believed that the transistorized cascode circuit was first used by S. H. Bowers of S.R.D.E., Christchurch. APPENDIX. DERIVATION OF TRANSISTOR PARAMETERS ...
  8. [8]
    [PDF] H Op Amp History - Analog Devices
    A second development (and one more germane to amplification), was the invention of the three-element triode vacuum tube by Lee De Forest, the "Audion," in 1906.
  9. [9]
    [PDF] Common Base Amplifiers and Cascode Amplifiers
    You can transform the small signal model of the common base by pretending the current source flows into the base and then out to the emitter. Recall that our ...
  10. [10]
    [PDF] Lecture 34: Designing amplifiers, biasing, frequency response Context
    Miller Capacitance of Input Stage. Find the Miller capacitance for Cgd1. Input resistance to common-gate second stage is low → gain across. Cgd1 is small. gd.
  11. [11]
    [PDF] Chapter 10: CASCADED AND CASCODE AMPLIFIERS
    The CE stage, where the Miller Effect could be a problem, is deliberately set up for a low gain to minimize it! • The gain is obtained from the CB output ...
  12. [12]
    [PDF] Lecture 8 Cascode and common source amplifier - KIT ADL
    The themes of this lecture are cascode and common source amplifier. Cascode is a circuit consisting of a MOSFET (the cascode transistor Tcasc) having a ...
  13. [13]
    [PDF] Lecture 8: Current Mirrors
    Low-Voltage Cascode Current Mirror. • M2 and M4 should be sized such that. • V. GS2. = V. GS4. • M1 and M3 biased near edge of saturation. • V. DS1 ≈ VDS3 ≈ ...
  14. [14]
    [PDF] Biasing Techniques for Linear Power Amplifiers - DSpace@MIT
    May 10, 2002 · Power amplifiers with conventional fixed biasing attain their best efficiency when operate at the maximum output power.
  15. [15]
    [PDF] Fully Integrated CMOS Power Amplifier - UC Berkeley EECS
    Dec 6, 2006 · As discussed in Chapter 4, the size and the bias of the cascode transistor will affect the gain, output power and efficiency. Another ...
  16. [16]
    [PDF] Amplifier Input Common-Mode and Output-Swing Limitations
    Amplifier common-mode input range is limited by the input stage's operating voltages, especially for MOSFETs, which are limited by the negative rail and within ...
  17. [17]
    [PDF] Multistage Amplifiers - Analog & Digital Electronics
    This Miller capacitance is C ... A cascode amplifier has a high gain, moderately high input impedance, a high output impedance, and a high bandwidth.
  18. [18]
    [PDF] On the Operation of CMOS Active-Cascode Gain Stage
    As a result, a single-stage cascode amplifier typically exhibits a better power efficiency relative to a Miller-compensated two-stage design, and is widely used ...
  19. [19]
    [PDF] Design of Sub-mW RF CMOS Low-Noise Amplifiers - UBC ECE
    One shortcoming of the cascode topology is that the extra transistor consumes voltage headroom. ... gain, noise, linearity, and power consumption of the amplifier ...Missing: disadvantages | Show results with:disadvantages
  20. [20]
    [PDF] Practical Considerations for Low Noise Amplifier Design - White Paper
    The cascode amplifier is the most versatile of the three topologies. It provides the most stable signal gain over the widest bandwidth with only a slight ...
  21. [21]
    [PDF] N90-21324
    The signal and noise gain of the common- source cascode amplifier appears to offer substantialadvantages in acheiving predicted noise levels. INTRODUCTION.
  22. [22]
    [PDF] ECEN 325 Lab 8: BJT Amplifier Configurations
    BJT Small-Signal AC models​​ BJTs are nonlinear devices, where the collector current is an exponential function of the base-emitter voltage. Typical BJT ...
  23. [23]
    finding the output resistance of bjt folded cascode
    Jun 16, 2018 · I am being asked to find the output resistance of following BJT cascode amplifier, from "Microelectronic Circuits" by Sedra and Smith, 7th edition, problem 8. ...
  24. [24]
    [PDF] Basic BJT Amplifiers
    The output resistance specification is met in the computer simulation. In the. PSpice analysis, the ac beta is 135 and the output resistance is Ro = 176 .
  25. [25]
    [PDF] BJT Amplifiers - Higher Education | Pearson
    4. The r parameter bac is the same as the h parameter hfe. 5. A bypass capacitor in a CE amplifier decreases the voltage gain.
  26. [26]
    None
    Below is a merged summary of BJT Cascode in Audio Power Amplifiers based on Bob Cordell’s *Designing Audio Power Amplifiers* (2011). To retain all information in a dense and organized format, I’ve used tables in CSV-style text blocks where appropriate, followed by a narrative summary for additional context. The response consolidates all segments, avoiding redundancy while preserving details on discrete and integrated implementations, examples, advantages, and URLs.
  27. [27]
    [PDF] Design of Analog CMOS Integrated Circuits - CORE
    Design of Analog CMOS. Integrated Circuits. Behzad Razavi. Professor of Electrical Engineering. University of California, Los Angeles. Boston Burr Ridge, IL ...
  28. [28]
    [PDF] Lecture 15 Multistage FET Amplifiers - Cornell University
    The FET cascode has a large input resistance, a very large output resistance, and a large gain. But it is much better than a CS-CS cascade in terms of the ...
  29. [29]
    A 0.18-$\mu{\hbox {m}}$ Dual-Gate CMOS Device ... - ResearchGate
    In order to verify the model accuracy, a cascode configuration with the proposed dual-gate device is employed in a low-noise amplifier. The dual-gate model is ...
  30. [30]
    (PDF) A dual-gate 60GHz direct up-conversion mixer with active IF ...
    This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs current reuse and double frequency circuits in the RF ...
  31. [31]
    A novel class of complementary folded-cascode opamps for low ...
    Aug 9, 2025 · The circuit of the error amplifier is a self-compensating topology based on the low-voltage complementary folded cascode operational amplifier ...
  32. [32]
    Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements
    Insufficient relevant content. The provided URL (https://ieeexplore.ieee.org/document/951695) points to a page about a "Low supply voltage high-performance CMOS current mirror," but the specific details about the regulated cascode technique, its feedback mechanism, output resistance formula (e.g., r_out ≈ 1/g_m,reg * r_o), or its benefits are not accessible or explicitly detailed in the visible metadata or abstract snippet.
  33. [33]
    Low supply voltage high-performance CMOS current mirror with low ...
    This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be ...
  34. [34]
    A Fully Integrated 1.13 NEF 32-Channel Neural Recording SoC With 12.5 pJ/Pulse IR-UWB Wireless Transmission for Brain Machine Interfaces
    **Summary of Recycling Folded Cascode OTA in Neural Interfaces (Post-2020)**
  35. [35]
    A Fully Integrated 1.13 NEF 32-Channel Neural Recording SoC With ...
    Oct 11, 2023 · The current-recycling folded-cascode OTA is capacitively- coupled with the DC-blocking capacitors Cin, as shown in. Fig. 2. At relatively low frequencies ...
  36. [36]
    US2795694A - Cascode amplifier with signal and a. g. c. voltages ...
    A radio frequency amplifier comprising a pair of electron tubes, the cathode of the first of said tubes being effectively connected to ground at radio ...
  37. [37]
    What is a Cascode Amplifier? - Utmel
    Mar 3, 2021 · In the year 1939, the tern cascode was included in an article written by Roger Wayne Hickman and Frederick Vinton Hunt. The subject at hand is ...
  38. [38]
    The Field-Effect Transistor, August 1972 Popular Electronics - RF Cafe
    Jul 28, 2017 · The dual-gate MOSFET finds its most popular application as the mixer stage in AM, FM, and TV tuners where it provides a convenient means of " ...
  39. [39]
    [PDF] DESIGNING WITH FIELD-EFFECT TRANSISTORS - Bitsavers.org
    The purpose of this book is to aid the electronics circuit designer in the utilization of the field-effect transistor (FET). Since its emergence.
  40. [40]
    [PDF] A Low-Noise Amplifier* - Non-secure http index page
    It is believed that the low-noise cascode circuit can also be adapted to low-pass amplifiers. LI. GROUNDED-CATHODE AMPLIFIERS. For use in the subsequent ...
  41. [41]
    A Low-Power, Low-Noise Recycling Folded-Cascode Operational ...
    We present in this paper a low-noise, low-power CMOS operational transconductance amplifier designed for the preconditioning stage of implantable neural ...
  42. [42]
    A High-Performance, Low-Noise Class-AB Folded-Cascode Op ...
    Sep 25, 2025 · An ultra-low power high gain CMOS OTA for biomedical applications. June 2019 · Analog Integrated Circuits and Signal Processing.
  43. [43]
    https://ieeexplore.ieee.org/document/10536098
  44. [44]
    Broadband Millimeter-Wave 5G Power Amplifier Design in 22 nm ...
    Feb 23, 2022 · Three millimeter-wave (mm-Wave) power amplifiers (PAs) that cover the key 5G FR2 band of 24.25 to 43.5 GHz are designed in two different ...
  45. [45]
    https://efficiencywins.nexperia.com/innovation/gan-fets-why-cascode
  46. [46]
    (PDF) Stacked Strongly Coupled GaN/SiC Cascode Device With ...
    Aug 4, 2025 · The silicon carbide (SiC) mosfet s provide superior properties over conventional silicon power devices with a higher switching speed and lower ...Missing: chargers 2020-
  47. [47]
    GaN FETs: Why cascode? | Efficiency Wins
    Sep 30, 2020 · The obvious answer for our 650 V GaN FETs for high-voltage / high-current / high-power applications was to go with cascode mode.Stable High-Power Operation · Cascode - The Obvious Answer · Dilder Chowdhury
  48. [48]
    A 5 mW 28 nm CMOS Low-Noise Amplifier with Transformer-Based ...
    Oct 31, 2024 · This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s applications using 28 nm CMOS technology.
  49. [49]
    Ultra compact multi-standard low-noise amplifiers in 28 nm CMOS ...
    Nov 2, 2017 · This work presents the design of two compact multi-standard low-noise amplifier (LNA) in a 28 nm low-power bulk CMOS process.
  50. [50]
    [PDF] ECE315 / ECE515 Lecture – 8 Date: 05.09.2016
    Sep 5, 2016 · (a) Calculate small signal gain at low frequencies. (b) What ... Small Signal Model of Cascode: 1 1. m o in g rV. -. 1o r. 2. V. 2 2 m g V.
  51. [51]
    None
    ### Summary of High-Frequency Models for BJT and MOSFET
  52. [52]
    [PDF] Frequency Response - Solayman EWU
    The High-Frequency MOSFET Model Figure 9.6(a) shows the small-signal model of the MOSFET, including the four capacitances Cgs, Cgd, Csb, and Cdb. This model ...
  53. [53]
    https://ieeexplore.ieee.org/document/8906913
  54. [54]
    https://ieeexplore.ieee.org/document/4252923
  55. [55]
    A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications
    **Summary of High-Frequency Considerations for mm-Wave Cascode LNA:**
  56. [56]
    A 23.2-40.3 GHz Low-Noise Amplifier with Transformer-Based T-Type Topology
    - **Title**: A 23.2-40.3 GHz Low-Noise Amplifier with Transformer-Based T-Type Topology