45 nm process
The 45 nm process refers to a generation of semiconductor manufacturing technology that fabricates integrated circuits with transistor gate lengths and other critical features measuring 45 nanometers, enabling approximately twice the transistor density of the prior 65 nm node while reducing power consumption and improving performance.[1] This node marked a pivotal advancement in CMOS (complementary metal-oxide-semiconductor) technology, introduced commercially in 2007, and was adopted by leading foundries to sustain Moore's Law by packing billions of transistors onto chips for applications in processors, mobile devices, and embedded systems.[2] A defining innovation in the 45 nm process was Intel's implementation of high-k metal gate (HKMG) transistors, which replaced traditional silicon dioxide gate dielectrics with hafnium-based high-k materials and polysilicon gates with metal gates, reducing gate leakage by more than five times, boosting drive current by more than 20%, and cutting active power by about 30% compared to 65 nm designs.[1][2] This breakthrough, the first major transistor redesign since the 1960s, allowed Intel to produce the Penryn family of Core 2 processors—such as dual-core models with over 400 million transistors—entering volume production in late 2007 at facilities in Oregon and Arizona.[1][2] Meanwhile, TSMC's 45 nm process emphasized low-power optimization using 193 nm immersion lithography and extreme low-k dielectrics, achieving higher speeds, lower energy use, and greater die yield per wafer, as demonstrated by Qualcomm's first 45 nm 3G chips, which were taped out in 2007.[3][4] The 45 nm node facilitated widespread adoption across the industry, with TSMC enabling designs for mobile and multimedia applications through its generic low-power process, while Intel's HKMG approach set a precedent for subsequent nodes like 32 nm.[3][5] Key challenges overcome included quantum tunneling in thin dielectrics and compatibility with high-temperature manufacturing, addressed via atomic layer deposition and gate-last fabrication techniques.[2] Overall, this process node bridged the transition from planar bulk CMOS to more advanced structures, supporting the proliferation of multi-core CPUs, GPUs, and system-on-chips in the late 2000s.[5]Overview
Definition and Node Characteristics
The 45 nm process node represents a milestone in MOSFET semiconductor fabrication, defined by the International Technology Roadmap for Semiconductors (ITRS) as the generation where the contacted half-pitch of DRAM memory cells measures approximately 45 nm. This metric serves as the primary identifier for the technology node, reflecting the scaling of minimum feature sizes in memory arrays while accommodating variations in logic transistor dimensions.[6] The node emphasized continued dimensional shrinkage to boost integration density and performance, adhering to classical scaling principles where linear dimensions reduce by about 30% per generation to double transistor counts without proportional power increases.[7] The 45 nm process node was introduced for high-volume manufacturing in 2007–2008 by leading manufacturers like Intel, ahead of the ITRS 2005 projection for DRAM half-pitch scaling to 45 nm in 2010, though it aligned with logic scaling goals. Key physical parameters included a typical contacted metal-1 half-pitch of around 45–50 nm for MPU/ASIC interconnect layers and a contacted poly-silicon gate pitch of approximately 120–160 nm. Gate lengths were scaled to 35–40 nm in commercial implementations like Intel's, supporting effective channel control while mitigating short-channel effects through optimized doping profiles. While ITRS provided projections (e.g., 25 nm gate length for 2007), actual commercial processes like Intel's featured gate lengths of 35 nm and transistor densities up to 3.33 million transistors per mm² in logic circuits, demonstrated in representative implementations like multi-core processors. The predominant lithography method was 193 nm argon fluoride (ArF) immersion, which used water as an immersion medium to achieve resolutions below the dry wavelength limit, enabling reliable patterning of critical layers without relying on extreme ultraviolet alternatives.[8][6][9] At the core of the 45 nm node were planar bulk-silicon MOSFETs, with no widespread adoption of multi-gate structures like FinFETs, which emerged in later generations. These transistors featured scaled channel lengths of 35–40 nm to sustain drive currents above 1 mA/µm at supply voltages near 1 V, while equivalent oxide thickness (EOT) was reduced to about 1 nm using high-κ dielectrics as a key enabler for gate stack scaling. Interconnects relied on copper with low-κ dielectrics, achieving metal-1 half-pitches of 45 nm to support overall chip densities exceeding 1 billion transistors in practical dies. This configuration prioritized performance-per-watt improvements, with off-state leakage controlled below 100 nA/µm through halo implants and strain engineering.[10][11]Significance in Semiconductor Scaling
The 45 nm process node played a pivotal role in sustaining Moore's Law by overcoming key scaling barriers encountered at the preceding 65 nm generation, where continued reliance on silicon dioxide (SiO₂) gate oxides resulted in severe challenges. At 65 nm, gate oxide thicknesses had been scaled to approximately 1.2 nm, leading to exponentially increased gate leakage currents on the order of 100 A/cm² at 1 V due to quantum tunneling effects, which compromised device reliability and exacerbated static power dissipation.[12][13] This leakage, combined with rising subthreshold currents from shorter channel lengths, drove up power density, making it difficult to maintain performance gains without excessive heat generation and energy consumption in high-density circuits.[14] Furthermore, achieving the required equivalent oxide thickness (EOT) below 1 nm for capacitive drive current improvement while controlling leakage demanded innovative materials beyond traditional SiO₂.[15] The introduction of the 45 nm node enabled a doubling of transistor density compared to 65 nm, allowing for either smaller die sizes with equivalent functionality or higher integration levels on the same footprint, thereby extending the trajectory of exponential complexity growth.[16] Performance benefits included a 30% improvement in switching speed at iso-power or a 20–30% reduction in active power at iso-performance, achieved through optimized scaling that mitigated the leakage issues of prior nodes.[17] High-κ dielectrics briefly referenced here as a key enabler helped achieve sub-1 nm EOT with significantly lower gate leakage, facilitating these gains without reverting to unfeasibly thin SiO₂ layers.[18] Economically, the 45 nm process marked the widespread adoption of high-volume 300 mm wafer production across the industry, which, despite increased fabrication complexity and wafer costs around $2,000–$5,000 each, yielded a net reduction in cost per transistor through higher yields and density improvements.[19][20] This transition amplified manufacturing efficiency, with transistor costs continuing to decline post-45 nm, albeit at a slower rate than earlier nodes, supporting broader accessibility of advanced computing.[21] In line with International Technology Roadmap for Semiconductors (ITRS) projections from 2005, the 45 nm node featured a contacted metal-1 half-pitch scaling toward 45 nm (projected for 2010), down from approximately 68 nm at the 65 nm node.[22][23] These metrics underscored the node's contribution to dimensional shrinkage, ensuring continued viability of planar CMOS scaling into the late 2000s.Technological Features
High-κ Dielectrics and Metal Gates
In the 45 nm process node, traditional silicon dioxide (SiO₂) gate dielectrics were replaced with high-κ materials, such as hafnium dioxide (HfO₂) or hafnium silicon oxynitride (HfSiON), to maintain capacitance while scaling the equivalent oxide thickness (EOT) to approximately 0.9–1.0 nm.[24][25] Intel pioneered the full high-κ metal gate (HKMG) approach in their 45 nm process, while other manufacturers like TSMC paired high-κ dielectrics with traditional polysilicon gates.[26] These high-κ dielectrics, with relative permittivities (κ) ranging from 4 to 24, allowed for physically thicker layers of 1.5–2 nm, significantly reducing quantum mechanical tunneling and gate leakage currents by factors of 25–1000× compared to SiO₂ or silicon oxynitride (SiON) equivalents at the same EOT.[9][25] This approach addressed the exponential increase in leakage that would occur with direct SiO₂ scaling below 1.2 nm, enabling continued transistor performance improvements without excessive power dissipation.[24] In Intel's HKMG implementation, metal gates—primarily titanium nitride (TiN) with work function tuning for both n-type metal-oxide-semiconductor (NMOS) and p-type (PMOS)—were introduced alongside high-κ dielectrics to eliminate polysilicon depletion effects, which previously added an effective 0.3–0.5 nm to the EOT and reduced drive currents by up to 20%.[27] These metals provided dual work functions near the silicon band edges (around 4.1 eV for NMOS and 5.2 eV for PMOS), resolving Fermi level pinning issues that hindered threshold voltage control in poly-Si gates.[9][25] By replacing doped polysilicon, metal gates improved gate capacitance utilization and enabled better compatibility with high-κ materials, contributing to enhanced short-channel effects management in 45 nm devices.[27] Integration of high-κ dielectrics and metal gates presented several challenges, including the need for a thin interfacial SiON or SiO₂ layer (0.5–1 nm) to promote adhesion, suppress charge trapping, and maintain interface trap densities below 10¹¹ cm⁻² eV⁻¹.[25] These stacks required thermal stability up to 1000–1100°C during dopant activation and silicide formation, with Hf-based materials demonstrating amorphous structures resistant to crystallization-induced defects.[9][25] Compatibility with strained silicon channels was achieved by optimizing deposition processes to minimize stress relaxation, though pMOS threshold voltage shifts of ~0.5 V and interfacial layer re-growth during high-temperature steps remained key hurdles.[27][25] The adoption of high-κ dielectrics and metal gates in the 45 nm process yielded notable performance gains, including a 20% increase in drive current (I_on) at constant off-state leakage compared to prior nodes, alongside subthreshold leakage reduction to below 100 nA/µm.[9] These improvements, with electron and hole mobilities retaining ~90% of universal SiO₂ values at fields of 1 MV/cm, supported higher transistor densities and switching speeds while keeping gate leakage under 0.1 A/cm².[25][24]Lithography and Patterning Methods
The 45 nm process marked a critical transition in semiconductor lithography, where 193 nm ArF excimer lasers served as the primary light source to push optical resolution limits. Immersion lithography, utilizing water as the immersion fluid between the lens and wafer—increasingly adopted by foundries like TSMC—increased the numerical aperture (NA) to 1.35, enabling single-exposure resolutions down to approximately 38 nm half-pitch for dense features.[3] This approach overcame the diffraction constraints of dry lithography, allowing manufacturers to pattern critical layers like gates and contacts without immediately resorting to extreme ultraviolet (EUV) tools. To achieve the full 45 nm half-pitch density required for logic and memory devices, double patterning techniques were essential, effectively doubling feature resolution by splitting patterns into multiple exposures or self-aligned structures. Litho-etch-litho-etch (LELE) involved sequential lithography and etching steps to define complementary patterns, while spacer-defined double patterning (SDDP), also known as self-aligned double patterning (SADP), used sidewall spacers formed on an initial pattern to create finer pitches with better overlay control. These methods were particularly vital for dry 193 nm systems, as adopted by Intel for critical layers, but also complemented immersion setups to extend optical lithography's viability beyond single-exposure limits.[28] Reticle enhancements played a key role in managing diffraction and proximity effects at this node. Phase-shift masks (PSMs), such as alternating or attenuated types, improved image contrast by introducing controlled phase differences in the transmitted light, enhancing resolution for sub-45 nm features. Optical proximity correction (OPC) algorithms adjusted mask patterns to compensate for distortions, ensuring accurate on-wafer reproduction of design intent through techniques like sub-resolution assist features.[29] The adoption of double patterning increased process complexity, adding multiple lithography and etching steps that could reduce yields due to accumulated errors, but it remained more economical than pursuing 157 nm F2 lithography, which was abandoned owing to challenges in vacuum ultraviolet source stability, CaF2 lens costs, and pellicle development. This strategy allowed the 45 nm node to leverage existing 193 nm infrastructure, contributing to higher transistor densities while deferring EUV adoption.[30][31]Transistor and Interconnect Enhancements
In the 45 nm process, transistor performance was enhanced through strain engineering techniques that introduced controlled stress to the silicon channel, boosting carrier mobility without significantly increasing power consumption. For NMOS transistors, tensile strain was applied using stress memorization techniques and high-tensile silicon nitride liners, resulting in electron mobility improvements of 10–20%.[28] For PMOS transistors, compressive strain was achieved using embedded SiGe in the source and drain areas, yielding hole mobility gains of up to 30%.[28] These mobility enhancements, ranging from 10–30% overall, allowed for higher drive currents and faster switching speeds at scaled dimensions, maintaining transistor performance amid shrinking gate lengths.[28] Interconnect improvements in the 45 nm node focused on reducing resistance-capacitance (RC) delays to support increased transistor density and signal speed. Low-κ dielectrics, such as porous carbon-doped oxide (SiOCH) with dielectric constants around 2.1–2.9, were integrated with copper damascene wiring and thin TaN barrier layers to prevent copper diffusion and enhance reliability.[32] This combination achieved a 15% reduction in RC delay compared to prior nodes, mitigating signal propagation losses in denser layouts.[28] The typical gate pitch scaled to 160 nm, paired with contact dimensions of approximately 50 nm, enabled efficient local routing with 3–4 metal layers for front-end connections.[28][32] Power delivery in the 45 nm process addressed challenges from thinner inter-layer dielectrics by incorporating optimized design rules that bolstered electromigration resistance. TaN barriers in copper lines, combined with refined current density limits, ensured robust performance under high loads, preventing void formation and maintaining interconnect integrity over extended operation.[28] These enhancements allowed for reliable power distribution in multi-layer stacks, supporting the overall scaling of logic density.[28]Development and Demonstrations
Early Research Milestones
The International Technology Roadmap for Semiconductors (ITRS) editions from 2001 to 2005 outlined accelerating timelines for semiconductor scaling, with the 2001 version projecting the 45 nm node for high-performance microprocessor production around 2010 based on DRAM half-pitch metrics, while subsequent updates refined this to emphasize urgent needs for advanced materials.[33] By the 2005 ITRS, the 45 nm node was forecasted for initial production in 2010, driven by MPU gate length scaling to approximately 25 nm and the recognition that traditional SiON gate dielectrics would face severe leakage and power limitations at this scale.[22] This edition specifically highlighted high-κ dielectrics as essential for maintaining equivalent oxide thickness below 1 nm while controlling gate tunneling currents, marking a pivotal shift toward alternative gate stack materials to sustain Moore's Law. Early collaborative efforts amplified these roadmap imperatives, notably IBM's 2002 research on fully silicided (FUSI) metal gates as a pathway to replace polysilicon electrodes and achieve tunable work functions for CMOS compatibility at sub-65 nm nodes. This work, presented at the 2002 International Electron Devices Meeting (IEDM), demonstrated FUSI gates with nickel silicide on polysilicon, showing improved threshold voltage control and reduced depletion effects, laying groundwork for integration with high-κ materials in alliance-driven development.[34] Academic institutions contributed foundational studies on high-κ material reliability, with IMEC reporting in 2003 on the thermal and electrical stability of HfSiON dielectrics, which exhibited superior crystallization resistance compared to pure HfO₂, enabling equivalent oxide thicknesses of 1.2 nm with low leakage after 700°C annealing. These findings, detailed in proceedings from the International Workshop on Gate Insulator, underscored HfSiON's potential for 45 nm gate stacks by mitigating interface traps and bias-temperature instabilities through nitrogen incorporation. Advancements in lithography tooling were critical for patterning feasibility, as ASML demonstrated in 2005 the TWINSCAN XT:1700i immersion scanner with 1.2 numerical aperture (NA), achieving 45 nm dense lines and spaces in resist, sufficient for half-pitch resolution in logic and memory production.[35] Complementing this, Nikon and Canon advanced 193 nm dry and immersion tools, with Nikon's NSR-S307E scanner supporting 0.92 NA exposures for 55 nm features transitioning toward 45 nm development, and Canon's FPA-5500iZ4 enabling similar resolutions for 300 mm wafers.[36] The patent landscape reflected maturing integration strategies, exemplified by Intel's 2004 filings on high-κ/metal gate processes, including methods for hafnium-based dielectrics with tantalum or titanium nitride gates to optimize work function and suppress Fermi level pinning. These innovations, building on Intel's IEDM 2004 presentation of 30 nm gate length transistors with HfO₂ and metal electrodes achieving 1.0 V drive currents over 1 mA/μm, provided proprietary pathways for compatible CMOS scaling at 45 nm.[37]Technology Demos by Companies
In 2004, Taiwan Semiconductor Manufacturing Company (TSMC) achieved an early milestone in 45 nm process development by demonstrating a functional 6-transistor SRAM cell measuring 0.296 µm², utilizing planar silicon-on-insulator (SOI) technology and immersion lithography for patterning critical layers. This prototype highlighted TSMC's progress in scaling transistor structures while maintaining static noise margins above 120 mV, paving the way for denser memory integration in logic processes. Building on this, several companies advanced prototypes in 2006, focusing on SRAM cells as key indicators of process maturity due to their sensitivity to lithography resolution and transistor performance. Intel led with the first public demonstration of a 0.346 µm² SRAM cell fabricated on 300 mm wafers, incorporating high-κ dielectrics and metal gates to reduce gate leakage while enabling higher drive currents; this marked a significant shift from traditional polysilicon gates, as detailed in the high-κ and metal gate section. The cell supported operation up to 3.8 GHz in a 153 Mb array, demonstrating yields suitable for high-volume manufacturing potential.[28] Advanced Micro Devices (AMD), collaborating with IBM under their joint development agreement, showcased a 0.370 µm² SRAM cell in April 2006, optimized for SOI substrates to enhance performance in power-sensitive applications. This effort leveraged immersion lithography and strain-enhanced transistors for improved carrier mobility, achieving approximately 15% better SRAM cell performance over prior nodes while ensuring compatibility with AMD's processor architectures.[38][39] Texas Instruments (TI) emphasized applications in analog and mixed-signal circuits with its June 2006 demonstration of a 0.24 µm² SRAM cell, the smallest reported at the time, achieved through immersion (wet) lithography and ultralow-κ dielectrics. This prototype doubled wafer output compared to 65 nm processes and targeted 30% performance gains at lower power, supporting TI's focus on integrated mixed-signal systems.[40] United Microelectronics Corporation (UMC) concluded the year's demos in November 2006 with a 45 nm SRAM cell under 0.25 µm², featuring a 50% size reduction from 65 nm equivalents via 30% design rule scaling and immersion lithography. The emphasis was on cost efficiency, enabling higher transistor density and faster device speeds by 30% without exotic materials, aligning with UMC's foundry model for broad adoption.[41] These demonstrations underscored competitive advancements in cell density and lithography, as summarized below:| Company | Year | SRAM Cell Size (µm²) | Key Features |
|---|---|---|---|
| TSMC | 2004 | 0.296 | Planar-SOI, immersion lithography |
| Intel | 2006 | 0.346 | High-κ + metal gate, 300 mm wafers |
| AMD (w/ IBM) | 2006 | 0.370 | SOI compatibility, strain enhancement |
| TI | 2006 | 0.24 | Wet lithography for analog/mixed-signal |
| UMC | 2006 | <0.25 | Cost-focused design rule shrink |