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Multiple patterning

Multiple patterning is a set of advanced photolithography techniques employed in semiconductor manufacturing to produce integrated circuit features with dimensions below the resolution limit of conventional single-exposure lithography, achieved by overlaying multiple patterns or using self-aligned processes to multiply pitch and density.^[1]^[2] These methods enable the creation of denser, smaller structures essential for scaling down transistor sizes and enhancing device performance in modern electronics.^[3] By dividing complex patterns into simpler sub-patterns exposed sequentially or through spacer-based deposition, multiple patterning addresses the physical constraints of light wavelength and optics in fabricating chips at nodes from 14 nm down to 3 nm and beyond.^[4] Developed as an interim solution during the transition from deep ultraviolet (DUV) lithography to extreme ultraviolet (EUV) systems, multiple patterning emerged in the mid-2000s to extend the viability of existing 193 nm immersion tools for sub-10 nm features, allowing continued Moore's Law scaling without immediate full adoption of costlier EUV infrastructure.^[1] It has been pivotal in producing high-volume memory and logic chips, such as those used in smartphones and data centers, by improving feature density and reducing overall manufacturing costs through optimized pattern transfer.^[2] The technique's evolution reflects ongoing innovations in process control, where process window analysis helps split layouts to maximize printability and yield.^[3] Key variants include litho-etch-litho-etch (LELE) double patterning, which uses two separate exposures and etches to double line density, and self-aligned double patterning (SADP), a spacer-based method that forms patterns via conformal deposition and selective etching for precise pitch multiplication without relying on perfect overlay alignment.^[1]^[2] More advanced approaches like self-aligned quadruple patterning (SAQP) further quadruple density using one lithography step followed by multiple spacer depositions and etches, enabling features as small as 7 nm half-pitch while minimizing edge placement errors.^[2]^[4] These techniques are often combined with optical proximity correction (OPC) and multi-color patterning to handle complex topologies, such as odd-circle graphs in metal layers.^[3] Despite its effectiveness, multiple patterning introduces significant challenges, including overlay misalignment between exposures that can degrade electrical performance, increased process complexity with multiple etch and deposition steps, and higher costs from extended cycle times compared to single patterning.^[1]^[4] Stochastic defects and edge placement errors remain concerns at aggressive nodes, necessitating advanced metrology and process window optimization for production readiness.^[3] Looking ahead, while high-numerical-aperture EUV promises to reduce reliance on multi-patterning by enabling single-exposure printing at 3 nm pitches, hybrid approaches integrating multiple patterning with EUV will likely persist for vias, cuts, and high-density layers through the 2 nm era.^[4]

Introduction to Lithography Challenges

Resolution Limits in Optical Lithography

The resolution in optical lithography is fundamentally governed by the Rayleigh criterion, which defines the minimum resolvable feature size, or critical dimension (CD), as R = k_1 \frac{\lambda}{NA}, where \lambda is the wavelength of the illuminating light, NA is the numerical aperture of the projection optics, and k_1 is a process-dependent factor that accounts for the specifics of the imaging system, mask, and resist.^[5] This equation highlights the three primary levers for improving resolution: reducing \lambda, increasing NA, and minimizing k_1. In practice, k_1 values for advanced semiconductor nodes typically range from 0.25 to 0.3, reflecting optimizations in illumination schemes, mask design, and computational lithography techniques.^[6] Diffraction imposes a physical limit on optical lithography, preventing the faithful reproduction of features smaller than approximately \lambda/2 in a single exposure without significant distortion, as the wave nature of light causes interference patterns that blur fine details.^[7] This diffraction barrier arises from the finite aperture of the optics, which filters out higher spatial frequencies necessary for sharp imaging of sub-wavelength structures, leading to aerial image contrast loss and pattern fidelity degradation.^[8] Historically, 193 nm argon fluoride (ArF) immersion lithography emerged as the industry standard for scaling beyond the 45 nm node, enabling production at 22 nm and 14 nm technology nodes through high-NA optics (up to 1.35) and resolution enhancement techniques, but it encounters severe challenges for sub-10 nm features due to the fixed \lambda and diminishing returns on NA increases.^[9] Further reductions in k_1 below 0.25 are theoretically constrained by the physics of coherent imaging limits, and in practice, they introduce excessive defects such as stochastic noise and pattern collapse from poor image contrast.^[5] At low k_1 values, optical proximity effects (OPE) become pronounced, exacerbating issues like line-edge roughness (LER), where random variations in the edge profile of printed features arise from reduced aerial image contrast and photon shot noise in the resist.^[10] LER, typically quantified as the standard deviation of edge position (often 2-5 nm at advanced nodes), degrades device performance by increasing variability in transistor dimensions and leakage currents, making single-exposure printing untenable for sub-10 nm scales.^[11] These limits have driven the adoption of multiple patterning strategies to effectively halve the effective k_1 without violating single-exposure physics.

Need for Multiple Patterning

Multiple patterning refers to a set of lithographic techniques that employ multiple sequential exposures and etching steps to form a single final pattern on a semiconductor wafer, thereby surpassing the resolution limits of single-exposure optical lithography by effectively lowering the process factor k1 in the Rayleigh criterion for resolution.^[12]^[13] Adopting multiple patterning requires careful decomposition of the integrated circuit layout into separate masks, each handling a portion of the overall pattern, along with stringent control of alignment tolerances to ensure precise overlay between layers. For advanced nodes such as 5nm, overlay errors must be maintained below 2nm to avoid defects that could compromise device performance.^[14]^[15] This approach enables the fabrication of features with half-pitches as small as 10-20nm using existing 193nm immersion lithography tools, bridging the gap until the widespread availability of extreme ultraviolet (EUV) lithography and thereby sustaining the scaling trajectory of Moore's Law in the pre-EUV era.^[12]^[16] Intel first commercially adopted multiple patterning at the 45 nm node in 2008, with significant implementation at the 22 nm node around 2011, particularly for metal layers requiring tight pitches and complex layouts, and broader industry adoption following for 20 nm processes.^[17]^[18]^[13] However, these techniques introduce significant tradeoffs, including heightened process complexity from additional lithography and etch cycles, elevated manufacturing costs due to more masks and steps, and increased risks of defects from overlay variations and pattern interactions compared to single-patterning methods.^[12]^[19]

Situations Requiring Multiple Patterning

Sub-Resolution Pitch Challenges

In optical lithography, sub-resolution pitch refers to the scenario where the pitch of features, defined as the distance between repeating elements such as lines in a grating, falls below twice the resolution limit of the system, causing interference fringes from adjacent features to overlap and degrade pattern fidelity.^[20] This limitation arises from the fundamental Rayleigh criterion, which sets the minimum resolvable half-pitch based on wavelength, numerical aperture, and process factor.^[20] As a result, single-exposure patterning fails to produce distinct features, necessitating multiple patterning techniques to achieve the required density. A prominent example occurs in one-dimensional grating patterns, such as those in metal interconnect layers of advanced logic devices, where attempting a single exposure at pitches below 40 nm leads to line merging and loss of critical dimensions.^[20] In these cases, uniform dense lines intended for sub-20 nm half-pitches cannot be resolved without splitting the pattern across multiple masks, as the overlapping diffraction orders prevent clean aerial image formation.^[12] The pitch doubling concept addresses this by decomposing a coarse, resolvable pattern into two or more offset finer patterns, each exposed and etched separately, effectively halving the pitch per step.^[20] This approach, foundational to litho-etch-litho-etch (LELE) double patterning, enables denser arrays while staying within the resolution capabilities of immersion lithography tools.^[21] Mathematically, multiple patterning with n exposures can reduce the effective pitch by a factor of n (for binary splitting in LELE), allowing sub-10 nm half-pitches from initial patterns at 64 nm or larger; however, overlay errors accumulate across steps, propagating as \sqrt{n} times the single-exposure error, which demands stringent control such as an overlay budget where the standard deviation \sigma_{\text{overlay}} < \frac{\text{half-pitch}}{6} to maintain edge placement accuracy below 10% of the feature size.^[20]^[22] Misalignment in these processes particularly exacerbates bridge defects in dense linear arrays, where adjacent lines unintentionally connect due to overlay shifts exceeding 5-10% of the pitch, reducing yield in critical layers like gates or contacts.^[20] Such defects are amplified in repetitive 1D structures, requiring advanced metrology and correction schemes to mitigate stochastic and systematic errors.^[20]

Two-Dimensional Patterning Issues

In optical lithography, two-dimensional (2D) patterns encounter significant distortions due to diffraction effects during single-exposure printing, particularly as feature sizes approach the diffraction limit. Sharp corners in irregular 2D shapes, such as those found in logic gates or interconnects, tend to round off because high spatial frequency components required for precise edges are lost in the diffraction process, leading to blurred or softened contours in the resist image.^[23] This rounding degrades pattern fidelity and can compromise device performance by altering critical dimensions and electrical properties.^[24] A key challenge in 2D patterning is the tradeoff between line tip extension and overall linewidth control. To elongate line tips and mitigate end-shortening caused by diffraction, optical proximity corrections (OPC) often require widening the line body elsewhere on the mask, which violates design rules for uniform linewidths and increases manufacturing variability.^[25] At low k1 values, this issue intensifies, requiring significant OPC that can widen linewidths elsewhere. In contact and via arrays, these diffraction-induced distortions manifest as circular design holes printing as elliptical shapes, with elongation often favoring one axis due to asymmetric aerial image formation.^[23] This ellipticity reduces contact area and can lead to yield losses in interconnect layers. Illumination source optimization further complicates 2D patterning with mixed orientations. Dipole sources enhance resolution for features aligned perpendicular to the pole orientation (e.g., horizontal lines with a vertical dipole), but they underperform for orthogonal features, necessitating separate exposures.^[26] Annular sources provide more isotropic illumination suitable for random 2D layouts, yet they offer inferior contrast and resolution compared to dipole for unidirectional patterns, limiting their effectiveness in hybrid orientations without multiple patterning.^[26]

Complex Layouts and Multi-Pitch Patterns

Complex layouts in multiple patterning lithography often involve regions with varying feature densities or pitches, which cannot be adequately addressed by uniform single- or double-patterning approaches due to the inherent limitations of optical resolution and process uniformity. In such scenarios, even minor variations in pitch across a layout can lead to significant challenges in mask decomposition, as these irregularities disrupt the regular alternation required for color assignment in double patterning. This results in color conflicts, where features that should be assigned to separate masks violate spacing rules, necessitating additional masks or layout modifications to resolve the incompatibilities.^[27] Slight deviations from the ideal two-beam interference conditions in grating structures further complicate patterning, as small pitch variations amplify optical proximity effects (OPE), leading to enhanced linewidth variations and edge distortions that degrade pattern fidelity. For instance, in dense gratings, non-uniform pitches cause asymmetric diffraction and increased scattering, exacerbating CD through-pitch variations beyond what uniform pitch splitting can correct. Additionally, layouts containing both horizontal and vertical features demand tailored illumination strategies; horizontal lines benefit from vertical dipole illumination to optimize contrast, while vertical lines require horizontal dipole setups, often mandating decomposition into separate masks to align with these orientation-specific source conditions. A representative example of these challenges arises in contact hole arrays with varying sizes or irregular arrangements, where standard double patterning fails to achieve sufficient resolution and uniformity, requiring quadruple patterning to define precise positions and dimensions. In such cases, self-aligned quadruple patterning processes are employed to multiply hole patterns from a coarser pre-pattern, enabling sub-20 nm half-pitches while accommodating size variations that would otherwise cause overlay errors or incomplete etching. The decomposition of these complex layouts is fundamentally modeled as a graph coloring problem, where features are vertices and spacing constraints form edges; odd-length cycles in the conflict graph necessitate more than two colors (masks), rendering the problem NP-hard and requiring heuristic algorithms for practical resolution.^[28]

Decomposition-Based Techniques

Pitch Splitting

Pitch splitting is a decomposition-based multiple patterning technique used in optical lithography to achieve feature densities beyond the single-exposure resolution limit, particularly for one-dimensional periodic structures like dense line arrays. This method addresses sub-resolution pitch challenges by dividing a dense layout into multiple, sparser masks that can be resolved individually with conventional immersion lithography tools.^[12] The core process flow, known as litho-etch-litho-etch (LELE), begins with decomposing the target layout into alternating subsets, such as odd and even lines, to create two independent masks with doubled pitch. The first mask is exposed and etched into the substrate, forming initial features; then, a second photoresist layer is applied, the second mask is exposed and aligned to the first pattern, and the adjacent features are etched. Finally, end-to-end trimming steps are performed using additional lithography and etch processes to connect the split segments and define precise line lengths, ensuring a continuous final pattern without gaps or overlaps.^[12] Variants of pitch splitting extend this approach for finer resolutions. Double patterning halves the effective pitch by using two LELE steps, suitable for pitches around 40 nm at the 7 nm node. Quadruple patterning further splits the layout into four masks via two sequential double patterning cycles (LELELELE), achieving quarter-pitch densities for even tighter features, though at increased complexity.^[12] A primary challenge in pitch splitting is alignment, where precise overlay control between successive exposures is critical to avoid bridging or necking defects. For the 7 nm node, overlay must be maintained to within 2 nm to ensure reliable pattern fidelity and device performance.^[19] Pitch splitting finds primary application in patterning metal lines within the backend-of-line (BEOL) interconnects, where regular, dense wiring requires high fidelity at sub-20 nm pitches. Historically, Intel first implemented double pitch splitting at the 22 nm node in 2011 to enable 90 nm pitch metal layers supporting complex 2D routing.^[29] In terms of implementation, pitch splitting roughly doubles the number of masks and process steps compared to single patterning, significantly elevating manufacturing costs due to additional lithography and etch operations.^[12]

Line Cutting

Line cutting is a decomposition-based multiple patterning technique that addresses the challenges of fabricating complex two-dimensional (2D) patterns at advanced nodes by first creating continuous lines and then selectively segmenting them. The process begins with patterning long, parallel lines using a primary lithography step, often with a relaxed pitch that exceeds the resolution limit of the tool, allowing for higher fidelity in line formation. A secondary lithography exposure then defines narrow cuts at precise intersections, etching away portions of the lines to create the required discontinuities and shapes. This two-step approach, sometimes enhanced with complementary polarity exposures to optimize cut placement, enables the realization of intricate features without the need for full 2D decomposition in the initial patterning stage.^[30] One key advantage of line cutting is its ability to reduce the complexity associated with 2D pattern decomposition, as the primary lines can be formed with fewer overlay constraints, and precision is focused solely on the cut locations. Overlay errors are thus localized to these cuts, simplifying alignment and improving overall process yield compared to traditional multi-exposure methods for dense 2D layouts. The cuts themselves are typically 10-20 nm wide, achieved using deep ultraviolet (DUV) immersion lithography or emerging extreme ultraviolet (EUV) tools to ensure sub-20 nm precision at pitches down to 40 nm.^[30] This technique is particularly beneficial for simplifying complex layouts, such as those with irregular pitches or dense interconnects, by converting them into unidirectional lines prior to segmentation. Practical applications of line cutting include gate cuts in FinFET transistors, where continuous gate lines are segmented to isolate individual devices, and via cuts in back-end-of-line (BEOL) interconnects to define precise contact points without bridging adjacent metals. However, defect risks arise from process variations, such as line edge roughness (LER), which can result in incomplete cuts and lead to electrical shorts between features, potentially causing yield loss in high-density regions.^[12] Line cutting gained significant adoption in industry, notably as a core element in TSMC's 7 nm process node for patterning the M0 and M1 metal layers, where self-aligned double patterning (SADP) forms the initial lines and a dedicated cut mask handles segmentation to achieve the required densities.^[12]

Self-Aligned Techniques

Sidewall Image Transfer and Basic SADP

Sidewall image transfer (SIT) and basic self-aligned double patterning (SADP) represent a pioneering self-aligned approach to pitch multiplication in optical lithography, enabling sub-resolution features without requiring multiple lithographic exposures. The process initiates with the lithographic definition and etching of sacrificial mandrels, or core patterns, on a substrate, typically spaced at the resolution limit of the lithography tool. A thin conformal film, such as silicon dioxide or silicon nitride, is then deposited via chemical vapor deposition, uniformly coating the mandrels and exposing the substrate between them.^[31] An anisotropic reactive ion etch is subsequently applied to remove the deposited film from horizontal surfaces, resulting in sidewall spacers that remain adhered to the vertical edges of the mandrels; this etch-back step effectively doubles the pattern density by creating features at half the original pitch. The mandrels are then selectively removed, and the spacer-defined pattern is transferred to the substrate through a final directional etch, where the spacers serve as a hard mask to define the ultimate features. This transfer leverages the precise geometry of the spacers to replicate high-fidelity edges, as first demonstrated in early edge-defined grating fabrication.^[31] The self-aligned mechanism of SADP inherently minimizes overlay errors by eliminating the need for secondary lithographic alignment, achieving sub-nanometer precision in advanced nodes—often less than 1 nm—compared to traditional double patterning methods that suffer from exposure-to-exposure misalignment. This advantage stems from the conformal deposition and etch processes, which position spacers relative to the core pattern without additional masking steps. Unlike pitch splitting, which relies on non-self-aligned dual exposures, basic SADP uses a single lithographic print for the mandrels, reducing sensitivity to tool overlay variations.^[32] In practice, basic SADP has been widely adopted for one-dimensional structures in logic devices, such as fin patterning in 14 nm FinFET transistors, where it enables uniform, high-aspect-ratio features at pitches around 40-50 nm. For instance, Intel's 14 nm process employed SADP for critical gate and fin layers to achieve reliable density scaling. However, the technique is limited to highly regular, unidirectional arrays, as the fixed positioning of spacers relative to mandrels complicates accommodation of two-dimensional or multi-pitch layouts, often requiring additional trimming or cuts that increase complexity.^[32]^[33] The pitch multiplication is mathematically expressed as an effective pitch P_{\text{effective}} = \frac{P_{\text{original}}}{2}, where P_{\text{original}} is the mandrel pitch; the final critical dimension is primarily dictated by the thickness of the deposited spacer film, which must be precisely controlled during deposition to ensure uniformity across the wafer.^[31]

Spacer-Is-Dielectric Double Patterning (SID SADP)

Spacer-Is-Dielectric Double Patterning (SID SADP) represents an advanced variant of self-aligned double patterning (SADP) tailored for enhanced compatibility with two-dimensional layouts and reduced defectivity in semiconductor manufacturing. In this technique, dielectric materials serve as the final spacers that define spaces between patterned features, contrasting with traditional SADP approaches that rely on sacrificial spacers requiring removal. This configuration allows for greater flexibility in patterning complex, non-periodic structures at sub-20 nm pitches, making it suitable for interconnects and memory arrays where precise control over line widths and spaces is critical. By leveraging the dielectric spacers directly, SID SADP minimizes overlay errors inherent in litho-etch-litho-etch (LELE) methods, achieving self-alignment through sidewall deposition and etching processes.^[34] The core advantage of SID SADP lies in its use of low-k dielectric spacers, which replace higher-stress sacrificial materials like amorphous carbon or silicon, thereby reducing film stress and improving structural integrity during integration. These low-k materials, often with dielectric constants below 3.0, also enhance gap fill in subsequent metallization steps by providing better conformal coverage and lower capacitance in back-end-of-line (BEOL) layers. Additionally, the dielectric nature of the spacers offers superior etch selectivity during pattern transfer, enabling cleaner delineation of features without residue or bridging defects that plague sacrificial spacer flows. For instance, in contact layers, SID SADP facilitates hole shrinking by depositing thin dielectric liners inside pre-patterned vias, reducing critical dimensions by up to 20% while maintaining sidewall uniformity.^[35]^[36] The process flow for SID SADP begins with mandrel formation, where a core (mandrel) mask patterns initial features—typically wider lines or trenches—onto a hard mask layer using lithography and etch. A conformal low-k dielectric film, such as silicon oxycarbide, is then deposited via chemical vapor deposition to wrap the mandrels uniformly, forming spacers of controlled thickness equal to half the target pitch. Anisotropic etching follows to remove excess dielectric from horizontal surfaces, leaving sidewall spacers intact. The mandrels are selectively pulled via wet or dry etch, exposing the underlying substrate where the spacers now define the dielectric spaces. Finally, pattern transfer etches the target layer (e.g., oxide or metal) using the spacers as a hard mask, followed by spacer removal or retention depending on the integration scheme. This sequence ensures pitch doubling with minimal masks, typically requiring only a mandrel mask and a block mask for trimming non-linear features.^[37] To extend SID SADP to two-dimensional patterns, angled deposition techniques are employed during spacer formation, enabling the creation of triangular or honeycomb arrays by shadowing effects that selectively deposit material on sidewalls. This approach is particularly effective for dense, hexagonal layouts, as seen in DRAM capacitor patterning, where it triples density compared to single patterning while avoiding cuts in periodic regions. Samsung used self-aligned double patterning (SADP) for honeycomb-structured capacitor holes in its 20 nm DRAM node, achieving an effective pitch of around 26 nm and improving cell capacitance by 21% relative to prior generations. Overall, these enhancements position SID SADP as a bridge to extreme ultraviolet (EUV) lithography, supporting scaling to 16 nm pitches in metal lines with reduced defect densities below 0.1/cm².^[38]^[39]

Self-Aligned Quadruple Patterning (SAQP)

Self-aligned quadruple patterning (SAQP) extends self-aligned double patterning (SADP) by performing two successive spacer deposition and etching cycles, enabling a fourfold pitch reduction from the initial lithographic pattern. The process begins with a mandrel patterned via 193 nm immersion lithography at a relatively coarse pitch, such as 90 nm, followed by conformal deposition of silicon dioxide spacers using atomic layer deposition (ALD). Anisotropic etching with fluorine-based plasma defines the first set of sidewalls, and the mandrel is selectively removed using oxygen plasma. An intermediate trimming step, typically involving dilute hydrofluoric acid cleaning, refines the features to mitigate any asymmetry before the second spacer deposition and etching cycle, which uses similar ALD and plasma etch steps but with chlorine-based mandrel removal. The resulting quadruple pattern is then transferred into underlying layers like silicon nitride pads and bulk silicon via reactive ion etching.^[40] This iterative approach achieves a density multiplication factor of 4x, dividing the original pitch by four to pattern ultra-fine features critical for advanced nodes, such as fins at 18–28 nm pitch in 5 nm processes or gates approaching 3 nm dimensions. For instance, in high-density fin arrays, SAQP can produce fin top critical dimensions (CD) of about 7 nm with heights up to 115 nm, far beyond single-exposure limits of deep ultraviolet lithography.^[40] Key challenges in SAQP include cumulative spacer asymmetry from non-conformal deposition or etching, which induces pitch walking—non-uniform spacing that degrades overlay—and demands exceptional CD control, often targeting sub-1 nm uniformity (3σ) for critical dimensions and pitch walk. Achieving this requires precise process modeling and metrology to minimize line edge roughness (around 2.2 nm) and line width roughness (1.2 nm), as deviations amplify across the multi-step sequence.^[41]^[40] Intel employed SAQP for active patterns, including fin formation, in its 10 nm logic technology—equivalent to industry 7 nm scaling—with a 34 nm fin pitch and 7 nm fin width, enabling third-generation FinFETs in high-performance and low-power applications without initial EUV reliance.^[42] Variants of SAQP incorporate multi-spacer reduction through additional deposition-etch iterations, achieving greater than 4x density multiplication, such as in self-aligned octuple patterning (SAOP) for sub-10 nm nodes.^[43] Overall, SAQP proved essential for sub-7 nm feature patterning in the pre-full EUV era, supporting dense 1D structures like fins before EUV maturity reduced multi-patterning complexity.^[12]

Advanced and Hybrid Methods

Directed Self-Assembly (DSA)

Directed self-assembly (DSA) leverages the phase separation of block copolymers (BCPs) to form ordered nanoscale domains, such as cylinders or spheres, which serve as templates for high-resolution patterning in semiconductor manufacturing. This bottom-up approach is guided by top-down lithographic pre-patterns to achieve long-range order and precise placement, enabling features beyond the resolution limits of conventional lithography without requiring multiple exposures. The self-assembly is driven by the Flory-Huggins interaction parameter (χ), which quantifies the incompatibility between polymer blocks, promoting microphase separation into thermodynamically stable morphologies like cylindrical domains suitable for via patterning.^[44]^[45] The DSA process primarily employs two directing strategies: chemoepitaxy and graphoepitaxy. In chemoepitaxy, chemical pre-patterns on the substrate, such as neutral and preferential regions created via techniques like LiNe or ULST flows, induce selective wetting of BCP blocks to align domains perpendicularly or in-plane. Graphoepitaxy, conversely, uses topographic templates like trenches or posts fabricated by 193 nm lithography to confine and orient the BCP film, promoting epitaxial growth along the guiding features. These methods allow integration with existing immersion lithography tools, where the pre-pattern defines coarse layout and the BCP multiplies density through natural domain spacing.^[44]^[45] DSA achieves sub-10 nm feature sizes and pitch multiplication factors exceeding 10, such as 9× for hexagonal hole arrays at 30 nm pitch, enabling dense periodic structures unattainable by direct patterning. In logic devices, it is applied to via and contact arrays, improving local critical dimension uniformity (LCDU) from 1.71 nm to 1.41 nm by rectifying lithographic imperfections. For memory, DSA supports hole patterning in DRAM, reducing defects in capacitor arrays and enhancing pattern fidelity at advanced nodes like 7 nm FinFETs.^[45] Key challenges include high defectivity, with current densities around 10 defects/cm²—far above the <1/cm² target for production—arising from dislocations due to phase misalignment or bridging between domains, which require optimized annealing to mitigate. Integration with 193 nm pre-patterns demands precise control of surface energy and thickness to avoid misalignment, while compatibility with extreme ultraviolet (EUV) lithography adds complexity in material selectivity. In 2025, Intel researchers demonstrated hybrid DSA-EUV for 3 nm and beyond nodes, using DSA to rectify line/space patterns at 24 nm pitch, reducing line edge roughness (LER) to 1.70 nm and line width roughness (LWR) to 1.40 nm, paving the way for dose-efficient sub-10 nm scaling. IMEC has also advanced hybrid DSA-EUV pilots in this area.^[45]

Other Specialized Techniques

Self-aligned triple patterning (SATP) combines elements of litho-etch-litho-etch (LELE) processes with spacer-based self-alignment to achieve odd-multiple patterning densities, offering reduced overlay sensitivity compared to traditional triple patterning for features down to sub-15 nm half-pitch. This hybrid approach typically involves an initial mandrel patterning followed by spacer deposition and selective etching to form three distinct lines from two masks, enabling quasi-two-dimensional design flexibility in advanced nodes.^[46] Tilted ion implantation (TII) defines sub-lithographic patterns by directing ions at an oblique angle into a masking layer, creating shadowed regions that enhance etch selectivity without requiring additional lithography steps.^[47] The technique exploits ion damage to accelerate etching in exposed areas, allowing features smaller than the original mask—such as lines or vias at half the pre-existing pitch—to be formed cost-effectively, with demonstrated resolution below 20 nm using argon ions on silicon dioxide layers.^[48] In display technology, TII facilitates fine patterning of thin-film transistor arrays in active-matrix liquid crystal displays (AMLCDs) and organic light-emitting diode (OLED) panels, where it enables precise doping and sidewall definition to improve pixel density and uniformity.^[49] Complementary polarity exposures reduce mask count in line-cutting by using positive and negative tone resists in tandem, where one exposure defines broad areas to protect and the other removes unwanted segments, effectively combining multiple cuts into two aligned patterns. This method is particularly advantageous for dense interconnects, as it minimizes overlay errors associated with numerous individual cut masks, achieving up to 50% fewer exposures while maintaining edge placement accuracy in 193 nm immersion lithography extensions. Self-aligned blocking, also known as self-aligned cutting, employs deposited blockers or local masks formed via selective deposition to terminate lines and prevent over-etching in multi-patterned arrays, ensuring electrical isolation without dedicated trim masks for each endpoint.^[50] The process leverages material selectivity—such as carbon-based blockers on metal lines—to create self-registering barriers, reducing mask complexity and edge placement error budgets in sub-40 nm pitches.^[51] As of 2025, machine learning-assisted pattern segmentation, exemplified by Siemens' ML-SRPP (Machine Learning Statistics Risk Pattern Predictor), optimizes these specialized techniques by predicting defect risks and decomposing layouts into viable multi-pattern segments, enhancing yield in hybrid flows with up to 20% improved critical dimension control.

Implementation Considerations

Costs and Mask Requirements

Multiple patterning techniques substantially elevate mask requirements compared to single patterning, typically demanding 2 to 4 masks per affected layer to achieve sub-resolution features through sequential exposures and etches. This escalation arises because each patterning step—such as in double patterning (LELE: litho-etch-litho-etch) or self-aligned quadruple patterning (SAQP)—requires dedicated masks for distinct subsets of the layout, preventing interference from diffraction limits. For advanced nodes like TSMC's 5 nm process, total mask counts surpass 80 layers, a figure reduced from a potential 115 through EUV integration but still reflecting the multiplicative impact of multiple patterning on non-EUV layers.^[19]^[52] Mask fabrication costs form a critical economic barrier, with individual advanced masks priced at $100,000 to over $1 million due to intricate patterning and materials like those for ArF immersion or EUV. Full mask sets for a single chip design at leading-edge nodes thus exceed $10 million, and multiple patterning amplifies this by 2-4 times per layer, contributing 20-50% to overall wafer processing costs through added fabrication, inspection, and alignment expenses. Published data from TSMC illustrates this: their 7 nm multiple patterning flow incurs mask set costs of approximately $15 million, roughly 3 times the $5 million for 16/14 nm nodes, driven by triple and quadruple patterning in metal and contact layers.^[53]^[54]^[55] Layout decomposition into multiple masks imposes stringent design rule adjustments, including widened minimum spacings (often 1.5-2x single-patterning pitches) to enable conflict-free assignment of features to masks. Coloring conflicts emerge when odd-cycle graphs in the layout prevent bipartite or tripartite decomposition without violations, potentially requiring feature splitting, dummy fills, or rerouting to resolve, which complicates physical design flows and increases turn-around time.^[56]^[57] Alignment precision across masks is addressed through model-based optical proximity correction (OPC), which simulates multi-exposure interactions to refine mask contours, minimizing overlay errors and process variations in critical layers.^[58]

Productivity and Tooling

Multiple patterning techniques in semiconductor manufacturing involve multiple lithography and etch cycles per layer to achieve sub-20 nm feature sizes, typically ranging from 1 to 4 cycles depending on the complexity of the pattern. For instance, litho-etch-litho-etch (LELE) double patterning requires two full lithography-etch cycles, while self-aligned quadruple patterning (SAQP) employs a single initial lithography step followed by two cycles of spacer deposition and selective etching to quadruple the pattern density.^[12]^[59] These additional cycles increase tool demands, with SAQP often requiring 2-3 specialized tools per cycle for conformal deposition, anisotropic etching, and trimming to ensure precise pitch multiplication without defects. High-numerical-aperture (high-NA) immersion scanners, such as the ASML TWINSCAN NXT:2050i with 1.35 NA, are essential for these processes, providing the resolution needed for advanced logic and memory nodes while supporting 300 mm wafer production. By 2025, hybrid EUV-DUV lithography tools have emerged to optimize multiple patterning, combining deep ultraviolet (DUV) immersion for less critical layers with extreme ultraviolet (EUV) for high-resolution steps, thereby reducing overall cycle times in hybrid flows.^[60]^[61] Wafer throughput on these immersion scanners reaches approximately 295 wafers per hour (wph), but multiple patterning effectively halves this rate for double patterning and further reduces it for quadruple schemes due to repeated exposures and processing. For example, quadruple patterning at the 7 nm node can demand up to four times the lithography exposures of single patterning, potentially requiring fourfold the scanner capacity—such as 24 tools for multi-pass flows versus 6 for single-exposure equivalents—to sustain fab output. Productivity enhancements include parallel wafer processing in multi-chamber tools to handle simultaneous cycles and inline metrology systems for real-time overlay and critical dimension monitoring, which minimize downtime and enable faster yield ramps.^[60]^[4]

Unique Challenges in Multiple Patterning

One of the primary technical difficulties in multiple patterning arises from overlay and critical dimension (CD) errors, which propagate cumulatively across multiple litho-etch steps, exacerbating edge placement errors (EPE) and line edge roughness (LER). In litho-etch-litho-etch (LELE) configurations, for instance, overlay inaccuracies entangle with CD variations and stochastic effects, leading to amplified local and global errors that can dominate the EPE budget in logic devices. Studies indicate that even a 1 nm overlay error can effectively double the LER impact in subsequent patterning steps due to this propagation, particularly in dual-layer processes where random CD fluctuations add to systematic misalignments.^[62]^[63] Defect types unique to multiple patterning include stochastic noise in spacer formation and bridging during cut steps, both of which stem from resist variability and process instabilities. Stochastic noise, driven by shot noise and photon fluctuations in the resist, induces sidewall roughness in self-aligned double patterning (SADP) spacers, potentially causing pitch walking or incomplete spacer definition that propagates to final patterns. Bridging defects, often occurring in cut or trim steps, result from incomplete etching or residual material between features, leading to short circuits; inverse lithography techniques have been employed to mitigate these by optimizing mask pixels to reduce hotspots in 14 nm and 10 nm nodes. These defects are particularly challenging in spacer-based flows, where even minor resist profile variations can amplify failure risks.^[64]^[65]^[66] Mixed methods, such as combining LELE with SADP for hybrid layers, introduce additional challenges in interconnect patterning at advanced nodes, where variability in metal lines arises from differing alignment requirements and process interactions between the two techniques. Hybrid regimes utilizing 193 nm immersion lithography must account for increased CD non-uniformity and overlay sensitivity when SADP spacers interface with LELE-defined features, complicating decomposition and increasing the risk of systematic defects like pitch doubling errors. These combinations are essential for complex layouts but demand precise co-optimization to control interconnect variability. Addressing these issues requires advanced metrology, including scanning electron microscopy (SEM) and atomic force microscopy (AFM), to verify multi-mask alignments and measure sub-10 nm features across patterning steps. CD-SEM provides high-resolution imaging for overlay and CD uniformity in SADP flows, while CD-AFM offers three-dimensional profiling to detect sidewall variations and spacer defects that SEM alone may miss. These tools enable periodic calibration of scatterometry models and inline verification, crucial for controlling pitch walk in self-aligned quadruple patterning (SAQP).^[67]^[68]^[69] As of 2025, AI-driven defect prediction has emerged as a key mitigation strategy, using machine learning to forecast stochastic failures and process variations in multiple patterning, thereby reducing yield loss by approximately 15% through early intervention. Computational guided inspection frameworks integrate neural networks to analyze multi-layer defect risks, enhancing prediction accuracy for hybrid flows and minimizing inline yield impacts. This approach prioritizes high-risk patterns, allowing proactive adjustments in lithography and etch steps.^[70]^[71] In 3D stacking architectures like complementary field-effect transistors (CFETs), multiple patterning errors are amplified due to the vertical integration of stacked layers, where misalignment in fin or nanosheet patterning propagates through multi-stack etches, exacerbating vertical EPE and dopant segregation. The 3D structure intensifies overlay challenges, as small lateral errors in base patterning layers lead to compounded variability in upper stacks, impacting device performance and reliability in sub-3 nm nodes. Tight control of inner spacers and etch-back uniformity is essential to mitigate these amplified effects.^[72]^[73]

Industrial Adoption and Future

Adoption in Logic and Memory Nodes

Multiple patterning techniques have played a pivotal role in enabling the scaling of logic devices to advanced nodes, particularly where extreme ultraviolet (EUV) lithography was not yet fully mature. Intel incorporated self-aligned quadruple patterning (SAQP) to form fins and gates in its 7 nm and 5 nm FinFET processes, allowing for precise control over critical dimensions below 20 nm while maintaining pattern fidelity.^[74] Similarly, TSMC applied litho-etch-litho-etch (LELE) double patterning for back-end-of-line (BEOL) interconnects in its 5 nm node, addressing the challenges of dense metal routing without EUV for all layers.^[75] These approaches ensured reliable transistor density improvements, with SAQP providing self-alignment to minimize overlay errors in front-end-of-line (FEOL) features. In memory technologies, multiple patterning has been indispensable for high-aspect-ratio structures. For dynamic random-access memory (DRAM) at 1x nm generations (around 14-16 nm half-pitch), spacer-is-dielectric self-aligned double patterning (SID SADP) is employed to pattern capacitor holes, using conformal spacers to define storage node openings with a single mandrel mask and reducing the need for multiple lithographic exposures.^[76] In 3D NAND flash, SADP combined with line-cut masks patterns wordlines, enabling the separation of continuous lines into individual cells across stacked layers, which supports terabit-scale densities while managing etch selectivity in vertical channels.^[77] At the 7 nm and 5 nm nodes, multiple patterning was required for the majority of layers to achieve sub-20 nm pitches, though the introduction of partial EUV at 3 nm reduced this dependency by single-patterning critical features.^[78] Samsung demonstrated functional 7 nm silicon incorporating SAQP for fin patterning as early as 2018, validating the technique's viability for high-performance logic before full EUV integration.^[79] This approach was extended to Samsung's 3 nm gate-all-around (GAA) process in 2022, where SAQP supported nanosheet formation in early production ramps.^[80] As of 2025, multiple patterning remains integral to nodes like TSMC's N2 (2 nm), applied to non-EUV layers such as peripheral interconnects to complement EUV for core features, ensuring cost-effective scaling amid ongoing EUV throughput limitations. Pilot production of N2 wafers began in 2025, with mass production starting by the end of the year.^[81]^[82]

Integration with EUV and Beyond

Multiple patterning techniques continue to play a complementary role in extreme ultraviolet (EUV) lithography ecosystems, particularly as the industry transitions from deep ultraviolet (DUV) dominance to EUV-enabled scaling. Low-numerical-aperture (low-NA) EUV systems, with a numerical aperture (NA) of 0.33, enable single patterning for most critical layers down to approximately 24 nm pitch in logic and memory applications, significantly reducing the complexity compared to DUV multiple patterning. However, for denser features below 20 nm pitch, such as vias and contacts in advanced nodes, low-NA EUV often requires double or quadruple patterning to achieve the necessary resolution and overlay control. High-NA EUV systems, operating at 0.55 NA, further extend single-patterning capabilities to around 20 nm pitch for metal lines and spaces, as demonstrated by imec's achievements in patterning 20 nm pitch damascene structures and 13 nm tip-to-tip spacing without multiple exposures. Despite this progress, high-NA EUV still necessitates double patterning for sub-20 nm pitches in vias and other high-density elements, where stochastic noise limits single-exposure viability.^[83]^[4]^[84] Hybrid flows integrating EUV and DUV multiple patterning have emerged as practical solutions to optimize cost and throughput in sub-5 nm nodes, leveraging the strengths of each technology. In these schemes, EUV is typically used for patterning cuts, vias, and less dense features where its higher resolution minimizes mask counts, while DUV multiple patterning—often self-aligned quadruple patterning (SAQP)—handles the densest line-and-space arrays, such as metal routing or word lines in memory. This approach reduces overall mask requirements compared to full DUV flows and avoids the higher capital costs of expanding EUV capacity for every layer. For instance, in 5 nm node evaluations, hybrid EUV-DUV processes have shown feasibility for achieving 40 nm pitch gratings with improved edge placement error over pure multiple patterning alternatives.^[85]^[86] Looking beyond 2025, multiple patterning remains integral to 2 nm and 1.4 nm (A16/A14) nodes starting in 2026, particularly for enabling backside power delivery (BSPDN) structures that route power rails through the wafer backside to reduce IR drop and improve performance by 15-20%. In these nodes, EUV multiple patterning will be applied to fabricate high-aspect-ratio vias and trenches for BSPDN, often requiring double patterning even with high-NA tools due to overlay tolerances below 2 nm. TSMC's A16 process, for example, incorporates BSPDN with multiple patterning for critical interconnects, forgoing high-NA EUV in favor of low-NA EUV hybrids to control costs. Challenges in this integration include amplified EUV stochastic defects, where photon shot noise and resist blur in multiple exposures can increase line-edge roughness by 20-30% and defect densities to over 1/cm² at sub-20 nm pitches, necessitating advanced dose controls and simulation-based mitigation.^[87]^[88] As of 2025, regional developments underscore multiple patterning's ongoing relevance amid EUV adoption hurdles. In China, semiconductor manufacturers like SMIC are employing DUV multiple patterning—up to seven exposures per layer—on 28 nm immersion tools to produce 7 nm-equivalent logic chips, achieving yields sufficient for commercial devices despite U.S. export restrictions on EUV. Meanwhile, imec's research on EUV multiple patterning for A10 (sub-1 nm equivalent) nodes demonstrates 18 nm pitch lines/spaces using low-NA EUV double patterning, paving the way for hybrid integration in cost-optimized flows. Samsung began mass production of its 2 nm GAA chips in November 2025, continuing to integrate multiple patterning where needed. Post-3 nm, multiple patterning is expected to decline in high-volume logic due to EUV maturation but persist in cost-sensitive memory applications like DRAM and NAND, where economic pressures favor DUV extensions over full EUV retrofits, potentially sustaining quadruple patterning through the decade.^[89]^[90]^[91]^[92]

References

[1]
https://newsroom.lamresearch.com/Enabling-Advanced-ICs-with-Multiple-Patterning
[2]
Patterning | Applied Materials
Self-aligned quadruple patterning effectively decreases the lithography resolution by 4x using a spacer-based patterning approach with one lithography step and ...Missing: manufacturing | Show results with:manufacturing
[3]
The application of multiple patterning solutions based on process ...
Dec 10, 2024 · The multi-patterning technologies aim to enhance the feature density of integrated circuits and achieve smaller process nodes through multiple ...
[4]
Single Vs. Multi-Patterning Advancements For EUV
Jun 20, 2024 · Enhanced throughput: Multi-patterning requires several lithography and etch cycles, each adding to the overall process time. In contrast, single ...
[5]
What is the Rayleigh criterion?
### Summary of Rayleigh Criterion in Optical Lithography
[6]
[PDF] Improving Lithography - Chris Mack, Gentleman Scientist
• The physical limit for k1 is 0.25 (the lowest we can go, using 2-beam imaging). – Early processes had k1 = 1.0. – Today's best processes have k1 = 0.28.
[7]
Exploiting Entanglement to Beat the Diffraction Limit | Phys. Rev. Lett.
Sep 25, 2000 · Classical optical lithography is diffraction limited to writing features of a size 𝜆 / 2 or greater, where 𝜆 is the optical wavelength.
[8]
Optical lithography at half the Rayleigh resolution limit by two ...
Recently, it has shown that Rayleigh diffraction limit (a size λ/2) is overcome using entangled-photon pairs, where λ is the optical wavelength.
[9]
Promising Lithography Techniques for Next-Generation Logic Devices
Apr 23, 2018 · 193-nm immersion lithography (193i) has given influential boost to the further development of microelectronics, and the 22- and 14-nm nodes are ...
[10]
Patterning challenges in the sub-10 nm era - SPIE Digital Library
Mar 28, 2016 · This paper will describe some of these challenges in more detail, and suggest directions for future research to keep optical lithography relevant even below ...
[11]
Line Edge Roughness (LER) - Semiconductor Engineering
Line edge roughness, or LER, is defined as a deviation of a feature edge from an ideal shape. Semiconductor features are not perfectly smooth.
[12]
Multiple Patterning - Semiconductor Engineering
Multiple patterning is a technique that overcomes the lithographic limitations in the chip-manufacturing process.
[13]
Will EUV Kill Multi-Patterning? - Semiconductor Engineering
Jan 19, 2017 · Even with EUV in play, i193 multi-patterning may still be the most cost effective option in certain cases.Missing: seminal | Show results with:seminal
[14]
Smaller, smarter, faster, and more accurate: the new overlay metrology
Apr 1, 2010 · With the introduction of double patterning, overlay capability below 5nm is required for optical lithography density scaling to the 22nm node ...
[15]
Overlay Improvement Roadmap: Strategies for Scanner Control and ...
Aug 9, 2025 · Unsurprisingly, overlay capability < 10 nm is already required for currently nodes in development, and the need for multi-patterned levels has ...
[16]
Extending the era of Moore's Law through lower cost patterning
Jan 17, 2017 · Thus, TII double-patterning presents a technological pathway for the semiconductor industry to extend the era of Moore's Law. References: [1] ...
[17]
[PDF] A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High ...
M1 employs double patterning to enable tight pitch and complex layouts. All other metal layers are fabricated with cost effective single patterning lithography.
[18]
Multi-Patterning Issues At 7nm, 5nm - Semiconductor Engineering
Nov 28, 2016 · But at 5nm, they would require EUV, plus a multiple patterning scheme. Still to be seen, however, is when or whether EUV will become ...
[19]
https://semiengineering.com/multi-patterning-problems-grow/
[20]
https://doi.org/10.1117/12.2222256
[21]
https://doi.org/10.1117/12.656163
[22]
Projection optical lithography - ScienceDirect.com
By its very definition, optical lithography employs photons in the optical regime, and the wave nature of light dictates that diffraction limits the patterning ...
[23]
Investigation of the corner rounding effect near the diffraction limit in ...
Jan 10, 2025 · The rounding of corners can severely degrade the performance and reliability of microelectronic devices due to incomplete pattern transfer.
[24]
Corner rounding and line-end shortening in optical lithography
Corner rounding and line-end shortening in optical lithography · C. Mack · Published in Other Conferences 20 October 2000 · Engineering, Physics, Materials Science.
[25]
Annular Illumination - an overview | ScienceDirect Topics
Annular illumination is a method of apertured exposure in a wafer stepper that changes the optical pathway and incident landing angle of incoming light.
[26]
[PDF] Pushing Multiple Patterning in Sub-10nm: Are We Ready? - Yibo Lin
Jun 7, 2015 · For multiple patterning lithography, one of the most fun- damental problems is to decompose the layout into a specific number of masks. Then ...
[27]
[PDF] Layout Decomposition for Double Patterning Lithography∗
We achieve an overall layout decomposition method for DPL which includes graph construction, conflict cycle detection, and node splitting processes. Our ...
[28]
Intel's 22FFL Process Improves Power, Cost, and Analog
Jan 15, 2018 · At the 22nm node, Intel adopted double-patterning for a single 90nm pitch metal to support 2D routing and complex layout shapes. In contrast ...
[29]
https://www.realworldtech.com/intel-22ffl-process/
[30]
Self-Aligned Double Patterning (SADP) - Semiconductor Engineering
The SADP process uses one lithography step and additional deposition and etch steps to define a spacer-like feature. SADP, which has been used to extend NAND to ...
[31]
https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/self-aligned-double-patterning/
[32]
(PDF) A 14nm logic technology featuring 2 nd-generation FinFET ...
Nov 21, 2015 · A 14nm logic technology using 2nd-generation FinFET transistors with novel subfin doping technique, self-aligned double patterning (SADP) for ...
[33]
Self-Aligned Double Patterning—Part Deux
Aug 14, 2014 · Because these gaps between the wires will contain dielectric material, this form of SADP is called Spacer-is-Dielectric (SID). It is ...
[34]
Patterning exploration of 16nm pitch metal lines using spacer-is ...
Apr 22, 2025 · To enable variable metal line widths in an EUV-SADP approach, a so-called spacer-is-dielectric (SID) scheme is required, resulting in a fixed ...
[35]
Fill/Cut Self-Aligned Double-Patterning - Semiconductor Engineering
Nov 17, 2016 · There are two general SADP approaches: spacer is dielectric (SID) and spacer is mask (SIM). For details of the fabrication steps in these ...
[36]
Self-Aligned Double Patterning, Part One
May 15, 2014 · SADP is similar to the litho-etch-litho-etch (LELE) double patterning (DP) you're all coming to grips with in 20/16/14nm technologies, in that ...
[37]
Lithography Resolution Limits - Arrayed Features - SemiWiki
Apr 17, 2020 · When the SADP process is applied to two-dimensional patterns, the possibilities expand. For example, in Figure 4, features on a square lattice ...
[38]
DRAM Scaling Challenges Grow - Semiconductor Engineering
Nov 21, 2019 · To make these structures in the fab, Samsung used a 193nm immersion lithography and self-aligned double-patterning (SADP) process. In the flow, ...
[39]
Self-aligned quadruple patterning to meet requirements for fins with ...
May 14, 2016 · In this SAQP method, each patterning step gives a CDU value in the sub-nanometer range (3 sigma). As well as controlling the CDU, we ...
[40]
Using Process Modeling To Enhance Device Uniformity During Self ...
Nov 18, 2021 · This study demonstrates that hole CD uniformity can be improved in an SAQP process through simulation and control of ALD thickness.
[41]
A 10nm high performance and low-power CMOS technology ...
Abstract: A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, ...
[42]
https://ieeexplore.ieee.org/document/8268472
[43]
https://ieeexplore.ieee.org/document/7059037
[44]
https://doi.org/10.1039/C3SM52607K
[45]
Self-aligned Triple Patterning for Continuous IC Scaling to Half-Pitch ...
Self-aligned triple patterning (SATP) technique offers both improved resolution and quasi-2D design flexibility for scaling integrated circuits down to sub-15 ...
[46]
Tilted ion implantation as a cost-efficient sublithographic patterning ...
Jun 1, 2016 · These results indicate that the TII technique can be used to define various patterns by adjusting the implant dose and masking-layer etch time.
[47]
https://pubs.aip.org/avs/jvb/article/34/4/040608/587773/Tilted-ion-implantation-as-a-cost-efficient
[48]
https://ieeexplore.ieee.org/document/8403865
[49]
Self-aligned multi-patterning cut/block mask decomposition techniques
Self-aligned multi-patterning (SAMP) processes require cut/block masks to define the line ends of metal target shapes, and provide the proper electrical ...Missing: blocking | Show results with:blocking
[50]
Self-aligned blocking integration demonstration for critical sub-40nm ...
Multipatterning requires the use of multiple masks which is costly and increases process complexity as well as edge placement error variation driven mostly by ...
[51]
TSMC Details 5 nm - WikiChip Fuse
Mar 21, 2020 · If N5 was a multi-patterning DUV-based process, the mask count would have ballooned up to 1.91x. In other words, with 14/16nm using around 60 ...
[52]
Semiconductor Wafer Mask Costs - AnySilicon
We have collected wafer mask set prices from our network and generated a chart that shows the comparison of maskset price for each node.
[53]
Cost Allocation in Semiconductor Chip Production - VBsemi
According to IBS data, the mask cost at the 16/14nm process is around $5 million, and at the 7nm process, the mask cost rapidly rises to $15 million. At the 7nm ...
[54]
[PDF] IMPACT OF MASK COSTS ON PATTERNING STRATEGY
$$15M Mask set ~2.5% of cost! $5M Mask set ~1.5% of cost! Page 12. EUV: DESIGN ...
[55]
Changes and Challenges Abound in Multi-patterning Lithography
Multi-patterning affects almost all aspects of design and manufacturing. For physical design it adds additional design rule constraints and constrains cell ...
[56]
[PDF] Role of Design in Multiple Patterning: Technology Development ...
Example showing translation of overlay error into CD variation in negative-tone DP process. Multiple-Patterning lithography (MP) enhances the resolution of a.
[57]
Method and apparatus for performing model-based OPC for pattern ...
A method for decomposing a target circuit pattern containing features to be imaged into multiple patterns. The process includes the steps of separating the ...
[58]
How Advanced Patterning Enables Smarter, Smaller Chips (Semi 101)
Jul 10, 2025 · After being patterned, the light is then projected onto the scanner's mirrors, reducing it by a factor of 4x until it reaches the wafer coated ...
[59]
The ASML TWINSCAN NXT:2050i
### Summary of TWINSCAN NXT:2050i
[60]
DUV Lithography: A Resurgent Force in Semiconductor Manufacturing
Oct 10, 2025 · This hybrid approach also enables more efficient multiple patterning, which is essential for pushing DUV lithography into sub-10nm territory.
[61]
Multiple patterning - Wikipedia
Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance ...Situations requiring multiple... · Other multi-patterning... · EUV multiple patterning...
[62]
Metrology, Inspection, and Process Control for Microlithography XXXIV
Apr 10, 2020 · ... CD, local placement errors, overlay errors ... In multi patterning processes, overlay is now entangled with CD including OPC and stochastics.
[63]
Budget analysis on dual layer edge placement error in logic devices
Apr 24, 2025 · This study focuses on dual-layer EPE in logic devices with litho-etch-litho-etch (LELE) configurations, analyzing critical contact layers susceptible to short ...
[64]
https://www.spiedigitallibrary.org/conference-proceedings-of-spie/9778/97781Z/Simulation-of-shotnoise-induced-side-wall-roughness-in-electron-lithography/10.1117/12.2219295.full
[65]
https://www.spiedigitallibrary.org/conference-proceedings-of-spie/9778/97782X/Controlling-bridging-and-pinching-with-pixel-based-mask-for-inverse/10.1117/12.2219281.full
[66]
Advances in Patterning Materials and Processes XXXIV | (2017) - SPIE
May 2, 2017 · For all defect orders the highest free energies were obtained when a pinning stripe was located directly under or adjacent to the terminating ...
[67]
2023 IRDS Metrology
Near-term precision (measurement uncertainty) requirements for the next few years can be met using single tools. Overlay metrology capability lags the need for.
[68]
Can remote SEM contours be used to match various SEM tools in ...
Apr 27, 2023 · In this paper we evaluate the possibility to use SEM contour metrology to perform a remote CD matching on images coming from two different CD- ...
[69]
AFM metrology for 3D high aspect ratio semiconductor structures
Apr 24, 2025 · We propose an innovative AFM-based solution 1,2 for characterizing extremely high aspect ratio structures, optimized for high-volume manufacturing (HVM).Missing: verification | Show results with:verification
[70]
A novel machine learning solution to maximize defective die capture ...
Apr 24, 2025 · This paper introduces a novel machine learning solution, Computational Guided Inspection (CGI), designed to enhance defective die capture and yield prediction ...
[71]
Guided random synthetic layout generation and machine-learning ...
Apr 22, 2025 · In this paper we propose a flow to combine synthetic layout generation and machine-learning based defect prediction to accelerate new technology ...
[72]
https://ieeexplore.ieee.org/document/10994396
[73]
Critical in-line OCD metrology for CFET manufacturing
May 5, 2025 · The multiple novels etch-back steps require tight vertical edge placement error (vEPE). Inner spacer uniformity control also becomes more ...
[74]
T ECHNICAL B RIEFS - IEEE Electron Devices Society
It features a 3rd-generation FinFET architecture with SAQP used for fin formation, and self-aligned double patterning for metallization. The 7 nm platform fea-.
[75]
CMOS Scaling for the 5 nm Node and Beyond: Device, Process and ...
In a multi-patterning scheme, such as SAmP and LELE, a new parameter, EPE (edge placement error) is introduced. It combines CD, overlay errors, and includes ...
[76]
1xnm DRAM Challenges - Semiconductor Engineering
Feb 18, 2016 · In contrast, Samsung has developed a self-aligned double patterning (SADP) scheme that requires only mask layer. In the flow, the HCS shapes ...Missing: SID | Show results with:SID
[77]
Advanced Patterning Techniques For 3D NAND Devices
Aug 15, 2019 · In this discussion, we will analyze various patterning schemes for staircase and slit structures at different TCAT (Terabit Cell Array Transistor) 3D NAND ...
[78]
Multi-Patterning EUV Vs. High-NA EUV - Semiconductor Engineering
Dec 4, 2019 · That's the 7nm node, roughly a 40nm minimum pitch,” HJL's Levinson said. The minimum pitch refers to the metal 2 (M2) structure in chips.
[79]
VLSI 2018: Samsung's 2nd Gen 7nm, EUV Goes HVM - WikiChip Fuse
Aug 4, 2018 · At the 2018 Symposia on VLSI Technology and Circuits, Samsung gave us a first glimpse of what their 7nm EUV process looks like. Samsung's second ...
[80]
Samsung Begins Chip Production Using 3nm Process Technology ...
Jun 30, 2022 · Optimized 3nm process achieves 45% reduced power usage, 23% improved performance and 16% smaller surface area compared to 5nm process.Missing: patterning SAQP
[81]
Rethinking Multipatterning for 2nm Node - SemiWiki
Feb 25, 2025 · Any double patterning scheme in EUV lithography for 2nm node still requires the imaging of a 10 nm linewidth, eg, the cell with four routing tracks and two ...
[82]
Imec achieves new milestones in single patterning High NA EUV
Sep 22, 2025 · Imec demonstrates line structures at 20nm pitch with 13nm tip-to-tip dimensions relevant for damascene metallization, as well as 20nm and ...Missing: hybrid | Show results with:hybrid
[83]
https://www.imec-int.com/en/press/imec-achieves-new-milestones-single-patterning-high-na-euv-lithography-both-damascene-and
[84]
Exploring EUV and SAQP pattering schemes at 5nm technology node
Mar 20, 2018 · ... EUV or DUV with MP, or a hybrid flow that contains both DUV-MP and EUV. In this work we are comparing two potential pattering techniques for ...
[85]
EUV's Future Looks Even Brighter - Semiconductor Engineering
where EUV is used only for the most critical layers, while 193nm ArF, ArF immersion, and KrF (248nm) scanners handle less ...
[86]
Clash of the Foundries: Gate All Around + Backside Power at 2nm
Oct 1, 2024 · Power delivery also improves on two fronts with BSPDN. ... The 1.4nm nodes and beyond should start to include greater complexity on the backside.
[87]
TSMC reiterates it doesn't need High-NA EUV for 1.4nm-class ...
May 28, 2025 · It is noteworthy that TSMC's A14 will be succeeded by A14 with SPR backside power delivery in 2029, and it does not appear that the foundry will ...
[88]
https://www.tomshardware.com/tech-industry/semiconductors/tsmc-reiterates-it-doesnt-need-high-na-euv-for-1-4nm-class-process-technology
[89]
Novel patterning technology to boost EUV performance
Apr 22, 2025 · Multiple patterning approach using 0.33NA EUV lithography could be extended up to technology node A10 targeting 18-nm pitch for Line/Space ...
[90]
Finding, Predicting EUV Stochastic Defects
Jun 17, 2021 · Beyond 30nm pitches, EUV double patterning is required, which falls under the 5nm and 3nm nodes. Double-patterning EUV involves splitting a chip ...