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Dry etching

Dry etching is a microfabrication technique that removes material from a substrate surface using plasma-generated reactive species and ions, enabling precise, anisotropic patterning essential for semiconductor device fabrication.^[1] The process occurs in a vacuum chamber where a low-pressure gas, such as fluorocarbons, chlorine, or oxygen, is ionized by electrical energy to form plasma, producing radicals and high-energy ions that chemically react with or physically sputter the exposed material, volatilizing it for removal.^[2] This method contrasts with wet etching, which relies on liquid chemical solutions and typically results in isotropic etching with undercutting, whereas dry etching provides directional control for high-resolution features down to nanometer scales.^[3] Key advantages of dry etching include superior selectivity, allowing targeted removal of specific materials like silicon or oxides without damaging underlying layers, and the ability to achieve vertical sidewalls with aspect ratios exceeding 50, critical for advanced integrated circuits.^[1] It is more complex and costly than wet etching due to the need for vacuum systems and plasma generation but yields higher precision and throughput in mass production, making it indispensable for nanoscale semiconductor manufacturing.^[2] Common types of dry etching encompass reactive ion etching (RIE), which combines chemical reactions and physical bombardment for etch rates around 50 nm/min on silicon; inductively coupled plasma (ICP) etching, offering higher plasma densities for faster rates (hundreds of nm/min) and deep structures; and deep reactive ion etching (DRIE), such as the Bosch process, which alternates etching and passivation steps to create high-aspect-ratio trenches up to 160 in narrow features.^[1] These variants are tuned by parameters like gas composition, ion energy, and pressure to optimize anisotropy and minimize surface damage.^[3] In applications, dry etching is pivotal for patterning circuit layers in microelectronics, fabricating microelectromechanical systems (MEMS), and creating nanostructures like nanowires or photonic devices, supporting the ongoing miniaturization of electronics toward sub-10 nm nodes.^[1] Its evolution continues to address challenges in emerging materials, such as III-nitrides and silicon carbide, ensuring compatibility with next-generation technologies.^[4]

Fundamentals

Definition and Principles

Dry etching is a gas-phase microfabrication process that removes material from a substrate surface using ionized gases, known as plasma, typically conducted in a vacuum environment without the use of liquid chemicals. This technique relies on the generation of reactive species within the plasma to chemically interact with the substrate, forming volatile by-products that are easily evacuated, while physical ion bombardment enhances the removal process. Unlike liquid-based methods, dry etching provides precise control over material removal, making it essential for patterning fine structures in semiconductor devices.^[5]^[6] The fundamental principles of dry etching center on the plasma's role in producing a mix of reactive ions, radicals, and neutral species through processes such as ionization, dissociation, and excitation. In a low-pressure glow discharge, electrons energized by an applied electric field collide with gas molecules, ionizing them to form positive ions and freeing electrons, while also dissociating molecules into reactive radicals (e.g., fluorine atoms from CF₄) that chemically etch the surface. Directional ion acceleration in the plasma sheath—created by self-bias electric fields—enables anisotropy by promoting vertical etching over lateral undercutting, as ions bombard the surface perpendicularly. This combination of chemical reactivity and physical sputtering allows for high-fidelity pattern transfer.^[6]^[7]^[5] Key performance metrics in dry etching include etch rate, defined as the volume or thickness of material removed per unit time (typically on the order of hundreds of angstroms per minute); selectivity, the ratio of etch rates between the target material and protective mask (e.g., 10:1 for SiO₂ over Si); and uniformity, which measures consistent etching across the substrate surface to minimize variations (often targeted below 2% deviation). These parameters are influenced by plasma conditions and gas chemistry, ensuring reproducible results in device fabrication. Plasma operations commonly occur at pressures of 1–100 mTorr to maintain mean free paths suitable for directed ion transport, with radiofrequency (RF) power at 13.56 MHz to sustain the glow discharge efficiently.^[5]^[6]^[7] Due to its anisotropic nature, dry etching enables the fabrication of sub-micron feature sizes with high aspect ratios, which is critical for advanced integrated circuits where isotropic processes would cause excessive lateral erosion.^[6]

Comparison to Wet Etching

Wet etching involves the isotropic chemical dissolution of materials using liquid etchants, such as acids or bases, which react uniformly in all directions, often resulting in undercutting beneath the mask and limiting resolution for fine features.^[8]^[9] In contrast, dry etching employs plasma-generated species for directional control, enabling anisotropic etching that proceeds preferentially in the vertical direction, unlike the diffusion-limited, isotropic reactions of wet etching.^[10]^[9] This anisotropy arises from ion bombardment in dry processes, allowing for precise profile control and vertical sidewalls essential for high-density circuits.^[8]^[10] Dry etching offers several advantages over wet etching, including superior compatibility with photoresists due to the absence of liquid immersion, which reduces mask erosion; enhanced control over etch profiles to minimize undercutting; and significantly reduced chemical waste through the use of volatile byproducts that are exhausted rather than disposed of as liquids.^[8]^[9] These benefits enable higher selectivity in certain plasma chemistries (up to 500:1 for some material-gas combinations) and support the fabrication of features with vertical sidewalls, critical for advanced microfabrication.^[9] However, dry etching has notable drawbacks, such as higher equipment costs due to vacuum systems and power supplies; potential plasma-induced damage, including lattice defects and charge traps in semiconductors; and greater complexity in process control from interdependent parameters like pressure and power.^[10]^[8]^[9] While wet etching remains suitable for bulk material removal in larger-scale processes, it is inadequate for features smaller than 1 μm due to its isotropic nature, leading to excessive lateral etching; dry etching has dominated precision applications in semiconductor manufacturing since the 1980s.^[9]^[10]

Parameter	Dry Etching	Wet Etching
Typical Etch Rate	10–100 nm/min	100–1000 nm/min
Aspect Ratio	>10:1	~1:1

These values illustrate dry etching's slower but more controlled removal for high-aspect-ratio structures, compared to wet etching's faster but less precise bulk etching.^[9]^[8]^[10]

Mechanisms and Types

Physical Etching Processes

Physical etching processes in dry etching rely on the bombardment of a substrate surface by high-energy ions or neutral particles to remove material through momentum transfer, without involving chemical reactions. The primary method is ion beam etching (IBE), also known as ion beam milling or sputtering, where a directed beam of accelerated ions, typically noble gas ions such as Ar⁺, strikes the surface and ejects atoms via physical collisions.^[11]^[12] This technique is particularly suited for applications requiring precise material removal, such as surface cleaning and patterning of metals or dielectrics in semiconductor fabrication.^[12] The core mechanism of physical etching is sputtering, where incident ions transfer kinetic energy to target atoms, displacing them if the energy exceeds the surface binding energy. The efficiency of this process is quantified by the sputter yield Y, defined as the average number of atoms removed per incident ion. Sputter yield depends primarily on the ion energy E_i, typically in the range of 100–1000 eV, and the angle of incidence, with yields increasing as the angle deviates from normal up to about 60°–80° before dropping sharply due to ion reflection.^[13]^[14] For perpendicular incidence and energies above the threshold (around 15–30 eV), a simplified model from Sigmund's theory approximates the yield as

Y \approx \frac{\alpha E_i}{U_b},

where \alpha is a material- and ion-specific constant (often around 0.042–0.2 atoms/eV for common systems), E_i is the ion energy, and U_b is the surface binding energy (e.g., ~4–5 eV for metals like silicon).^[13] This linear approximation holds for moderate energies (~100 eV) where energy deposition is proportional to E_i, derived from the nuclear stopping power in elastic collisions; full Sigmund theory integrates the deposited energy density F_D over the cascade volume, yielding Y = \Lambda F_D with \Lambda incorporating nuclear stopping cross-sections, but the simple form captures the direct proportionality for practical etching estimates.^[13] For example, argon ions at 500 eV on copper yield ~2.3 atoms/ion, compared to ~0.5 for silicon, illustrating material dependence.^[13] In operation, physical etching employs inert gases like argon at low pressures (10^{-4}–10^{-3} Torr) to generate a collimated ion beam via sources such as electron bombardment or Kaufman guns, ensuring ions arrive with controlled energy and minimal scattering.^[11]^[12]^[15] The directional nature of the beam results in highly anisotropic etching, with vertical etch rates dominating over lateral ones, as ions primarily impact horizontal surfaces.^[11] Variants like ion milling extend this to broader beam geometries for uniform thinning, often used in sample preparation for microscopy.^[12] Etch rates typically reach hundreds of Å/min at current densities of a few mA/cm².^[12] Physical etching excels in achieving high anisotropy (approaching 1, or fully directional removal) due to the collimated beam, but offers low selectivity, roughly 1:1 across materials, as removal rates scale with sputter yields rather than chemical reactivity, limiting its use to scenarios involving non-reactive or blanket materials.^[11] This makes it ideal for endpoint detection in multilayer stacks or trimming features without undercutting.^[11]

Chemical and Reactive Ion Etching

Chemical etching in dry processes relies on plasma-generated reactive radicals to remove material from the substrate surface through volatilization, without significant ion bombardment. In this isotropic method, the plasma dissociates precursor gases such as CF₄ or SF₆ to produce fluorine radicals (F•), which react with surface atoms—typically silicon—to form volatile compounds like SiF₄ that desorb into the gas phase.^[16]^[5] This approach offers high selectivity due to the specificity of radical-surface reactions, often exceeding that of physical methods, but lacks directionality, leading to undercutting in patterned features.^[17] Reactive ion etching (RIE) combines chemical reactions with physical ion bombardment to achieve anisotropic etching, where ions from the plasma enhance the chemical process by activating the surface and promoting product desorption. In RIE, reactive radicals perform the primary etching, while low-energy ions (typically 100–500 eV) sputter the surface or disrupt bonds, increasing reaction efficiency and enabling vertical sidewalls.^[18]^[19] Common gases include Cl₂ for silicon etching, forming volatile SiCl₄, and O₂ for organic materials like photoresists, producing CO₂ and H₂O.^[8] RIE can achieve selectivities greater than 100:1, such as silicon over silicon dioxide in chlorine-based plasmas, due to the non-reactivity of oxide with Cl radicals.^[20] The mechanisms of RIE follow Langmuir adsorption kinetics, involving three steps: adsorption of radicals onto the surface, chemical reaction to form volatile products, and desorption enhanced by ion impacts. Radicals adsorb dissociatively according to the Langmuir isotherm, where surface coverage θ is given by θ = (K [radical]) / (1 + K [radical]), with K as the adsorption equilibrium constant and [radical] as the radical concentration near the surface; at low coverage (typical in etching), θ ≈ K [radical].^[21] Ions then facilitate reaction by breaking bonds and aiding desorption, preventing product accumulation that would inhibit further etching. For anisotropy, sidewall passivation occurs through polymer deposition from fluorocarbon additives, protecting non-horizontal surfaces from radical attack—as seen in the Bosch process for deep reactive ion etching (DRIE).^[22] In DRIE, the Bosch process alternates etching cycles using SF₆ plasma to generate F radicals for chemical etching at the trench bottom, with ion bombardment providing directionality, and passivation cycles using C₄F₈ to deposit a Teflon-like polymer on sidewalls.^[23]^[22] This cyclic approach (typically 10–100 cycles) enables high-aspect-ratio (up to 50:1) 3D structures in silicon, such as MEMS trenches over 100 μm deep, with smooth sidewalls and minimal scalloping when optimized.^[24] The etch rate in RIE is dominated by the synergistic ion-enhanced chemical component, modeled as R = k [\text{radical}] \Gamma_{\text{ion}}, where k is the rate constant incorporating synergy, [radical] is the radical concentration, and \Gamma_{\text{ion}} is the ion flux. This arises from the total etch rate ER_{\text{tot}} = ER_{\text{s}} + ER_{\text{c}} + ER_{\text{i}}, where ER_{\text{s}} is physical sputtering (\propto \Gamma_{\text{ion}}), ER_{\text{c}} is spontaneous chemical etching (\propto [\text{radical}]), and the ion-enhanced term ER_{\text{i}} = s \Gamma_{\text{ion}} \theta, with sputtering-enhanced yield s and coverage \theta \approx b [\text{radical}] (b as adsorption coefficient) for low θ, yielding the proportional form; the full Langmuir derivation balances adsorption rate \Gamma_{\text{rad}} (proportional to [radical]) against desorption, but synergy dominates in RIE.^[25] For silicon in Cl₂ plasma, [Cl•] ≈ 10¹⁵–10¹⁶ cm⁻³ and \Gamma_{\text{ion}} ≈ 10¹⁵–10¹⁶ ions cm⁻² s⁻¹ yield rates of 100–500 nm/min, with k derived from experimental fits around 10⁻¹⁵–10⁻¹⁴ cm³ s⁻¹ ion⁻¹, illustrating the flux dependence.^[26] A key challenge in these processes is the loading effect, where etch rates vary with pattern density due to local depletion of radicals in high-open-area regions, reducing rates by up to 20–50% across a wafer.^[27] This arises from limited radical replenishment in dense features, exacerbating non-uniformity in DRIE. Mitigation involves optimizing cycle times in Bosch processes to balance radical supply, increasing gas flow or pressure to enhance diffusion, or using pulsed plasmas to reduce depletion—achieving uniformity within 5–10% over 200 mm wafers.^[28]

Equipment and Operation

Reactor Designs

Dry etching reactors are designed to generate and sustain plasma within a controlled vacuum environment, enabling precise material removal through ion bombardment and chemical reactions. The primary configurations include capacitively coupled plasma (CCP), inductively coupled plasma (ICP), and electron cyclotron resonance (ECR) systems, each differing in power coupling mechanisms, plasma density, and operational pressures to suit various etching requirements. These designs prioritize uniformity, minimal contamination, and efficient gas handling to support high-throughput semiconductor processing. Capacitively coupled plasma (CCP) reactors, commonly used for standard reactive ion etching, feature parallel-plate electrodes housed in a vacuum chamber, where radiofrequency (RF) power applied between the plates capacitively couples energy to the plasma.^[25] The lower electrode serves as the substrate platen, while the upper electrode often incorporates a gas distribution showerhead for uniform precursor delivery. These systems operate at pressures of 10–100 mTorr, achieving plasma densities of 10^9–10^10 cm^{-3} and self-bias voltages up to 500 V to direct ions toward the wafer.^[25] Vacuum chambers are typically constructed from anodized aluminum for durability and electrical grounding, lined with quartz or alumina to prevent contamination from wall erosion during plasma exposure.^[29] Wafer clamping employs mechanical pins or electrostatic chucks on the platen to maintain thermal contact and position stability, while gas inlet manifolds ensure even distribution and exhaust ports, connected to turbomolecular pumps, facilitate rapid byproduct removal. Inductively coupled plasma (ICP) reactors support high-density etching by decoupling plasma generation from substrate biasing, using external RF coil antennas—either helical or planar—wrapped around or positioned above the cylindrical chamber to induce an azimuthal electric field that efficiently heats electrons.^[25] This configuration allows independent control of ion flux and energy, operating at lower pressures of 0.5–50 mTorr with plasma densities exceeding 10^{11} cm^{-3}.^[25] Chamber materials mirror those in CCP designs, with aluminum bodies and quartz liners to minimize particle generation, and the substrate platen includes advanced clamping mechanisms for handling larger wafers up to 300 mm.^[29] Gas inlets via multi-port manifolds promote uniform flow, and dedicated exhaust systems with throttled valves maintain pressure while evacuating volatile etch products. Electron cyclotron resonance (ECR) reactors enable low-pressure operation by combining microwave power at 2.45 GHz with a static magnetic field of approximately 875 G to achieve electron resonance, producing highly uniform, high-density plasmas (10^{11}–10^{12} cm^{-3}) at 0.1–1 mTorr.^[25] The design incorporates permanent or electromagnetic coils for field generation, often with a separate plasma excitation zone upstream of the substrate area, and chambers use non-magnetic materials like stainless steel or aluminum, protected by quartz components to avoid field distortion and contamination.^[29] Wafer clamping on a biased pedestal ensures precise alignment, complemented by inlet manifolds for reactive gas injection and exhaust configurations that handle low-flow regimes efficiently. Remote plasma sources, such as microwave plasma reactors, generate radicals upstream from the substrate chamber to enable damage-free etching by reducing direct exposure to high-energy ions, with plasma confined via waveguides or toroidal designs before species diffusion to the wafer. These systems incorporate isolated plasma generation modules, gas separation baffles, and downstream exhaust for safe byproduct abatement, often using quartz tubing to preserve radical longevity while minimizing substrate charging effects.

Key Process Parameters

In dry etching processes, plasma parameters play a central role in controlling etch performance. Radio frequency (RF) power, typically ranging from 50 to 2000 W in reactive ion etching (RIE) systems, governs ion energy and plasma density, with higher power levels accelerating ions to enhance physical sputtering and chemical reaction rates.^[25] However, elevated RF power can increase etch rates while risking substrate damage through excessive ion bombardment, necessitating careful calibration to balance selectivity and uniformity.^[25] Chamber pressure, commonly maintained between 1 and 500 mTorr, influences the mean free path of ions and radicals; lower pressures promote directional ion trajectories, improving etch anisotropy by reducing lateral etching, whereas higher pressures favor isotropic chemical etching due to increased collisions.^[25] Gas-related parameters are equally critical for reaction kinetics and process stability. Feedstock gas flow rates, measured in standard cubic centimeters per minute (sccm), typically span 10 to 200 sccm depending on the reactor size and target material, ensuring adequate supply of reactive species while facilitating byproduct removal to prevent redeposition.^[25] Mixture ratios, such as CF₄ with ~5% O₂, are adjusted to optimize fluorine radical generation for silicon-based [etching](/page/ networks/etching), where oxygen enhances selectivity by scavenging carbon deposits.^[30] Substrate temperature control, often between 20°C and 150°C, modulates adsorption and desorption rates; elevated temperatures accelerate volatile product formation but may degrade mask integrity if exceeding thermal limits.^[31] Process effects are interconnected, with higher RF power boosting overall etch rates up to several hundred nm/min but potentially compromising surface quality through plasma-induced damage.^[25] Low-pressure conditions (e.g., below 50 mTorr) enhance vertical profiles by minimizing scattering, achieving aspect ratios greater than 10:1 in high-density plasmas.^[25] Endpoint detection is facilitated by optical emission spectroscopy (OES), which monitors plasma emission peaks—such as those from etch byproducts—to signal layer clearance, enabling precise termination.^[32] Optimization strategies involve systematic tuning of these parameters to achieve desired outcomes like uniform etch depths and smooth sidewalls. Factorial design experiments, screening interactions among variables such as RF power, pressure, and gas flows, identify dominant factors for etch rate and selectivity. A specific example in RIE is balancing bias voltage (typically 100-500 V, derived from RF settings) to control ion energy for sidewall passivation; moderate bias voltages promote polymer deposition on vertical surfaces, yielding near-vertical profiles, while excessive bias erodes passivation and induces undercutting. The ion flux at the plasma sheath edge, a key metric for etch rate prediction, is approximated by the equation:

\Gamma \approx \frac{n_e v_B}{4}

where n_e is the electron density (typically $10^{10} to $10^{12} cm⁻³ in low-pressure plasmas) and v_B is the Bohm velocity.^[25] This arises from plasma sheath theory: ions enter the sheath from the presheath with the Bohm speed v_B = \sqrt{\frac{k T_e}{m_i}}, where k is Boltzmann's constant, T_e is electron temperature (1-5 eV), and m_i is ion mass, satisfying the Bohm criterion for quasineutrality. The factor of 1/4 accounts for the isotropic velocity distribution in the presheath, with ion density at the sheath edge roughly half the bulk plasma density (n_s \approx n_e / 2), leading to the directed flux \Gamma = n_s v_B \approx (n_e v_B)/4 under steady-state conditions.^[25] Higher n_e (via increased RF power) elevates \Gamma, directly scaling etch rates proportional to ion bombardment.^[25]

Applications

Semiconductor Manufacturing

Dry etching serves as a cornerstone in semiconductor manufacturing, particularly for complementary metal-oxide-semiconductor (CMOS) processes used in integrated circuit fabrication. It enables precise pattern transfer after photolithography, creating critical structures such as polysilicon gates in metal-oxide-semiconductor field-effect transistors (MOSFETs), contact holes that connect transistors to metal layers, and shallow trenches for isolation in CMOS devices. These applications leverage the anisotropic nature of dry etching to achieve vertical sidewalls and minimal undercutting, which are essential for maintaining device performance at nanometer scales.^[33] In polysilicon gate etching, reactive ion etching (RIE) with chlorine-based (Cl₂) chemistry is widely adopted to remove polycrystalline silicon layers while preserving underlying gate dielectrics and spacers. This process typically involves mixtures like Cl₂/HBr/O₂ to balance etch rate and selectivity, achieving profiles suitable for sub-20 nm gate lengths in advanced MOSFETs. For contact hole formation and via etching in interconnects, fluorocarbon plasmas (e.g., CF₄ or CHF₃) are employed to anisotropically etch through silicon dioxide or low-k dielectrics, forming high-aspect-ratio openings with minimal plasma-induced damage to copper or tungsten lines. In shallow trench isolation (STI), fluorine-based chemistries create trenches that are subsequently filled with oxide to electrically isolate active regions in CMOS layouts.^[33] Dry etching integrates seamlessly into photolithography workflows, where it follows resist patterning to transfer features onto the wafer, supporting the transition to extreme ultraviolet (EUV) lithography for scaling CMOS to 3 nm nodes as of 2025. EUV-compatible dry etching processes, using metal-oxide resists applied via vapor-phase deposition, enable sub-5 nm feature definition by improving resolution and reducing line-edge roughness in high-volume manufacturing. Performance metrics emphasize uniformity across 300 mm wafers to maximize yield in cluster tools optimized for production. In damascene interconnect schemes, high selectivities (often >10:1) for SiO₂ over Si ensure precise etching of dielectric layers without significant substrate erosion, as demonstrated in fluorine-deficient fluorocarbon processes.^[34]^[35] Despite representing a significant portion of fabrication costs due to equipment and process complexity, dry etching remains vital for sustaining Moore's Law by facilitating transistor density increases through precise nanostructuring.^[36]

MEMS and Other Devices

Dry etching plays a pivotal role in fabricating microelectromechanical systems (MEMS), where deep reactive ion etching (DRIE) enables the creation of high-aspect-ratio silicon microstructures essential for devices such as accelerometers and microfluidic channels.^[37]^[38] DRIE's anisotropic nature allows for precise vertical profiles, supporting the integration of mechanical components like suspended beams and channels in compact sensors.^[39] A key variant, the Bosch process, achieves deep trenches through alternating etch-passivate cycles: an etching step using SF₆ plasma removes silicon, followed by a passivation step with C₄F₈ to deposit a protective fluoropolymer layer on sidewalls, preventing lateral etching and enabling depths exceeding hundreds of micrometers.^[22]^[40] This cyclic approach is widely adopted for MEMS fabrication due to its high etch rates and sidewall control, producing structures with aspect ratios greater than 20:1 and depths up to 500 μm for features like gyroscope rotors or fluidic reservoirs.^[41]^[24] Recent advances in the 2020s have focused on cryogenic DRIE, operating at temperatures below -100°C, which yields smoother sidewalls in MEMS by minimizing scalloping effects inherent in the Bosch process and enhancing profile uniformity for optical and mechanical applications.^[42]^[43] Cryogenic methods leverage frozen etch byproducts to protect sidewalls, achieving verticality comparable to room-temperature DRIE while reducing surface roughness to sub-nanometer levels.^[44] Beyond MEMS, dry etching supports photonic devices through waveguide fabrication, where reactive ion etching defines narrow ridges in materials like chalcogenide glasses or lithium niobate, minimizing propagation losses for integrated optical circuits.^[45]^[46] In solar cells, plasma-based texturing reduces surface reflectance by creating micro-pyramids or random nanostructures on silicon wafers, boosting light trapping and efficiency without chemical waste.^[47]^[48] For nanotechnology, dry etching patterns quantum dot arrays, as seen in PbS thin films where inductively coupled plasma removes unpatterned regions with high selectivity, enabling photodetectors with tunable optoelectronic properties.^[49]^[50] Challenges in these applications include residue management during nanoimprint lithography (NIL) for flexible electronics, where O₂ plasma etching effectively removes residual polymer layers post-imprinting, ensuring clean pattern transfer without damaging underlying substrates like polyimide.^[51]^[52] This step is crucial for maintaining feature fidelity in bendable devices. In biomedical implants, dry etching fabricates neural probes with intricate 3D geometries, such as penetrating microelectrodes on silicon substrates, allowing precise tissue interfacing for chronic neural recording.^[53]^[54] Techniques like deep reactive ion etching create shank widths below 50 μm with integrated channels, minimizing tissue damage while supporting high-density electrode arrays.^[55]^[56]

Advanced Topics

High Aspect Ratio Etching

High aspect ratio etching refers to dry etching processes that create features with an aspect ratio—defined as the depth divided by the width—exceeding 10:1, enabling the fabrication of deep, narrow structures essential for advanced micro- and nanoscale devices.^[57] These processes face significant challenges, including ion scattering, where directional ions collide with sidewalls and lose energy, reducing vertical etching efficiency; radical depletion, as reactive species are consumed along the feature depth, limiting supply to the bottom; and aspect ratio dependent etching (ARDE), which causes etch rates to decrease nonlinearly with increasing aspect ratio due to transport limitations of both ions and neutrals.^[58]^[59] ARDE is particularly pronounced in diffusion-limited regimes, where the effective etch rate E at the feature bottom follows the approximate model E \propto \frac{1}{1 + \frac{AR}{\lambda}}, with AR as the aspect ratio and \lambda as the characteristic transport length of reactive species (often related to the mean free path or diffusion coefficient).^[60] This form arises from solving the diffusion equation for neutral radicals in a one-dimensional trench model, assuming steady-state transport where the flux J at depth z satisfies J(z) = -D \frac{dC}{dz}, with D as the diffusion coefficient and C as the radical concentration; boundary conditions include surface consumption at the bottom (C(AR \cdot w) = 0, where w is width) and bulk supply at the top (C(0) = C_0). Integrating yields an exponential decay in concentration, approximated for high AR by the inverse form above, highlighting how etch rate drops as AR exceeds \lambda, typically on the order of 1–10 for plasma conditions.^[60]^[61] To address these issues, specialized techniques such as pulsed plasma etching and multi-step gas pulsing in deep reactive ion etching (DRIE) are employed, where plasma power or gas flows are cycled to enhance species transport and renew passivation without excessive deposition.^[62] In DRIE, alternating SF₆-based etching pulses with C₄F₈ passivation steps allow aspect ratios exceeding 30:1 in inductively coupled plasma (ICP) systems, as demonstrated in silicon trench etching with controlled sidewall protection.^[63] Sidewall bowing, caused by ion scattering and polymer redistribution, is mitigated by optimizing passivation layer thickness—typically 10–50 nm of fluorocarbon—deposited during off-cycles to shield sidewalls while allowing ion access to the bottom.^[64] These methods are critical for fabricating FinFET transistors, where gate structures require aspect ratios >20:1 for improved channel control, and 3D NAND memory, demanding stacked channels with >50:1 ratios for higher density.^[63] Microloading effects exacerbate non-uniformity in high aspect ratio etching, as denser patterns deplete local radical concentrations faster, reducing etch rates by up to 50% in isolated vs. grouped features; compensation involves pattern density-aware process tuning, such as varying pulse durations.^[59] Faceting at mask edges, resulting from enhanced ion bombardment at corners and mask undercutting, leads to tapered profiles and is corrected by using tapered or hardened masks (e.g., Cr or Ni) combined with low-bias pulsing to minimize lateral erosion.^[65]

Emerging Techniques

Emerging techniques in dry etching are advancing toward atomic-scale precision to meet the demands of nanoscale fabrication, particularly for structures beyond the limits of conventional reactive ion etching. Among these, atomic layer etching (ALE) stands out as a cyclic, self-limiting process that removes material one monolayer at a time, enabling sub-nanometer control without the damage associated with continuous plasma exposure.^[66] This method addresses key challenges in fabricating advanced devices by providing uniform, damage-free etching across complex topographies.^[67] The ALE process typically involves sequential steps: surface modification through adsorption of a reactive species, followed by selective removal of the modified layer. In the modification step, an inhibitor or precursor, such as chlorine from a Cl₂ plasma, adsorbs onto the surface to form a thin, self-limiting reactive layer (e.g., SiClₓ on silicon). This is followed by an etch step where low-energy ions, like argon ions, desorb the modified layer as volatile byproducts (e.g., SiCl₂ gas), completing one cycle.^[66] For silicon etching, this Cl₂ plasma modification combined with Ar ion bombardment exemplifies the technique, achieving an etch per cycle (EPC) of approximately 0.5 nm with plasma assistance.^[66] The self-limiting nature ensures precise thickness control, with cycle times often in the range of seconds to minutes depending on the material and reactor design.^[67] The etch rate in ALE is fundamentally given by:

\text{ALE rate} = \frac{\text{monolayer thickness}}{\text{cycle time}}

where monolayer thickness is typically 0.1–0.5 nm for semiconductors like silicon. The paper introduces process synergy to quantify optimization, defined as synergy = (EPC - α - β) / EPC, where α represents unintended etching during the modification step and β represents sputtering of unmodified material during the etch step. High synergy (>80%) is achieved in optimized processes by minimizing these effects.^[66] In the isotropic thermal ALE variant, removal occurs uniformly via ligand-exchange reactions in vapor phase, leading to non-directional etching suitable for blanket films. Conversely, anisotropic plasma-enhanced ALE incorporates ion bombardment for directional control, enhancing vertical etch rates while minimizing lateral undercutting, as the ion energy (e.g., 20–50 eV) aligns desorption perpendicular to the surface. This distinction allows tailoring for high-aspect-ratio features.^[66]^[68] ALE enables etching precision below 1 nm per cycle, critical for gate-all-around (GAA) transistors where channel dimensions approach 3–5 nm, ensuring sharp interfaces and reduced variability in electron mobility.^[67] Plasma-enhanced ALE for dielectrics like HfO₂ and ZrO₂ achieves layer-by-layer removal with high selectivity relative to underlying layers, vital for 3D NAND and logic scaling.^[69] Beyond ALE, vapor phase etching emerges as a plasma-free alternative, relying on gas-phase reactions (e.g., HF vapor for SiO₂) to achieve isotropic removal without ion-induced damage, preserving surface quality for sensitive materials like β-Ga₂O₃.^[68] Neutral beam etching complements this by generating low-energy neutral species (e.g., Cl neutrals) from a remote plasma source, enabling anisotropic profiles with reduced leakage currents in GaN-based devices, such as micro-LEDs, where surface roughness is limited to 0.45 nm at aspect ratios up to 10.^[67] These techniques integrate seamlessly with extreme ultraviolet (EUV) lithography, supporting sub-5 nm patterning by providing the etch selectivity needed for high-numerical-aperture EUV resists and multi-patterning schemes.^[70] Sustainability drives further innovation, with halogen-free chemistries like N₂/H₂ plasma reducing reliance on fluorocarbons and chlorides, minimizing toxic byproducts and environmental impact while maintaining etch rates comparable to traditional methods (e.g., >10 nm/min for TiAlC).^[71] Such advances not only lower emissions but also enhance process safety in high-volume manufacturing.^[67]

Historical Development

Early Innovations

The development of dry etching originated from precursor techniques in the 1960s, where glow discharge plasmas were employed for surface cleaning in semiconductor processing to remove contaminants from substrates and vacuum chamber walls.^[72] These early applications, reviewed in foundational works on vacuum technology, laid the groundwork for extending plasma-based methods to material removal beyond mere cleaning.^[72] By the early 1970s, plasma etching emerged as a viable alternative to wet methods for patterning semiconductors, with the first significant advancements including radio-frequency (RF) plasma systems for photoresist stripping using oxygen plasmas, as demonstrated in 1971 experiments at Bell Laboratories.^[73] A key milestone was the 1971 patent for plasma processes targeting silicon nitride etching, marking the initial formal recognition of plasma etching for semiconductor device fabrication.^[74] During the 1970s, researchers at Bell Labs introduced RF-powered plasma etching systems, enabling controlled generation of reactive species in capacitively coupled reactors for more precise pattern transfer.^[75] This period also saw the pioneering work of J.W. Coburn and H.F. Winters, whose collaborative studies, including Coburn's 1979 paper, elucidated ion-enhanced etching mechanisms, showing how simultaneous ion bombardment and chemical reactions dramatically increased etch rates and anisotropy in silicon-based materials.^[76] Early dry etching processes frequently utilized tetrafluoromethane (CF4) gas in plasma discharges for selective removal of silicon dioxide (SiO2) layers, achieving etch rates suitable for dielectric patterning without excessive undercutting, as explored in late-1970s studies on fluorocarbon chemistries.^[77] Advancements in physical sputtering, a related dry technique, improved ion beam control for thin-film removal in integrated circuit production during the 1970s.^[78] In the 1980s, reactive ion etching (RIE) transitioned from research to commercial production, with companies like Lam Research—founded in 1980—and Applied Materials scaling batch RIE tools for high-volume semiconductor manufacturing, where Applied Materials captured market leadership by 1982 through systems etching dielectrics, metals, and polysilicon.^[74] By the mid-1980s, integrated circuit fabrication facilities (fabs) shifted predominantly from wet chemical etching to dry plasma methods at feature sizes around 3 micrometers, driven by needs for anisotropy and reduced chemical waste, though early fabs often employed hybrid wet-dry workflows to balance throughput and precision. This evolution enabled the first all-dry-etched devices, such as those produced by Texas Instruments in 1975, setting the stage for denser circuit integration.^[79]

Modern Evolution

In the 1990s and 2000s, dry etching advanced significantly through the adoption of high-density plasma reactors such as inductively coupled plasma (ICP) and electron cyclotron resonance (ECR) systems, which enabled higher etch rates and better uniformity for complex semiconductor structures.^[28] These reactors addressed limitations of earlier reactive ion etching by generating plasma densities exceeding 10^11 cm^{-3} at low pressures, facilitating precise control over ion energy and radical flux.^[75] A pivotal innovation was the development of deep reactive ion etching (DRIE), exemplified by the Bosch process introduced in 1993, which alternated etching and passivation cycles to achieve high-aspect-ratio features essential for microelectromechanical systems (MEMS).^[80] During the 2000s, the shift toward low-k dielectrics for interconnects drove further refinements in plasma chemistries, using fluorocarbon-based gases to minimize damage while maintaining selectivity over underlying barriers.^[81] The 2010s marked the rise of atomic layer etching (ALE), a self-limiting process funded in part by DARPA initiatives to enable sub-10 nm precision, contrasting with continuous plasma etching by removing material one monolayer at a time through sequential adsorption and desorption steps.^[82] This technique proved crucial for fabricating 3D integrated circuits (ICs) and FinFET transistors, where dry etching adapted to create vertical fins with aspect ratios over 20:1 and gate-all-around structures, supporting scaling from 22 nm to 7 nm nodes.^[83] By the 2020s, process complexity had evolved dramatically—from single-step etches in the 1980s to multi-cycle sequences exceeding 10 steps in modern flows—to meet demands for defect-free profiles in high-volume manufacturing.^[84] In 2025, AI-driven optimization emerged as a key update, employing machine learning surrogate models to predict and adjust etch rates in real time through parameter tuning.^[85] Sustainability efforts intensified in the 2020s amid regulations targeting perfluorocarbons (PFCs) and per- and polyfluoroalkyl substances (PFAS) used in plasma etching, with the semiconductor industry committing to phase out intentional PFOA uses by 2025 to curb emissions and environmental persistence.^[86] These pushes align with broader PFC reduction goals under frameworks like the Montreal Protocol, prompting shifts to alternative chemistries such as NF3 abatement systems.^[87] Dry etching also found niche applications in quantum computing fabrication, where low-energy ion beam etching patterns superconducting materials like niobium for resonators, enabling the exploration of broader material options for quantum hardware with performance comparable to conventional methods.^[88] This evolution has been propelled by Moore's Law, transforming dry etching from handling 1 μm features in the 1980s to sub-2 nm gates today, with the global etch equipment market surpassing $10 billion in 2025 to support these ultrathin nodes.^[89]^[90]

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