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Metal gate

A metal gate is a gate electrode structure in metal-oxide-semiconductor field-effect transistors (MOSFETs) composed of metal materials, replacing traditional doped polysilicon gates to enable precise threshold voltage tuning and improved device performance in advanced complementary metal-oxide-semiconductor (CMOS) technology.^[1] This innovation addresses key limitations of polysilicon gates, such as the poly-depletion effect that increases effective oxide thickness and reduces gate capacitance, by providing lower resistivity and compatibility with high-k dielectric materials like hafnium oxide (HfO₂).^[2] The adoption of metal gates marked a pivotal shift in semiconductor fabrication, particularly with the integration of high-k/metal gate (HKMG) stacks around the 45 nm technology node, allowing continued scaling of transistor dimensions while mitigating gate leakage and enhancing drive currents.^[3] Key advantages include a reduction in equivalent oxide thickness by 3–4 Å due to the absence of depletion regions in metals, superior thermal stability, and the ability to select metals with specific work functions—approximately 4.05 eV for n-type MOSFETs (NMOS) and 5.15 eV for p-type MOSFETs (PMOS)—to optimize channel inversion across the silicon bandgap of 1.1 eV.^[1] Fabrication approaches vary, with gate-first processes (e.g., used by IBM) integrating metals early in the workflow and gate-last or replacement metal gate (RMG) methods (e.g., employed by Intel and TSMC) inserting metals after high-temperature steps to preserve material integrity.^[1] This technology has been essential for high-performance computing applications, enabling faster switching speeds, lower power consumption, and higher transistor densities in modern integrated circuits, with ongoing refinements supporting nodes below 10 nm.^[2] Common metals include titanium nitride (TiN) for its tunable work function and ruthenium (Ru) for low resistivity, though challenges like Fermi level pinning at metal-dielectric interfaces require careful interface engineering.^[1]

Historical Development

Early Aluminum Gates

The first metal-oxide-semiconductor field-effect transistor (MOSFET) was demonstrated in 1960 by Mohamed M. Atalla and Dawon Kahng at Bell Laboratories, utilizing an aluminum gate in a p-channel configuration on a silicon substrate.^[4]^[5] This pioneering device featured a thermally grown silicon dioxide (SiO₂) layer as the gate dielectric, with aluminum serving as the gate electrode due to its high electrical conductivity, characterized by a resistivity of approximately 2.65 × 10⁻⁸ Ω·m, which facilitated efficient charge control.^[6] Aluminum's ease of deposition via thermal evaporation or sputtering onto the oxide surface further enabled straightforward integration into early MOS structures, allowing for the creation of discrete transistors and initial integrated circuits.^[7] By the mid-1960s, aluminum-gated MOSFETs saw widespread adoption in discrete MOS integrated circuits, particularly in p-channel implementations by companies like Fairchild Semiconductor and RCA, marking a shift toward scalable semiconductor manufacturing.^[8] The fabrication process for these early aluminum-gated devices began with thermal oxidation of the silicon wafer to form a thin SiO₂ gate dielectric, typically tens to hundreds of nanometers thick, which passivated the silicon surface and minimized interface states.^[5] Source and drain regions were typically predeffused, followed by aluminum deposition across the wafer using evaporation or sputtering techniques, then patterning via photolithography and wet etching to define the gate electrode and interconnects.^[7] This metal gate approach simplified production compared to earlier junction-based transistors, enabling the basic metal-oxide-semiconductor (MOS) capacitor structure central to MOSFET operation. The oxide capacitance, which governs gate control over the channel, is given by

C = \frac{\epsilon_0 \epsilon_r A}{d}

where \epsilon_0 is the vacuum permittivity, \epsilon_r is the relative permittivity of SiO₂ (approximately 3.9), A is the gate area, and d is the oxide thickness; the aluminum gate's direct metallic contact eliminated depletion layers at the top interface, yielding a pure insulator capacitance without poly-depletion complications.^[9] Despite these advantages, aluminum gates exhibited significant limitations, particularly thermal instability during processing temperatures exceeding 400°C, where aluminum atoms diffused through thin SiO₂ layers into the underlying silicon, leading to threshold voltage shifts and exacerbated short-channel effects.^[5] Early experiments at Fairchild in the 1960s highlighted this issue, showing device instability after annealing steps intended to activate dopants or form contacts, as aluminum penetration contaminated the channel region and altered doping profiles.^[10] Such diffusion-related instabilities, compounded by mobile ionic contaminants like sodium, undermined reliability in integrated circuits, ultimately prompting a transition to polysilicon gates for better thermal compatibility.^[11]

Introduction of Polysilicon Gates

The transition from aluminum to polysilicon gates in MOSFET fabrication during the late 1960s addressed key limitations in high-temperature processing, as aluminum's low melting point and diffusion tendencies hindered dopant activation steps exceeding 600°C.^[12] Polysilicon offered superior thermal stability, enabling dopant diffusion up to 1000°C without melting or significant degradation, which was essential for reliable source and drain formation in integrated circuits.^[13] Additionally, polysilicon could be deposited conformally using low-pressure chemical vapor deposition (LPCVD) at 600-650°C with silane precursors, allowing precise control over film thickness and uniformity on complex topologies. Initially introduced as undoped polysilicon for high-resistivity resistor loads in PMOS devices, the material provided stable passive components without requiring additional masking steps.^[14] By 1970, Fairchild Semiconductor advanced the technology with n+-doped polysilicon gates for enhancement-mode NMOS transistors, incorporating phosphorus or arsenic dopants to enhance conductivity while leveraging the gate as a diffusion mask.^[13] A pivotal innovation was the 1969 Bell Labs patent by Kerwin, Klein, and Sarace, which described a self-aligned gate process using polysilicon to define source and drain regions, thereby minimizing parasitic overlap capacitance and improving device packing density.^[15] Heavily doping polysilicon with phosphorus or arsenic dramatically reduced its resistivity from approximately 10^3 Ω·cm in the undoped state to ~10^{-3} Ω·cm, making it suitable for low-resistance gate electrodes without compromising process compatibility.^[16] This advancement enabled scaling of NMOS integrated circuits to feature sizes around 10 µm in the 1970s, as exemplified by Intel's 1103 DRAM introduced in 1970, which utilized silicon-gate technology to achieve 1 Kb density and outperform magnetic core memory in commercial applications.^[17]

Polysilicon Gate Era

NMOS Implementation

In NMOS implementations, polysilicon gates were heavily doped to n-type (N+) using phosphorus ion implantation at doses around 10^{15} cm^{-2}, which established a work function of approximately 4.1 eV for the gate material.^[18]^[19] This doping profile aligned the gate work function closely with the silicon conduction band, facilitating a typical NMOS threshold voltage (V_{th}) of about 0.7 V and enabling efficient enhancement-mode operation without excessive gate overdrive.^[20] Polysilicon gates found widespread use in depletion-load NMOS configurations for static logic circuits, where the depletion-mode load transistor provided a resistive pull-up without requiring a separate power supply rail.^[21] A prominent example is the Intel 8080 microprocessor, released in 1974, which employed n-channel silicon-gate (polysilicon) technology in its depletion-load NMOS design to achieve improved speed and TTL compatibility over prior PMOS devices. In memory applications, polysilicon gates served as word lines in dynamic RAM (DRAM) cells, leveraging their compatibility with the one-transistor-per-bit architecture introduced in the 1970s; for instance, the 4 Kbit DRAM chips of that era used silicon-gate NMOS processes to form the access transistor gates along the word lines.^[22] The electrical performance of these polysilicon gates in NMOS circuits was characterized by a sheet resistance of 20-50 Ω/sq for typical thicknesses around 500 nm, which supported circuit delays suitable for clock speeds reaching up to 10 MHz by the 1980s.^[23]^[24] This resistance level minimized RC delays in gate interconnects while maintaining process simplicity. A key optimization in the 1980s involved adding self-aligned silicides, such as TiSi_{2}, atop the polysilicon gates to further reduce sheet resistance to below 5 Ω/sq without risking shorts to the underlying silicon channel, as the silicide formation was confined by the gate sidewall spacers.^[25] By 1980, polysilicon gate technology dominated MOS integrated circuits, primarily through NMOS logic and memory, and enabled reliable scaling to sub-micron feature sizes down to 1 µm nodes by improving alignment precision and thermal stability over aluminum gates.

CMOS Integration

The integration of polysilicon gates into complementary metal-oxide-semiconductor (CMOS) processes emerged in the late 1970s as a natural extension of NMOS technology, enabling the complementary pairing of n-channel and p-channel transistors to achieve dramatically lower static power dissipation compared to single-channel NMOS designs. Early CMOS implementations retained the self-aligned polysilicon gate structure for precise control of channel lengths, but adapting it to both transistor types introduced challenges due to work function differences. Specifically, n+-doped polysilicon gates, with a work function of approximately 4.05 eV, provided low threshold voltages (V_th) for NMOS transistors but resulted in a significant mismatch for PMOS devices, where the ideal p-channel work function is around 5.2 eV; this led to elevated PMOS V_th values of about 1-1.5 V, degrading drive current balance and overall circuit performance.^[26]^[27] To address this asymmetry, 1980s CMOS processes commonly employed n+-doped polysilicon gates for both NMOS and PMOS transistors, compensating for the PMOS V_th shift through heavier boron channel implants to adjust the substrate doping profile. This approach maintained a unified gate material while enabling balanced complementary operation, though it increased process complexity with additional masking steps for selective implants. By the 1990s, dual-doped polysilicon gates became prevalent, using phosphorus or arsenic for n+ regions and high-dose boron implants for p+ regions to achieve work functions closer to 5.2 eV in PMOS; however, boron penetration through thin gate oxides during high-temperature annealing posed risks of threshold voltage instability and oxide degradation.^[28]^[29]^[30] The typical process flow for polysilicon gate CMOS involved shared deposition of undoped amorphous silicon followed by patterning to define gates for both NMOS and PMOS regions, with subsequent selective ion implantation for source/drain doping—n-type for NMOS and p-type for PMOS—while self-alignment minimized overlap capacitances. An illustrative example is the 1.2 µm CMOS technology developed in the mid-1980s for low-power logic applications, where polysilicon gates enabled efficient complementary switching in radiation-hardened environments. This integration facilitated power reductions of 50-100 times relative to NMOS equivalents, with standby currents below 1 µA per chip, making CMOS viable for portable electronics.^[31]^[32] Historically, the first commercial CMOS devices with polysilicon gates appeared in the early 1970s for battery-powered applications, such as RCA's silicon-gate frequency dividers in electronic wristwatches, which leveraged low standby power for extended operation. By the 1990s, polysilicon gate CMOS had scaled to 0.5 µm nodes in high-volume microprocessors, supporting clock speeds up to 200 MHz while preserving the complementary architecture's efficiency.^[33]

Scaling Challenges

Poly Depletion Effect

The polysilicon depletion effect arises in MOSFETs employing doped polysilicon as the gate material, particularly under inversion bias conditions. For an n-channel device, a positive gate-to-source voltage depletes mobile carriers from the polysilicon near the gate oxide interface, forming a depletion region that introduces an additional voltage drop and reduces the electric field penetration into the channel. This phenomenon degrades gate control over the channel, effectively mimicking a thicker gate dielectric and limiting scalability in sub-micron technologies.^[9] The physical mechanism can be quantified through the depletion width W_{\mathrm{dep}} in the polysilicon gate, approximated as W_{\mathrm{dep}} \approx \sqrt{\frac{2 \epsilon_{\mathrm{si}} \phi_b}{q N_{\mathrm{poly}}}}, where \phi_b \approx 0.5 \, \mathrm{V} is the band bending potential, N_{\mathrm{poly}} \approx 10^{20} \, \mathrm{cm}^{-3} is the gate doping concentration, q is the elementary charge, and \epsilon_{\mathrm{si}} is the permittivity of silicon. The resulting effective oxide thickness becomes t_{\mathrm{ox,eff}} = t_{\mathrm{ox}} + \frac{\epsilon_{\mathrm{ox}}}{\epsilon_{\mathrm{si}}} W_{\mathrm{dep}}, leading to a 10-20% reduction in gate capacitance at V_g = V_{\mathrm{dd}}.^[9] This effect significantly impacts device performance by effectively reducing the gate overdrive by approximately 0.2 V and reducing the on-state drive current I_{\mathrm{on}} by 15-25% in 90 nm nodes, thereby compromising speed and power efficiency. The issue became prominent for gate lengths below 100 nm, as highlighted in 1990s simulations by IBM and Intel researchers exploring scaling limits. Capacitance-voltage (C-V) profiling measurements confirm the capacitance drop in strong inversion, equivalent to a 3-5 Å (0.3-0.5 nm) increase in oxide thickness.^[34]^[35]

Resistance and Gate Leakage Issues

As semiconductor devices scaled below 65 nm, as gate lengths scaled below 50 nm the sheet resistance of polysilicon gates increased to several hundred Ω/sq, primarily due to grain boundary scattering, which substantially elevated the RC delay in gate electrodes and limited overall circuit performance. This resistance issue was temporarily alleviated through polycide structures, such as tungsten silicide (WSi₂) deposited on polysilicon, achieving resistivities around 100 μΩ·cm and reducing sheet resistance to manageable levels for nodes down to approximately 90 nm, though further scaling exposed limitations in silicide uniformity and thermal stability.^[36] A parallel challenge arose from gate leakage due to direct quantum tunneling through ultrathin SiO₂ layers below 2 nm, where electrons and holes traverse the barrier via the Wentzel-Kramers-Brillouin (WKB) approximation, yielding a current density J \propto \exp(-B t_{\mathrm{ox}}), with the constant B \approx 25 Å⁻¹ for typical barrier heights in SiO₂.^[37] At an oxide thickness of 1.2 nm, this mechanism produced gate leakage currents exceeding 1 μA/μm width under operational biases around 1 V, significantly contributing to standby power dissipation and exacerbating thermal management in dense circuits.^[38] In the 45 nm technology node, these effects manifested as a notable rise in gate delay by approximately 20-30% attributable to combined resistance and depletion contributions, while gate leakage accounted for over 50% of total static power in high-performance logic devices, as projected in the 2000s International Technology Roadmap for Semiconductors (ITRS).^[39] The 2003 ITRS edition crystallized industry consensus that conventional polysilicon-SiO₂ stacks would prove unsustainable beyond the 32 nm node due to these escalating electrical losses, prompting a shift toward alternative materials.^[39] Compounding these issues in PMOS transistors, boron penetration from heavily doped p⁺ polysilicon gates diffused through the thin SiO₂, elevating stress-induced leakage currents and reducing charge-to-breakdown by enhancing trap creation efficiency during electrical stress.^[40] Poly depletion further aggravated effective capacitance reduction, indirectly amplifying the perceived impact of resistance on delay in scaled devices.^[39]

Revival of Metal Gates

High-k Dielectric Integration

As the scaling of silicon dioxide (SiO₂) gate dielectrics approached thicknesses below 1.5 nm equivalent oxide thickness (EOT), direct tunneling currents became unacceptably high, leading to excessive gate leakage and power dissipation in CMOS transistors.^[41] This limitation, triggered by the poly-Si/SiO₂ stack's inability to maintain low leakage at sub-1.5 nm EOT, necessitated the adoption of high-k dielectrics to enable further scaling while preserving capacitive coupling.^[42] High-k materials like hafnium oxide (HfO₂, with a dielectric constant k ≈ 25) allow for physically thicker films (>2 nm) that achieve an EOT of approximately 1 nm through the relation EOT = (k_SiO₂ / k_high-k) × t_phys, where k_SiO₂ = 3.9 and t_phys is the physical thickness, thereby reducing tunneling without sacrificing performance.^[43] The integration of high-k dielectrics with metal gates presented significant challenges, particularly the reactivity of traditional polysilicon gates with HfO₂ during deposition and high-temperature processing, which forms undesirable silicides and degrades interface quality.^[44] To address this, two primary process flows emerged: gate-first, where the high-k dielectric is deposited followed by the metal gate and subsequent annealing to stabilize the stack; and gate-last (also known as replacement metal gate, RMG), which involves using a dummy polysilicon gate during source/drain formation, followed by its removal and metal fill after high-temperature steps to minimize thermal damage to the dielectric.^[45] Intel's pioneering implementation in 2007 utilized a gate-last approach for their 45 nm Penryn processors, featuring high-k first and metal gate last, with the dummy gate removed after high-temperature steps and replaced with metal, marking the first high-volume manufacturing of high-k/metal gate transistors.^[46] This integration achieved an EOT of 1.0 nm using hafnium-based dielectrics, resulting in gate leakage reductions of over 25× for NMOS and up to 1000× for PMOS compared to the prior 65 nm SiO₂-based process, significantly enhancing power efficiency.^[47] Initial materials focused on HfSiON (hafnium silicon oxynitride) for improved thermal stability and compatibility, but subsequent evolution shifted toward pure HfO₂ with lanthanum (La) or aluminum (Al) capping layers to fine-tune threshold voltage (V_th) by modulating the dipole at the high-k/SiO₂ interface, enabling better control over transistor characteristics without altering the gate electrode.^[48] These advancements allowed continued EOT scaling while mitigating leakage, forming the foundation for metal gate adoption in advanced nodes.^[46]

Metal Materials and Work Function Tuning

The work function of the metal gate electrode, denoted as \Phi_m, plays a pivotal role in determining the threshold voltage V_{th} of MOSFETs in CMOS technology, enabling effective control of carrier inversion at low supply voltages during scaling. For NMOS transistors, an optimal \Phi_m of approximately 4.1 eV (near the silicon conduction band edge) minimizes V_{th} for enhanced drive current, while PMOS requires \Phi_m \approx 5.2 eV (near the valence band edge) to achieve symmetric performance. In contrast, traditional n+-doped polysilicon gates exhibit a fixed \Phi_m \approx 4.1 eV, which is suitable for NMOS but leads to unacceptably high V_{th} for PMOS, limiting overall CMOS efficiency and scalability beyond the 90 nm node.^[49]^[50] Selection of metal materials focuses on achieving these band-edge work functions while ensuring compatibility with high-k dielectrics and thermal budgets. Mid-gap metals such as titanium nitride (TiN), with \Phi_m \approx 4.8 eV, provide balanced thresholds for initial implementations but require tuning for optimal CMOS pairing. For NMOS, nitrogen-rich tantalum nitride (TaN) offers \Phi_m \approx 4.3 eV, closely matching the desired value, whereas PMOS employs p-type metals like rhenium (Re) or molybdenum (Mo) to reach \Phi_m \approx 5.1 eV; alternatively, TiN/Al stacks enable fine adjustment toward this range through interfacial effects. These materials are chosen for their thermal stability, low resistivity, and ability to form conformal layers via atomic layer deposition (ALD), critical for sub-45 nm nodes.^[51]^[52] Work function tuning is accomplished through several established methods to precisely control \Phi_m without compromising stack integrity. Doping via processes like N_2 annealing can shift TiN's \Phi_m by up to 0.3 eV toward lower values by altering nitrogen stoichiometry and surface dipoles. Capping layers, such as La_2O_3, introduce interface dipoles that reduce \Phi_m by approximately 0.2 eV, ideal for NMOS band-edge alignment. In gate-first integration, dual-metal stacks combine these elements—for instance, layering TiN with Al and TaN—to achieve differential work functions. A seminal example is Intel's 2007 implementation at the 45 nm node, where a TiAlN (for NMOS) and TiN (for PMOS) configuration realized the necessary work function split, delivering equivalent or superior performance to polysilicon gates with enhanced drive currents and reduced leakage.^[53]^[54]^[46] The direct influence of \Phi_m on device characteristics is evident in the MOSFET threshold voltage equation:

V_{th} = \Phi_m - \Phi_{si} + 2\phi_f + \frac{\sqrt{4\epsilon_{si} q N_a \phi_f}}{C_{ox}}

Here, \Phi_{si} is the silicon work function, \phi_f the Fermi potential, N_a the substrate doping, \epsilon_{si} the silicon permittivity, q the elementary charge, and C_{ox} the oxide capacitance per unit area. This formulation highlights the linear dependence of V_{th} on \Phi_m, underscoring why precise tuning is essential for maintaining low V_{th} variability and enabling continued CMOS scaling post-2007.^[55]

Modern Applications

Advanced Node Technologies

In advanced semiconductor nodes, metal gates have been integral to three-dimensional transistor architectures, starting with the introduction of FinFETs at the 22 nm process. Intel's 22 nm technology, launched in 2011, employed tri-gate FinFETs where metal gates wrap around three sides of the silicon fin, providing superior electrostatic control over the channel compared to planar transistors.^[56] This structure utilized a replacement metal gate (RMG) process, also known as gate-last integration, to deposit high-k dielectrics such as HfO₂ followed by metal electrodes like TiN, enabling uniform gate formation across multiple fins for enhanced drive strength.^[56] The evolution toward gate-all-around (GAA) transistors further advanced metal gate integration, particularly in sub-7 nm nodes. Samsung's 3 nm process, introduced in 2022, incorporates nanosheet GAA channels where metal gates fully surround the stacked nanosheets, filling the spaces between them to achieve complete channel encirclement and improved short-channel effects management.^[57] This configuration significantly reduces leakage currents, with the overall process delivering approximately 45% lower power consumption compared to prior FinFET-based nodes like 5 nm.^[57] Adapting metal gate deposition for these complex 3D structures requires precise techniques to handle high-aspect-ratio features below 10 nm. Atomic layer deposition (ALD) of materials such as TaN and TiN ensures conformal filling and uniformity in narrow, tall gate trenches, maintaining work function compatibility while minimizing defects in high-k interfaces.^[58] For instance, plasma-enhanced ALD variants enable step-coverage exceeding 90% in aspect ratios over 20:1, critical for GAA nanosheet stacking.^[59] Key demonstrations of these integrations include TSMC's 5 nm FinFET node from 2019, where optimized metal gate stacks with high-k dielectrics achieved up to 15% higher performance at iso-power relative to the 7 nm generation, leveraging refined RMG processes for better threshold voltage control.^[60] As of November 2025, ongoing developments for 2 nm nodes incorporate extreme ultraviolet (EUV) lithography for precise gate patterning, alongside emerging metals like ruthenium (Ru) and molybdenum (Mo) to reduce sheet resistance in gate electrodes and interconnects, supporting scaling beyond traditional tungsten fills. TSMC's 2 nm (N2) process, featuring nanosheet GAA transistors, entered high-volume manufacturing in the second half of 2025, with early adoption by customers including Apple and NVIDIA for high-performance computing and AI applications.^[61]^[62]

Performance Advantages and Fabrication Challenges

Metal gates offer significant performance enhancements over traditional polysilicon gates in MOSFETs, primarily by eliminating the polysilicon depletion effect, which reduces the effective gate capacitance and limits drive current. This results in a 20-30% increase in on-state current (I_on) for equivalent off-state leakage, as demonstrated in simulations of high-k/metal gate stacks at sub-35 nm nodes.^[63] Additionally, metal gates enable equivalent oxide thickness (EOT) scaling down to 0.7 nm when paired with high-k dielectrics, providing approximately 15% higher gate capacitance compared to polysilicon counterparts, which improves electrostatic control and subthreshold swing.^[64] These benefits allow for lower supply voltage (V_dd) operation around 0.6 V, achieving up to 2x improvement in energy efficiency for logic circuits by reducing both dynamic and static power dissipation.^[63] In advanced nodes such as 7 nm FinFETs, the integration of metal gates has contributed to power-efficient scaling for high-performance computing, as highlighted in projections from the International Roadmap for Devices and Systems (IRDS) 2020 edition, which emphasizes the role of replacement metal gate (RMG) processes.^[65] Despite these advantages, fabricating metal gates presents notable challenges, particularly thermal budget mismatches during integration. Metals typically exhibit stability limits below 500°C, while source/drain activation requires annealing at around 1000°C; this conflict is addressed through RMG processes, where the metal is deposited after high-temperature steps to preserve material integrity.^[66] Another key issue is Fermi level pinning at the metal-high-k dielectric interface, which arises from metal-induced gap states and complicates precise work function tuning for CMOS compatibility.^[67] As devices scale toward 1 nm effective channel lengths, interface traps at the metal-gate stack become a critical hurdle, leading to degraded carrier mobility and increased variability in nanoscale FinFETs and beyond.^[68] Recent 2025 research explores mitigating these issues by incorporating metal gates with 2D channel materials like MoS_2, where in-plane or electrostatic gating configurations demonstrate improved doping control and reduced trap-induced hysteresis, potentially enabling sub-1 nm scalability with mobilities comparable to bulk silicon.^[69] Widespread adoption of metal/high-k gate stacks has occurred in advanced nodes since their introduction in high-volume manufacturing around the 45 nm node, including in Apple's M-series processors. However, fabrication yields in these leading-edge processes face challenges due to metal fill defects, such as voids or incomplete deposition in high-aspect-ratio trenches, necessitating advanced metrology and process optimization.^[65]

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[39]
[PDF] Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to ...
We have implemented 1.2nm physical SiO2 in our 90nm logic technology node [1], and have scaled physical SiO2 further down to 0.8nm and integrated it in research ...Missing: ITRS | Show results with:ITRS<|separator|>
[40]
[PDF] OVERALL ROADMAP TECHNOLOGY CHARACTERISTICS
Both the printed and physical gate length trends remain unchanged for the 2003 ITRS, and are forecast to continue scaling by about 70% per two-year cycle ...
[41]
Effect of boron penetration on the stress induced leakage current in ...
Boron penetration increases stress-induced leakage current (SILC) and decreases charge to breakdown in PMOS structures, increasing trap creation efficiency.
[42]
[PDF] gate Dielectric Process technology for the sub-1 nm equivalent ...
Scaling below ~1 nm for higher-performance devices and lower than ~1.5 nm for lower-power devices also became limited by poly-silicon depletion as well as gate ...
[43]
High-K Dielectric - an overview | ScienceDirect Topics
While MOSFETs have been realized at 1.5 nm oxide thickness, a major obstacle to overcome is the high level of direct tunneling current through the gate. One ...
[44]
[PDF] Electrical Properties of Compositional Al2O3 Supplemented HfO2 ...
Sep 16, 2022 · Hafnium oxide (HfO2) is technologically im- portant material due to its high dielectric constant (k = 20 - 25), high bulk mod- ulus, great ...
[45]
[PDF] High-K materials and Metal Gates for CMOS applications
The SiO2 layer used as the gate dielectric is now so thin (~1.2 nm) that the gate leakage current due to direct tunnelling of electrons through the SiO2 ...
[46]
Under the Hood: Intel's 45-nm high-k metal-gate process - EE Times
Nov 14, 2007 · It may seem odd that the introduction of high-k gate dielectrics has not reduced the equivalent oxide thickness (EOT) of Intel's 65-nm SiON.
[47]
[PDF] A 45nm Logic Technology with High-k+Metal Gate Transistors ...
In this work high-k + metal gate integration challenges are overcome (Fig. 2), enabling a return to 0.7X TOX(e) scaling while simultaneously reducing gate ...Missing: Penryn | Show results with:Penryn<|control11|><|separator|>
[48]
Origin of flat band voltage shift in HfO2 gate dielectric with La2O3 ...
It has also been reported that the choice of a high-k has a large impact on Vth shift, for example, an ultra-thin La2O3 capping layer on a HfO2 layer can ...Missing: Vth adjust
[49]
(PDF) A 45nm Logic Technology with High-k+Metal Gate Transistors ...
A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process.
[50]
Work Function Setting in High-k Metal Gate Devices | IntechOpen
As transistor size continues to shrink, SiO2/polysilicon gate stack has been replaced by high-k/metal gate to enable further scaling.
[51]
Metal gates for advanced sub-80-nm SOI CMOS technology
The optimal gate workfunction for the 50 nm technology node is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS).
[52]
Statistical modeling of metal-gate Work-Function Variability in ...
For instance, four types of metal nitride gate materials (TiN and TaN for NMOS and WN and MoN for PMOS devices) are studied and it is shown that TiN and WN ...
[53]
(PDF) Molybdenum as a Gate Electrode for Deep Sub-Micron CMOS ...
Aug 6, 2025 · Preliminary results indicate that the work function of Mo can be varied over the range of 4.0-5.0V by a combination of suitable post-deposition ...
[54]
[PDF] On the Thermal Stability of Atomic Layer Deposited TiN as Gate ...
The work function of ALD TiN depends strongly on the an- nealing condition. Annealing in pure up to 1000 C lowers the work function by about 0.3–0.5 eV.
[55]
Work function engineering using lanthanum oxide interfacial layers
Aug 6, 2025 · A La 2 O 3 capping scheme has been developed to obtain n -type band-edge metal gates on Hf-based gate dielectrics.
[56]
Impact of gate workfunction on device performance at the 50 nm ...
Sub-100 nm CMOS generations may need metal gates to counter poly-depletion, boron penetration, high poly-sheet resistance and potentially for compatibility ...<|control11|><|separator|>
[57]
[PDF] Intel's Revolutionary 22 nm Transistor Technology
Intel is introducing revolutionary Tri-Gate transistors on its. 22 nm logic technology. • Tri-Gate transistors provide an unprecedented combination.Missing: RMG HfO2
[58]
Samsung Begins Chip Production Using 3nm Process Technology ...
Jun 30, 2022 · Optimized 3nm process achieves 45% reduced power usage, 23% improved performance and 16% smaller surface area compared to 5nm process.
[59]
Atomic Layer Deposition (ALD) of Metal Gates for CMOS - MDPI
To reach threshold voltage (Vt) target, extreme care needs to be taken, because Vt is so sensitive to interfacial states that any slight difference in chemical ...<|separator|>
[60]
Area-Selective Atomic Layer Deposition of TiN Using Aromatic ...
Aug 13, 2020 · A plasma-assisted ALD process for area-selective deposition of TiN was developed, which involves dosing of inhibitor molecules at the start of every ALD cycle.
[61]
IEDM 2019 - TSMC 5nm Process - SemiWiki
Dec 16, 2019 · Moving from 7nm to 5nm Samsung has disclosed a 1.33x density improvement and TSMC has disclosed a ~1.84x density improvement. Clearly TSMC will ...
[62]
Novel Atomic Layer Processes for Semiconductor Manufacturing
Sep 15, 2025 · In this review, we examine emerging atomic layer processes: area-selective deposition (ASD), atomic layer annealing (ALA), and atomic layer ...
[63]
[PDF] Device Scaling of High Performance MOSFET with Metal Gate High ...
Our results show that aggressive channel length scaling continually provides transistor performance gain with the use of metal gate high-k technology. A band ...
[64]
Device scaling of high performance MOSFET with metal gate high-K ...
The use of a metal gate (rather than a polysilicon one) prevents poly depletion, eliminates the V th pinning problem that occurs with poly on high-k dielectrics ...
[65]
international roadmap - 2020 EDITION
Strained silicon, high-κ/metal gate, FinFET, and use of other semiconductor materials (e.g., germanium) represented the main features of this scaling ...
[66]
Gate stack technology for nanoscale devices - ScienceDirect.com
Mobility degradation arising from the metal electrode/3 nm HfO2 reaction can be recovered by hydrogen passivation, indicating that the increased Dit shown in ...
[67]
Overcoming the Fermi-Level Pinning Effect in the Nanoscale Metal ...
The removal of Fermi-level pinning effectively reduces the Schottky barrier height by 12.5% to 16%. The demonstrated devices exhibit a high responsivity of up ...
[68]
Estimation of performance degradation due to interface traps in the ...
Sep 12, 2025 · Device reliability issues originating from interface traps or bias temperature instability has been of great concern in emerging devices ...
[69]
Gating monolayer and bilayer graphene with a two-dimensional ...
Apr 7, 2025 · Here, we investigate the viability of using 2D transition metal dichalcogenides (MoS2. MoSe2, WS2, WSe2) as an electrostatic gate for monolayer ...
[70]
[PDF] Apple 2025 Environmental Progress Report
High adoption rates are a clear signal that customers value software updates. By January 2025, more than 75 percent of all iPhone devices introduced in the ...Missing: drop defects