22 nm process
The 22 nm process refers to a semiconductor manufacturing technology node, primarily pioneered by Intel, that utilizes a 22-nanometer feature size to fabricate integrated circuits with enhanced transistor density and efficiency.[1] Introduced in 2011, it marked a significant advancement by replacing traditional 2D planar transistors with 3D Tri-Gate transistors, which feature a vertical silicon fin surrounded by gates on three sides for superior electrostatic control and reduced leakage.[2] This innovation enabled high-volume production starting in late 2012, sustaining Moore's Law through denser packing and improved scaling.[1] Key technical features of Intel's 22 nm process include Tri-Gate transistors that deliver up to 37% higher performance at low operating voltages and more than 50% reduction in active power consumption compared to the preceding 32 nm planar technology.[2] The process achieved transistor densities exceeding 2.9 billion per die in demonstrations, such as a 364 Mbit SRAM array, while maintaining compatibility with existing high-k metal gate structures from prior nodes.[2] These improvements allowed for lower voltage operation, minimizing dynamic power and enabling more energy-efficient devices without sacrificing speed.[1] The 22 nm process was first implemented in Intel's Ivy Bridge microprocessors, part of the Core family, which powered laptops, desktops, and servers launched in 2012.[1] Subsequent generations, including Haswell in 2013, further refined the node for broader applications like chipsets and low-power components.[3] While Intel led its development, variants emerged from other foundries; for instance, TSMC's 22 nm ultra-low-power (22ULP) process, derived from 28 nm technology, targeted mobile and embedded applications with optimized performance-per-watt metrics.[4] GlobalFoundries also pursued a 22 nm fully depleted silicon-on-insulator (FD-SOI) node to compete in low-power segments.[3] The adoption of the 22 nm process significantly influenced the semiconductor industry by popularizing finFET-like (Tri-Gate) architectures, paving the way for sub-20 nm scaling in later nodes and driving innovations in mobile computing, data centers, and embedded systems.[2] Its legacy persists, with revived production for legacy components amid 14 nm supply constraints in 2019,[5] and continued use in specialized applications into the 2020s, such as UMC's 22 nm embedded high-voltage (eHV) platform launched in 2024 and Samsung's 22 nm mobile display driver ICs introduced in 2025.[6][7] Overall, the node exemplified a shift toward 3D transistor designs, balancing performance gains with power efficiency to meet escalating demands for portable and high-performance electronics.[1]Overview
Definition and scaling
The 22 nm process node represents a generation in semiconductor manufacturing where the nomenclature "22 nm" primarily denotes the targeted physical gate length of MOSFET transistors or the minimum metal half-pitch for interconnects, rather than a literal measurement of all device dimensions. This naming convention evolved from earlier nodes, where feature sizes like gate length and half-pitch were more closely aligned, but by the 22 nm era, it served as a marketing and roadmap identifier for overall scaling progress. According to the International Technology Roadmap for Semiconductors (ITRS) 2008 update, the 22 nm node targeted a physical gate length of approximately 22 nm, while metal 1 half-pitch was specified around 38 nm for microprocessor units (MPUs) in 2011.[8][9] This node achieved scaling through an approximate 0.7x linear dimension reduction from the preceding 32 nm process, which had a physical gate length of about 27 nm and metal half-pitch near 52 nm, resulting in roughly 2x higher transistor density per unit area. Such scaling adhered to Moore's Law principles by enabling more transistors on a chip while managing power and performance trade-offs, though the pace of shrinkage began to moderate due to physical limits in planar transistor designs. In practice, implementations like Intel's 22 nm process featured typical gate lengths of 30-34 nm and a contacted poly pitch of 90 nm, providing concrete metrics for this density gain.[8][10] Within the ITRS roadmap, the 22 nm node was positioned as a full technology generation succeeding the 32 nm node (introduced around 2009) and preceding the 14 nm node (around 2014), with production anticipated for 2011-2012. It marked a pivotal point emphasizing the transition from traditional planar transistors to 3D architectures, such as tri-gate FinFETs, to sustain scaling beyond classical limits while improving electrostatic control and reducing leakage. This shift addressed challenges in maintaining performance at sub-30 nm dimensions, aligning with ITRS projections for extended CMOS viability.[8][9][2]Historical timeline
The development of the 22 nm semiconductor process node built upon the prior evolution of planar transistor scaling, particularly Intel's introduction of the 32 nm process in 2009 with the Westmere family of processors, which marked the second generation of high-k metal gate technology and enabled initial production of chips integrating CPU and graphics cores.[11] This node was followed by the industry-wide adoption of the 28 nm half-node, a transitional shrink from 32 nm that improved density and performance without a full architectural overhaul; Taiwan Semiconductor Manufacturing Company (TSMC) became the first foundry to offer 28 nm general-purpose technology in 2011, with variants optimized for high-performance and low-power applications entering volume production shortly thereafter.[12] In May 2011, Intel unveiled its 22 nm process technology at the Intel Developer Forum, demonstrating the world's first 3-D tri-gate transistors designed to overcome planar scaling limitations by enhancing gate control and reducing leakage.[13] Later that year, at the International Electron Devices Meeting (IEDM) in December 2011, Intel presented joint research papers highlighting advancements in tri-gate architectures, including scalability for low-power III-V field-effect transistors, underscoring the technology's potential for future nodes.[14] Intel initiated high-volume manufacturing of 22 nm chips in the second quarter of 2012, with the Ivy Bridge processors representing the first commercial implementation, launching in April of that year and delivering significant improvements in performance-per-watt over the preceding 32 nm generation.[15] In parallel, other foundries advanced their 22 nm efforts; TSMC announced its 22 nm ultra-low-power (ULP) process in 2017, targeting mobile and IoT applications, with mass production commencing in 2018 to provide a planar-compatible option derived from its 28 nm platform.[3] Around 2014, GlobalFoundries began development of its 22FDX fully depleted silicon-on-insulator (FD-SOI) variant, culminating in the platform's official launch in July 2015 as a low-power alternative emphasizing energy efficiency for automotive and connected devices.[16] By 2013, the 22 nm node signified the broader industry's transition away from widespread planar transistor use at leading edges, as Intel's tri-gate adoption accelerated the shift toward multi-gate 3-D structures to sustain Moore's Law amid diminishing returns from traditional scaling.[17]Technical features
Transistor architecture
The 22 nm process introduced a pivotal advancement in transistor architecture through Intel's adoption of Fin Field-Effect Transistors (FinFETs) in a tri-gate configuration, marking the industry's first commercial implementation of 3D transistor structures for logic devices. This design features a vertical silicon fin serving as the channel, with the gate electrode wrapping around three sides—top and two lateral surfaces—for superior channel control compared to traditional 2D planar MOSFETs. The fin dimensions typically include a height of approximately 30 nm and a width of 8-10 nm, enabling fully depleted operation that minimizes leakage while maximizing performance in high-volume manufacturing.[2][18] In contrast to planar transistors, the tri-gate FinFET significantly reduces short-channel effects such as drain-induced barrier lowering and improves electrostatic integrity by increasing the gate-to-channel coupling, allowing for better scalability at advanced nodes. This architectural shift results in enhanced gate capacitance due to the expanded effective channel perimeter, which can be approximated by the formulaC_{\text{gate}} = \epsilon_{\text{ox}} \cdot \frac{ L_{\text{gate}} (2 H_{\text{fin}} + W_{\text{fin}} ) }{ t_{\text{ox}} },
where \epsilon_{\text{ox}} represents the oxide permittivity, H_{\text{fin}} and W_{\text{fin}} are the fin height and width, t_{\text{ox}} is the oxide thickness (or equivalent oxide thickness for high-k dielectrics, approximately 0.9 nm), and L_{\text{gate}} is the gate length. The increased capacitance supports higher drive currents and faster switching speeds, with NMOS transistors achieving approximately 1.0 mA/μm under typical operating conditions.[2][19][20] Intel's tri-gate FinFET differs from double-gate variants explored in other implementations, where the gate controls only two sides of the fin, potentially offering simpler fabrication but reduced electrostatic control. To further optimize performance, embedded silicon-germanium (eSiGe) stressors are integrated into the source and drain regions of PMOS transistors, providing a compressive strain that boosts hole mobility by about 30% and enhances overall PMOS drive strength. These innovations collectively enable the 22 nm tri-gate architecture to deliver up to 37% performance improvement at low voltages relative to the preceding 32 nm planar technology.[2][21][10]