3 nm process
The 3 nm process is a semiconductor manufacturing technology node that represents a major advancement in integrated circuit fabrication, enabling transistors with critical dimensions scaled to around 3 nanometers for higher density, enhanced performance, and reduced power consumption compared to the preceding 5 nm node.[1] This node, while not literally measuring all features at 3 nm, serves as a generational marker for process improvements in logic scaling, typically achieving 25-35% lower power usage or 10-15% higher performance at the same power, alongside up to 1.7 times greater transistor density.[2] Leading foundries like TSMC, Samsung, and Intel have commercialized variants of the 3 nm process, with TSMC's 3nm contributing about 23% of its revenue by Q3 2025, powering high-end applications in mobile devices, servers, and AI accelerators.[3][4][5][6] TSMC's N3 family, including enhancements like N3E and N3P, utilizes fin field-effect transistor (FinFET) architecture as its last major iteration before transitioning to gate-all-around (GAA) at smaller nodes, with mass production beginning in late 2022 and high-volume yields nearly 90% by mid-2025.[3][1][7] Samsung's 3 nm process, branded as SF3, employs multi-bridge-channel FET (MBCFET) GAA nanosheet transistors for superior channel control and scaling, entering production in June 2022 with reported improvements of 45% reduced power, 23% higher performance, and 16% smaller area over its 5 nm node, though yields have lagged at around 50-60% as of mid-2025.[4][1][8] Intel's Intel 3 process, also FinFET-based, delivers an 18% performance-per-watt gain over its Intel 4 node (equivalent to a 5 nm-class process) and entered high-volume manufacturing in 2024, targeting datacenter and high-performance computing with support for 1.2V operations and denser libraries.[5][1] These processes mark a critical tipping point for transistor evolution, as FinFETs approach physical limits in controlling short-channel effects and leakage, prompting the shift to GAA structures for future nodes while enabling denser interconnects at pitches like 48 nm contacted poly and 22 nm metal.[1] Notable implementations include Apple's A17 Pro, M4, and A18 chips on TSMC's N3, Samsung's Exynos 2500 processor on SF3, and Intel's Xeon 6 server CPUs on Intel 3, underscoring the node's role in driving efficiency for energy-intensive AI and mobile workloads.[3][4][5][9][10]History
Early research and development
The progression toward the 3 nm process was foreshadowed by the International Technology Roadmap for Semiconductors (ITRS) editions from 2011 to 2015, which outlined escalating challenges in scaling CMOS transistors from 5 nm and larger nodes. These roadmaps predicted that sub-5 nm dimensions would encounter severe short-channel effects, increased leakage currents, and limitations in classical planar and early FinFET architectures, necessitating innovations in device structures and materials to sustain performance gains.[11] By 2015, the ITRS emphasized the urgency of transitioning to multi-gate devices like gate-all-around (GAA) transistors to improve electrostatic control and enable continued density scaling beyond 5 nm.[12] Research milestones in the mid-2010s focused on evolving FinFETs toward GAAFET concepts, particularly through lab demonstrations of nanowire and nanosheet architectures. IBM researchers first introduced the stacked nanosheet GAAFET in 2015 as a viable path for sub-5 nm scaling, offering superior gate control over FinFETs by fully surrounding the channel with the gate dielectric.[13] Building on this, IMEC advanced the technology with 2016 demonstrations of lateral silicon nanowire GAA MOSFETs at scaled dimensions below 20 nm, highlighting their potential for ultimate CMOS scaling with reduced variability and enhanced drive currents.[14] By 2018, IMEC reported further refinements in stacked nanowire GAA transistors, achieving improved Ion/Ioff ratios and short-channel effect suppression suitable for 3 nm nodes and beyond.[15] Early material innovations in the 2010s laid groundwork for 3 nm viability by addressing gate stack and patterning limitations inherited from larger nodes. High-k metal gate (HKMG) stacks, initially commercialized at 45 nm, underwent extensive refinement during this decade for FinFET integration and GAA compatibility, enabling equivalent oxide thicknesses below 1 nm while minimizing quantum tunneling and threshold voltage variability at sub-5 nm scales.[16] Concurrently, precursors to extreme ultraviolet (EUV) lithography were tested in research settings, with developments in 13.5 nm wavelength sources and photoresists demonstrating sub-20 nm resolution and overlay precision under 5 nm, critical for single-exposure patterning in dense 3 nm layouts. Specific lab prototypes underscored these advancements' feasibility. In 2016, IMEC showcased 3 nm-class GAA prototypes using nanowire channels, validating multi-gate control for high-mobility channels at aggressive pitches.[14] Complementing this, TSMC's 2018 research on EUV integration confirmed its viability for 3 nm processes, with demonstrations of enhanced light-source power and multi-layer patterning that supported faster development cycles and reduced multi-patterning complexity compared to 5 nm approaches.[17]Technology demonstrations and announcements
In December 2019, TSMC presented a short course at the International Electron Devices Meeting (IEDM) outlining device technologies for 3 nm and beyond, including EUV lithography integration for enhanced scaling and initial test chip concepts demonstrating feasibility for high-density logic and SRAM structures.[18] Building on this, TSMC advanced its 3 nm development in 2020 with EUV-based test chips entering risk production, validating key process modules like multi-patterning and contact gate pitch scaling to achieve up to 1.7x transistor density over the 5 nm node while maintaining yield targets.[19] In January 2020, Samsung announced the fabrication of the world's first 3 nm gate-all-around FET (GAAFET) prototype using its multi-bridge-channel FET (MBCFET) architecture, which demonstrated a 30% transistor density improvement over its 5 nm process through better channel control and reduced short-channel effects.[20] In July 2021, Intel revealed RibbonFET, its implementation of gate-all-around transistor technology, as part of the Intel 20A process node—equivalent to a 3 nm class—aimed at delivering superior drive current and electrostatic integrity compared to FinFETs, with initial prototypes showing enhanced performance-per-watt metrics.[21] Concurrently, TSMC and Arm collaborated on 3 nm test vehicles, culminating in a successful tape-out of a test chip validating Armv9 physical IP, which included silicon results confirming robust power delivery networks with low IR drop and up to 10-15% efficiency gains in high-performance computing blocks.[22] At IEDM 2022, IMEC showcased a 3 nm-class nanosheet FET device, highlighting the architecture's potential for low-power applications through precise nanosheet width control and inner-spacer optimization.[1] During the 2022 TSMC Technology Symposium, TSMC demonstrated the N3E process variant with FINFLEX for flexible cell architectures while preserving compatibility with existing FinFET flows.[23]Commercialization timeline
TSMC initiated risk production of its 3 nm N3 process in 2021, marking the early stages of commercialization ahead of high-volume manufacturing.[24] This was followed by the start of high-volume manufacturing for N3 in the second half of 2022, with the process entering production for Apple's A17 Pro chip in high-performance computing and smartphone applications by late 2023.[3] Samsung Electronics began high-volume manufacturing of its first-generation 3 nm gate-all-around (GAA) process in mid-2022, initially targeting the Exynos series, though persistent yield challenges limited its adoption.[25] In 2023, TSMC ramped up its enhanced N3E variant, which saw its first tape-out with MediaTek for a flagship Dimensity chipset, enabling broader smartphone integration by 2024.[26] Samsung encountered significant yield issues with its 3 nm process during 2022-2023, reportedly below 20% initially, prompting major customers like Qualcomm to shift orders to TSMC's more reliable N3 platform.[8] Intel's equivalent 20A process, planned as a 2 nm-class node, faced delays and was ultimately canceled for consumer production in 2024, with manufacturing shifted to external foundries like TSMC.[27] By 2024, Samsung advanced to trial production of its second-generation 3 nm SF3 process, aiming for mass production in the second half of the year to address prior yield shortcomings.[28] In May 2025, Xiaomi announced its in-house XRING O1 chipset, fabricated on TSMC's N3E node, representing a key milestone in diversified 3 nm adoption for mobile processors.[29] Market events included Alchip Technologies' tape-out of a 3D IC test chip integrating 3 nm and 5 nm dies in September 2025, validating ecosystem readiness for advanced packaging.[30] TSMC further expanded 3 nm capacity in 2025, driven by AI chip demand from NVIDIA, increasing monthly wafer output to support high-performance computing growth.[31] In early 2025, Intel's Intel 3 process entered high-volume manufacturing, targeting datacenter applications with Xeon 6 processors.[32]Technology
Key innovations in transistor design
The 3 nm process involves advancements in transistor architecture, with some implementations shifting from fin field-effect transistors (FinFETs) to gate-all-around (GAA) nanosheet field-effect transistors (FETs) to enable continued scaling beyond the limitations of FinFETs at sub-5 nm nodes. Other implementations, such as TSMC's N3 family and Intel's Intel 3, refine FinFET designs through optimizations like narrower fin pitches (around 24-26 nm) and higher aspect ratios to enhance electrostatic control and reduce short-channel effects without transitioning to GAA.[3][5] In GAA nanosheet FETs, the channel is formed by multiple horizontally stacked silicon nanosheets, typically 3 to 5 layers thick, with the gate material fully encircling each nanosheet on all four sides. This all-around gate configuration provides enhanced electrostatic control over the channel, significantly reducing short-channel effects such as drain-induced barrier lowering and leakage currents compared to the partial gate wrapping in FinFETs. The stacked nanosheet design also allows for tunable device characteristics by varying the number and dimensions of the sheets, optimizing drive strength while maintaining compact footprints suitable for 3 nm densities.[33] Key implementations of GAA technology at 3 nm include Samsung's multi-bridge-channel FET (MBCFET), which employs stacked horizontal nanosheets as the conductive channels, enabling precise adjustment of channel width for balanced power, performance, and area (PPA) metrics. In MBCFET, the nanosheet structure facilitates higher current density through parallel conduction paths across the bridges, with demonstrated improvements of 23% in performance and 45% in power efficiency over preceding 5 nm FinFET-based processes. TSMC's N3X variant incorporates a backside power delivery network (BSPDN), relocating power rails to the wafer's underside to minimize IR drop and improve signal integrity in high-performance applications, thereby supporting higher operating voltages up to 1.2 V without compromising frontside routing density.[4][34] Interconnect innovations at 3 nm address rising resistance in narrow copper lines by adopting ruthenium-cobalt (Ru/Co) bilayer liners, which reduce liner thickness by up to 33% while enhancing copper wettability and void-free filling. These liners lower overall interconnect resistance by approximately 14% at pitches below 20 nm, mitigating RC delay increases that plague traditional tantalum-based barriers. To achieve such tight interconnect dimensions, extreme ultraviolet (EUV) lithography with multi-patterning techniques, such as self-aligned litho-etch processes, enables metal pitches as low as 24 nm, ensuring precise patterning of backend-of-line (BEOL) layers without excessive overlay errors.[35][36] The scaling benefits of GAA nanosheet FETs are quantified through the effective channel width, defined asW_{\text{eff}} = 2 \times (W + H) \times N
where W is the nanosheet width, H is the nanosheet thickness (or height), and N is the number of stacked nanosheets. This formulation allows designers to boost drive current by increasing N or sheet dimensions, yielding up to a 30% improvement in on-state current over equivalent FinFET structures at iso-area conditions, primarily due to enhanced gate-to-channel coupling and reduced source/drain resistance.[37][38]