2 nm process
The 2 nm process is an advanced semiconductor fabrication technology that enables the production of integrated circuits with transistor gate lengths and densities equivalent to approximately 2 nanometers, achieving unprecedented scaling in transistor count per chip while enhancing performance and energy efficiency. This node represents a critical evolution from prior generations like 3 nm, primarily through the adoption of gate-all-around (GAA) transistor designs—such as nanosheets, multi-bridge-channel FETs (MBCFETs), or RibbonFETs—which encircle the channel on all sides for superior electrostatic control, reduced leakage, and improved drive current compared to FinFET architectures.[1][2][3] Leading semiconductor foundries are at the forefront of 2 nm development, with both TSMC and Samsung having initiated production on their respective nodes as of late 2025. Taiwan Semiconductor Manufacturing Company (TSMC) pioneered its N2 node using first-generation nanosheet GAA transistors and innovations like Nanoflex for customizable sheet widths across logic cells. TSMC's N2 delivers up to a 15% higher performance or 30% lower power consumption at iso-speed compared to its N3E process, alongside a 15% increase in logic density and the industry's densest SRAM cell at 38 Mb/mm², an 11% improvement over N3. Risk production began in July 2024, with high-volume manufacturing beginning in late 2025 and over 15 major customers, primarily in high-performance computing (HPC) and AI, already committed.[4][1][5][6] Samsung Electronics advanced its SF2 (2 nm) process with MBCFET GAA technology, emphasizing stability and yield improvements to compete in mobile and HPC applications, including turnkey solutions for AI chiplets and advanced packaging like I-Cube. The company began mass production in 2025, initially for mobile devices, with expansion to HPC in 2026 and automotive by 2027, while prioritizing sub-3 nm enhancements over more aggressive 1.4 nm scaling. Early demonstrations include integration with Arm architectures for AI data centers, underscoring Samsung's focus on ecosystem partnerships.[7][8][9][10] The 2 nm process addresses escalating demands from artificial intelligence, machine learning, and edge computing, where higher density supports more complex neural networks and faster inference, while power efficiencies mitigate thermal challenges in data centers and devices. Global market projections indicate the 2 nm and beyond segment will expand from USD 29 billion in 2025 to USD 91.5 billion by 2034, driven by AI/HPC growth.[11][12]Historical Context
Evolution of Process Nodes
The semiconductor process node, commonly known as the "node," serves primarily as a marketing designation that reflects advancements in transistor density and overall feature scaling, rather than a precise measurement of physical dimensions like gate length; this disconnect became pronounced starting with the 22 nm node, where actual gate lengths exceeded the nominal node size.[13] This progression has been driven by foundational principles such as Moore's Law and Dennard scaling. Moore's Law, first articulated by Gordon E. Moore in 1965 and revised in 1975, observes that the number of transistors in an integrated circuit doubles approximately every two years (originally stated as every year, later adjusted to 18-24 months), enabling exponential growth in computational capability; mathematically, this is expressed as N(t) = N_0 \cdot 2^{t / \tau} where N(t) is the transistor count at time t, N_0 is the initial count, and \tau is the doubling period of 2 years (or 18-24 months).[14] Dennard scaling, proposed by Robert H. Dennard and colleagues in 1974, supported this trend by predicting that uniform reduction of all transistor dimensions by a factor k, along with proportional scaling of voltage and current, would keep power density constant, allowing chips to run faster without excessive heat. The historical evolution of process nodes traces a relentless shrinkage from early micrometer-scale technologies in the 1970s—such as the 10 μm node used in Intel's 4004 microprocessor—to sub-5 nm regimes today, embodying Moore's Law through decades of innovation. By the 1990s, nodes reached 500 nm and 250 nm, enabling denser logic and memory; the 130 nm node in 2001 marked widespread adoption of copper interconnects, while 90 nm in 2004 introduced strained silicon for performance gains. Further scaling to 65 nm (2006), 45 nm (2008), and 32 nm (2009) refined high-k metal gate materials to mitigate leakage.[15] More recent nodes accelerated density improvements: the 10 nm process debuted commercially in 2017 with Samsung's implementation, achieving transistor densities around 100 million transistors per square millimeter (MTr/mm²). The 7 nm node followed in 2018 from TSMC and Samsung, offering densities of approximately 96-140 MTr/mm² and supporting complex SoCs like Apple's A12. TSMC's 5 nm node entered production in 2020, reaching ~170 MTr/mm², a key enabler for high-performance mobile and AI chips. By 2022, the 3 nm node from both Samsung and TSMC pushed densities beyond 200 MTr/mm², sustaining scaling trends amid physical limits.[16] A pivotal architectural shift occurred with the transition from planar transistors to FinFET (fin field-effect transistor) designs at the 22 nm node, pioneered by Intel in 2011, which improved gate control over the channel to reduce leakage and enhance drive current in shorter channels. This was further advanced at the 3 nm node with the introduction of gate-all-around FETs (GAAFETs) by Samsung, providing fuller channel encirclement and serving as a bridge to 2 nm architectures.[17]Precursors to 2 nm
The 3 nm process node represented a critical step in semiconductor scaling, with leading foundries achieving mass production in 2022 and focusing on enhanced density and efficiency. TSMC's N3 process entered high-volume manufacturing that year, delivering up to a 1.6× logic density improvement over its 5 nm predecessor while reducing power by 30-35% at iso-speed.[18] Samsung's 3GAA process, the industry's first commercial gate-all-around (GAA) implementation, began production in mid-2022, providing 45% lower power consumption, 23% higher performance, and 16% reduced area compared to its 5 nm node.[17] Intel's Intel 3 node, a FinFET-based evolution of Intel 4 with extensive EUV usage, achieved high-volume production by 2024, offering 18% better performance at the same power and approximately 10% higher density.[19][20] These developments addressed scaling challenges like short-channel effects through refined FinFET and early GAA structures, building on gate-all-around field-effect transistors (GAAFETs) refined from 5 nm demonstrations. Experimental work on sub-3 nm technologies directly informed 2 nm designs, with research institutions pioneering prototypes to overcome electrostatic and interconnect limitations. In 2021, Imec presented nanosheet FET prototypes targeting 2.5 nm-class nodes at the VLSI Symposium, utilizing stacked silicon nanosheets in GAA configurations to achieve gate pitches below 45 nm and superior channel control over FinFETs. These devices demonstrated improved drive currents and reduced leakage, enabling tighter scaling for logic applications while mitigating quantum tunneling issues at sub-30 nm dimensions. Such prototypes highlighted the feasibility of multi-sheet GAA architectures for densities exceeding 300 MTr/mm², paving the way for commercial adoption. Power delivery innovations emerged as key enablers during 3 nm research, with backside power delivery networks (BSPDN) first prototyped to alleviate frontside routing congestion. Imec's early BSPDN tests at 3 nm scales showed a ~1.7× reduction in IR drop compared to conventional frontside delivery, equivalent to 20-30% voltage stability gains under high current loads.[21] By routing power rails through the wafer backside, these concepts minimized resistance in metal layers, allowing up to 30% power savings and supporting denser transistor arrays without excessive heat or noise. Lithography advancements from the 3 nm era extended EUV capabilities to support sub-3 nm pitches, with high-NA EUV systems developed as a bridge to finer features. Building on low-NA EUV (0.33 NA) used in 3 nm production, high-NA EUV at 0.55 NA enabled single-exposure patterning for 8 nm resolutions, reducing multi-patterning complexity and edge placement errors.[22] These extensions, explored in collaborative efforts by ASML and Imec, addressed stochastic noise and throughput limits, ensuring viable scaling paths for 2 nm interconnects and contacts.Development Timeline
Key Announcements and Milestones
In 2021, TSMC publicly unveiled its roadmap for the N2 process node, targeting high-volume manufacturing in 2025 and incorporating gate-all-around (GAA) nanosheet transistor technology as a successor to FinFETs.[23] Similarly, Samsung announced its SF2 2 nm process node on October 7, featuring multi-bridge-channel FET (MBCFET) transistors, with plans for mass production beginning in 2025 to support applications in big data, AI, and connected devices.[24] By 2023, Intel updated its process roadmap to include the 20A node—equivalent to a 2 nm-class technology—initially slated for manufacturing ramp-up in 2024, introducing RibbonFET GAA transistors; however, the node has been largely superseded by the 18A process for 2025 production, with 20A limited to select foundry offerings amid challenges in development and yield optimization.[25][26] In 2024, TSMC initiated risk production of its N2 process in July, marking a key step toward full-scale manufacturing and validating process stability ahead of customer tape-outs.[27] That same year, Imec released a pathfinding process design kit (PDK) for 2 nm technology in February, enabling early design exploration and prototyping for sub-2 nm nodes through collaborative efforts with industry partners.[28] Entering 2025, TSMC achieved a major milestone by completing pilot production of the N2 process in the first quarter, attaining yield rates exceeding 90% and paving the way for volume production in the second half of the year.[29] Meanwhile, Samsung resumed construction investments for its Taylor, Texas facility in August, accelerating preparations to support 2 nm process mass production targeted for 2026 and addressing prior delays in customer commitments.[30][31]Recent Advancements as of 2025
In 2025, TSMC ramped up its 2 nm (N2) process toward mass production in the second half of the year, following risk production trials initiated in 2024. Pilot yields for the N2 process exceeded 90% by mid-year, enabling a smooth transition to volume manufacturing at facilities in Taiwan; as of November 2025, initial mass production has begun in Q4, with full capacity for 2026 already allocated to customers.[32][33] The enhanced N2P variant, focusing on performance and efficiency optimizations without backside power delivery, began preparation for deployment in late 2026, targeting further improvements in power efficiency for AI and high-performance computing applications, with backside power delivery planned for the A16 node.[34][35] Samsung Electronics commenced mass production of its SF2 2 nm process in the fourth quarter of 2025 at facilities in South Korea, with yields reaching 50-60% by November and initial output focused on AI accelerators and mobile processors, such as the Exynos 2600 chipset for the Galaxy S26 series; the Taylor, Texas plant is preparing for additional capacity in 2026.[36][10][37] Japan's Rapidus Corporation advanced construction of its 2 nm fabrication facility in Chitose, Hokkaido, achieving significant milestones including cleanroom completion and equipment installation by mid-2025, with test production of GAA transistors beginning in July 2025 and overall progress supporting mass production in 2027.[38] Global efforts to bolster 2 nm capabilities received substantial support through the U.S. CHIPS and Science Act, with over $20 billion allocated across grants for advanced semiconductor facilities, including $6.6 billion to TSMC's Arizona expansion and $6.4 billion to Samsung's Texas operations. These investments facilitated infrastructure builds and yield improvements essential for domestic 2 nm production.[39][40] In November 2025, Imec updated its 2 nm pathfinding PDK with advanced SRAM memory macros, enhancing support for next-generation system-on-chip designs.[41]Core Technologies
Transistor Innovations
The 2 nm process introduces gate-all-around field-effect transistors (GAAFETs) based on stacked horizontal nanosheets, marking a shift from the fin-shaped channels of earlier FinFET designs introduced around the 7 nm node.[1] This architecture surrounds the channel on all four sides with the gate, enhancing electrostatic control and mitigating short-channel effects that limit scaling in prior technologies.[4] The nanosheet design stacks multiple thin silicon layers, typically 5-6 nm thick, to form the channel, allowing precise tuning of drive current while suppressing leakage currents compared to FinFETs. Samsung's implementation, known as the multi-bridge-channel FET (MBCFET), refines this GAAFET approach by employing up to four nanosheet bridges per fin structure, enabling flexible channel width adjustment for optimized performance in logic applications.[42] This multi-bridge configuration improves gate-to-channel coupling, further reducing off-state leakage and supporting the dense integration required at 2 nm scales.[3] Intel's RibbonFET, a GAAFET variant using stacked silicon nanowires, provides enhanced drive current and scaling for its 20A and 18A nodes.[43] A key benefit of these innovations lies in improved gate capacitance, governed by the formula C_g = \frac{[\epsilon](/page/Epsilon) \cdot A}{t_{ox}} where C_g is the gate capacitance, \epsilon is the permittivity of the gate dielectric, A is the effective gate area, and t_{ox} is the oxide thickness. Nanosheet designs effectively minimize the equivalent t_{ox} through enhanced conformal gate wrapping, boosting C_g and enabling lower supply voltages.Fabrication Methods
The fabrication of 2 nm process nodes relies on advanced lithography techniques to achieve the necessary feature resolution. High-numerical aperture (NA) extreme ultraviolet (EUV) lithography, with an NA of 0.55, enables single-patterning of critical layers at a 24 nm pitch, facilitating the creation of 2 nm-scale features.[44] These systems, developed by ASML, were first deployed to customers in 2025, marking a significant advancement over low-NA EUV for sub-2 nm scaling.[44] Power delivery in 2 nm fabrication incorporates a backside power delivery network (BSPDN), where power rails are positioned on the wafer's backside to decouple them from the frontside signal interconnects. This approach uses nano-through-silicon vias (nTSVs) or similar structures to connect power directly to transistors, enabling 15-20% improvements in power usage by reducing voltage drop (IR drop) compared to frontside-only configurations.[45] Such improvements enhance power integrity and enable denser layouts without excessive resistance losses. Gate dielectrics in 2 nm processes are formed using atomic layer deposition (ALD) to deposit ultra-thin hafnium oxide (HfO₂) layers with equivalent oxide thickness (EOT) below 1 nm while maintaining high dielectric constants for effective gate control.[46] ALD's precise, cycle-based growth ensures conformal coverage on complex three-dimensional structures, such as gate-all-around field-effect transistors (GAAFETs), minimizing leakage and supporting equivalent oxide thickness (EOT) scaling below 1 nm.[46] Interconnect scaling at 2 nm nodes addresses electromigration challenges through the adoption of ruthenium (Ru) and cobalt (Co) as liner materials in copper damascene processes, particularly for pitches around 20 nm. These metals provide better adhesion and barrier properties than traditional tantalum nitride, reducing liner thickness by up to 33% while improving resistance to electromigration and enabling lower overall resistivity at sub-20 nm dimensions.[47][48]Manufacturer Implementations
The following table summarizes key technical specifications for major 2 nm-class processes, based on available public data:| Manufacturer | Process | Gate Pitch (nm, est.) | Metal Pitch (nm) | Logic Density (MTr/mm²) | SRAM Density (Mb/mm²) | Performance Uplift (vs. prior node) | Power Reduction (vs. prior node) | Production Status |
|---|---|---|---|---|---|---|---|---|
| TSMC | N2 | ~45 | N/A | 313 | 38 | 15% | 30-35% | Mass production H2 2025 [49][50] |
| Samsung | SF2 | 44-48 | N/A | 231 | N/A | 5% | 8% | Mass production late 2025 [53] |
| Intel | 20A | N/A | N/A | N/A | N/A | N/A | N/A | Cancelled for foundry [54] |
| Intel | 18A | N/A | N/A | 238 | N/A | 25% | 36% | High-volume manufacturing 2025 [55][52] |
| Rapidus | 2 nm | N/A | ~28 | 237 | N/A | N/A | N/A | Prototypes 2025, mass 2027 [56][49] |
TSMC N2 Process
TSMC's N2 process represents a key advancement in its 2 nm-class technology, employing gate-all-around (GAA) nanosheet transistors to enable superior electrostatic control and reduced leakage compared to prior finFET designs. This architecture contributes to a 1.15 times increase in logic density over the N3E node, alongside up to 15% performance gains or 35% power reductions at iso-speed.[57][58] A distinguishing feature of the N2 process is its NanoFlex technology, which enables customizable nanosheet widths across logic cells for optimized performance and density. This innovation supports higher transistor densities while addressing scaling challenges in sub-3 nm nodes.[35][59] The N2 family includes variants tailored for specific workloads, with N2P slated for volume production in the second half of 2026 and delivering 18% speed uplift or 36% power savings over N3E at equivalent densities.[60][51] Early adoption of the N2 family includes MediaTek, which completed tape-out of its first 2 nm chip using the N2P variant in September 2025, positioning it as a pioneer among mobile SoC designers ahead of broader smartphone integrations. Mass production of N2 wafers is on track to commence in the second half of 2025, with initial capacity at 40,000 wafers per month ramping to support demand from mobile and AI sectors.[61][62] Pilot production yields for the N2 process have surpassed 90% for key modules like SRAM, reflecting mature process control despite the node's complexity. Wafer costs carry an initial 10-20% premium over 3 nm equivalents, priced around $30,000 per wafer to account for advanced lithography and materials, though economies of scale are expected to narrow this gap by 2027.[63][64]Samsung SF2 Process
Samsung's SF2 process represents the company's first-generation 2 nm semiconductor manufacturing node, leveraging second-generation multi-bridge-channel field-effect transistor (MBCFET) technology, which employs gate-all-around nanosheet structures to enhance transistor performance.[53] This architecture allows for tunable nanosheet widths, enabling optimized drive currents and reduced leakage compared to prior FinFET designs.[53] The SF2 node achieves a transistor density of approximately 231 million transistors per square millimeter, providing roughly 1.4 times the area scaling efficiency over Samsung's 3 nm process, which facilitates higher integration for complex chips.[65] Key performance enhancements include a 5% higher speed and 8% improved power efficiency relative to the second-generation 3 nm node (SF3), as announced in November 2025.[66] These gains position SF2 as a competitive option for high-performance computing and mobile applications, with initial mass production of chips like the Exynos 2600 commencing in late 2025. Mass production of SF2-based chips, such as the Exynos 2600, commenced in late 2025, with yields reaching approximately 50% as of November 2025.[10] To support expanded 2 nm production, Samsung has committed $17 billion to its Taylor, Texas fabrication facility, which resumed full construction in 2025 and is slated to ramp up output for AI-focused chips, including processors for partners like Tesla.[67] This U.S. expansion aims to bolster domestic manufacturing capacity, with initial 2 nm operations targeted for 2026 ahead of broader volume scaling in late 2026 or early 2027.[68] A pivotal partnership involves Qualcomm, which is testing samples of the Snapdragon 8 Elite Gen 5 manufactured on the SF2 process for potential future flagship mobile processors, with integration planned for 2026 devices such as the Galaxy Z Fold 8 and Z Flip 8.[69] This collaboration underscores SF2's viability for premium smartphones, potentially powering custom variants with enhanced AI capabilities.[70] Samsung has tackled fabrication challenges, particularly in extreme ultraviolet (EUV) lithography, through investments in advanced tools like high-NA EUV systems and process optimizations to mitigate stochastic defects—random variations in photon placement that can cause bridging or necking issues.[71] These efforts have elevated SF2 test yields from around 30% in early 2025 to over 50% by late in the year, with targets approaching 70% for stable mass production.[10] Compared to industry benchmarks like TSMC's N2 process, SF2 emphasizes aggressive pricing and U.S.-based scaling to capture market share in AI and mobile sectors.[72]Other Initiatives
Intel has cancelled its 20A process node, redirecting efforts to the subsequent 18A node, which incorporates RibbonFET gate-all-around (GAA) transistors and PowerVia backside power delivery network (BSPDN) to enhance performance and efficiency.[73] High-volume manufacturing of 18A is targeted for 2025 as a foundry offering.[74] This shift emphasizes Intel's focus on achieving process leadership through integrated transistor and power delivery advancements.[75] In Japan, Rapidus Corporation is advancing a 2 nm process through a strategic collaboration with IBM, leveraging licensed nanosheet GAA technology to prototype chips.[76] Backed by significant government funding as part of national semiconductor revitalization efforts, Rapidus unveiled its first 2 nm GAA transistor wafer prototype in July 2025 and plans to commence fab trials in Japan starting in 2026, aiming for mass production by 2027.[77] This initiative positions Rapidus as an emerging player in advanced node manufacturing, supported by partnerships with domestic firms like Sony and Toyota.[78] Research efforts at Imec, Europe's leading nanoelectronics research center, have produced prototypes and a pathfinding process design kit (PDK) for 2 nm node exploration, focusing on nanosheet transistors and beyond-CMOS innovations without plans for commercial fabrication.[79] Collaborations involving GlobalFoundries center on specialty and essential technologies rather than leading-edge logic nodes like 2 nm, with GlobalFoundries maintaining no announced commercial roadmap for such scales.[80] Imec's work emphasizes academic and industrial pathfinding to inform future European semiconductor capabilities.[28] Chinese semiconductor initiatives, particularly at SMIC, are pursuing experimental advancements toward sub-5 nm nodes but face severe constraints from U.S. export sanctions restricting access to extreme ultraviolet (EUV) lithography and advanced tools.[81] As a result, SMIC's current production remains at 7 nm-class processes, with any 2 nm-related research limited to domestic alternatives and significantly delayed by technology gaps.[82] These efforts reflect broader national goals for self-reliance amid geopolitical restrictions.[83]Performance Characteristics
Density and Efficiency Gains
The 2 nm process node achieves significant improvements in transistor density compared to the preceding 3 nm generation, enabling more compact chip designs with greater integration of components. Leading implementations, such as TSMC's N2, deliver a 15% higher logic density compared to its N3E process, with analyst estimates for high-density standard cells reaching approximately 313 million transistors per square millimeter (MTr/mm²).[84][85] Samsung's SF2 process provides approximately 5-15% density scaling over its 3 nm generation (SF3), with estimates around 231 MTr/mm².[86][65] These gains stem from architectural advancements like gate-all-around (GAA) nanosheet transistors, which allow tighter packing without compromising functionality.[87] In terms of energy efficiency, the 2 nm node offers 25-30% power reduction at equivalent performance levels relative to 3 nm, primarily through optimized GAA structures and backside power delivery network (BSPDN) integration in select implementations.[88][89] This efficiency uplift reduces overall energy consumption for logic operations, supporting denser deployments in power-constrained environments.[90] A key logic scaling metric for the 2 nm process is the SRAM bit cell size, which shrinks to enable macro densities up to 38 Mb/mm² in TSMC's N2—a 11% improvement over N3.[91][92] The following table summarizes density comparisons between representative 3 nm and 2 nm processes, focusing on logic, SRAM, and analog scaling (based on mixed-chip metrics including ~20% analog content):| Density Metric | 3 nm (e.g., TSMC N3E) | 2 nm (e.g., TSMC N2) | Scaling Factor |
|---|---|---|---|
| Logic (MTr/mm²) | Baseline | 1.15× | 1.15× |
| SRAM Density (Mb/mm²) | Baseline | 38 | 1.11× |
| Analog Circuitry | Baseline | ~1.1× | 1.1× |